diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-23 11:18:42 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-23 11:18:42 -0500 |
| commit | 03584ad439ce043f2ed7dde51f49e5dbb5ea8bce (patch) | |
| tree | eb6dc23c3076ace7e9522432f3fa6d1bc60c6f71 /tests | |
| parent | d8d6b869a2f34b602cdc216660d08b9acba93d43 (diff) | |
| download | gem5-03584ad439ce043f2ed7dde51f49e5dbb5ea8bce.tar.xz | |
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
Diffstat (limited to 'tests')
4 files changed, 1487 insertions, 1489 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 51c672072..9cd052175 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:40:27 -M5 executing on phenom +M5 compiled Aug 3 2010 18:29:42 +M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch +M5 started Aug 3 2010 18:34:19 +M5 executing on harpertown2 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 125751000 -Exiting @ tick 1907689250500 because m5_exit instruction encountered +Exiting @ tick 1908681362500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 011675055..e9f6d4b39 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,447 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198866 # Simulator instruction rate (inst/s) -host_mem_usage 278256 # Number of bytes of host memory used -host_seconds 282.46 # Real time elapsed on the host -host_tick_rate 6753860070 # Simulator tick rate (ticks/s) +host_inst_rate 149891 # Simulator instruction rate (inst/s) +host_mem_usage 287008 # Number of bytes of host memory used +host_seconds 374.37 # Real time elapsed on the host +host_tick_rate 5098345411 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56171530 # Number of instructions simulated -sim_seconds 1.907689 # Number of seconds simulated -sim_ticks 1907689250500 # Number of ticks simulated +sim_insts 56115151 # Number of instructions simulated +sim_seconds 1.908681 # Number of seconds simulated +sim_ticks 1908681362500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5124021 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 9548324 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 25931 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 576265 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 8953132 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 10665388 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 730260 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 6306789 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 727470 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 6470772 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 12459992 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 36652 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 761921 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 11628226 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 13936368 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 988790 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 8127927 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 948928 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 73665183 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 96210525 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.559994 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.324793 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 55454240 75.28% 75.28% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 8064036 10.95% 86.23% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 4660922 6.33% 92.55% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2129949 2.89% 95.44% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1559149 2.12% 97.56% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 477103 0.65% 98.21% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 293859 0.40% 98.61% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 298455 0.41% 99.01% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 73079830 75.96% 75.96% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 10159186 10.56% 86.52% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5793964 6.02% 92.54% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2862156 2.97% 95.51% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1992019 2.07% 97.59% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 630403 0.66% 98.24% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 376031 0.39% 98.63% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 368008 0.38% 99.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 948928 0.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 73665183 # Number of insts commited each cycle -system.cpu0.commit.COM:count 42069937 # Number of instructions committed -system.cpu0.commit.COM:loads 6784715 # Number of loads committed -system.cpu0.commit.COM:membars 161083 # Number of memory barriers committed -system.cpu0.commit.COM:refs 11506692 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 96210525 # Number of insts commited each cycle +system.cpu0.commit.COM:count 53877339 # Number of instructions committed +system.cpu0.commit.COM:loads 8834098 # Number of loads committed +system.cpu0.commit.COM:membars 219262 # Number of memory barriers committed +system.cpu0.commit.COM:refs 14863142 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 548150 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 42069937 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 486094 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6570892 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 39732534 # Number of Instructions Simulated -system.cpu0.committedInsts_total 39732534 # Number of Instructions Simulated -system.cpu0.cpi 2.659989 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.659989 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 157022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157022 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 723488 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 53877339 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 642718 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 8676299 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 50753913 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50753913 # Number of Instructions Simulated +system.cpu0.cpi 2.598475 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.598475 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 205122 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 205122 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15332.515478 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 143004 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 143004 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 215001000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 14018 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 14018 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3542 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11584.904538 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 183317 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 183317 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 334325500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106303 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 21805 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21805 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4992 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194777000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.081966 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 10476 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 6796922 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6796922 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 16813 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8824783 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8824783 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 24295.121423 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23079.908159 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 5780701 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5780701 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 28500765500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1016221 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1016221 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 272772 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 7389262 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7389262 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 34876157000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.162669 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1435521 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1435521 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 389370 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 24145069000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.118547 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 743449 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 165236 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 165236 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 1046151 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 210601 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 210601 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55488.433658 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 147119 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147119 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 994449500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 18117 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18117 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52488.433658 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 182459 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 182459 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 1561555500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.133627 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 28142 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 28142 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1477129500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.133627 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 18117 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 4544003 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4544003 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 28142 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5803460 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5803460 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 48954.080777 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54100.546465 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 2781940 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2781940 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 86196331165 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1762063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1762063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1458631 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3719396 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3719396 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 102023437400 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.359107 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 2084064 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2084064 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1707487 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 20373021486 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064888 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 303432 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.143990 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 120871 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 376577 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1266172497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9947.496514 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 8.716740 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 127068 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1264008487 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 11340925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 14628243 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11340925 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 14628243 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 38896.516038 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 8562641 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 11108658 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8562641 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 114697096665 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.244979 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 11108658 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 136899594400 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.240602 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2778284 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 3519585 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2778284 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1731403 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 37021374562 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.092310 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 3519585 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 2096857 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 44518090486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.097259 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1046881 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1422728 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.870622 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 445.758667 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 11340925 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.984997 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.015306 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 504.318463 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -7.836780 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 14628243 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11340925 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 41283.431307 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 14628243 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 38896.516038 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 8562641 # number of overall hits +system.cpu0.dcache.overall_hits::0 11108658 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 8562641 # number of overall hits -system.cpu0.dcache.overall_miss_latency 114697096665 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.244979 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 11108658 # number of overall hits +system.cpu0.dcache.overall_miss_latency 136899594400 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.240602 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2778284 # number of overall misses +system.cpu0.dcache.overall_misses::0 3519585 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2778284 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1731403 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 37021374562 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.092310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 3519585 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 2096857 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 44518090486 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.097259 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1046881 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1689051497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1422728 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2189074497 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 987239 # number of replacements -system.cpu0.dcache.sampled_refs 987751 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1343392 # number of replacements +system.cpu0.dcache.sampled_refs 1343785 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 445.758667 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9031985 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 500.400077 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11713425 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 319854 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 35782513 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 28650 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 428056 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 53705173 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 27333196 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9585932 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1147003 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 91050 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 963541 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 873282 # DTB accesses -system.cpu0.dtb.data_acv 817 # DTB access violations -system.cpu0.dtb.data_hits 12339819 # DTB hits -system.cpu0.dtb.data_misses 31654 # DTB misses +system.cpu0.dcache.writebacks 404610 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 46313195 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 39259 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 576703 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 69095576 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 36458125 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 12314815 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1498947 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 124799 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 1124389 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 818221 # DTB accesses +system.cpu0.dtb.data_acv 799 # DTB access violations +system.cpu0.dtb.data_hits 15815368 # DTB hits +system.cpu0.dtb.data_misses 34536 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 648811 # DTB read accesses -system.cpu0.dtb.read_acv 602 # DTB read access violations -system.cpu0.dtb.read_hits 7477600 # DTB read hits -system.cpu0.dtb.read_misses 25745 # DTB read misses -system.cpu0.dtb.write_accesses 224471 # DTB write accesses -system.cpu0.dtb.write_acv 215 # DTB write access violations -system.cpu0.dtb.write_hits 4862219 # DTB write hits -system.cpu0.dtb.write_misses 5909 # DTB write misses -system.cpu0.fetch.Branches 10665388 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6760263 # Number of cache lines fetched -system.cpu0.fetch.Cycles 17500096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 314893 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 54825819 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 690026 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100914 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6760263 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5854281 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.518751 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 74812186 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 609919 # DTB read accesses +system.cpu0.dtb.read_acv 595 # DTB read access violations +system.cpu0.dtb.read_hits 9601809 # DTB read hits +system.cpu0.dtb.read_misses 28742 # DTB read misses +system.cpu0.dtb.write_accesses 208302 # DTB write accesses +system.cpu0.dtb.write_acv 204 # DTB write access violations +system.cpu0.dtb.write_hits 6213559 # DTB write hits +system.cpu0.dtb.write_misses 5794 # DTB write misses +system.cpu0.fetch.Branches 13936368 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 8499965 # Number of cache lines fetched +system.cpu0.fetch.Cycles 22177505 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 429825 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 70536565 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 1947 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 890409 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.105672 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 8499965 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 7459562 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.534843 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 97709472 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.721901 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.017707 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 84062445 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 970614 0.99% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1876169 1.92% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 899130 0.92% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2879231 2.95% 92.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 630716 0.65% 93.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 762992 0.78% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1157633 1.18% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4470542 4.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74812186 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 6760263 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6760263 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15111.361670 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 97709472 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 8499965 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8499965 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14903.591508 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12055.592401 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6055842 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6055842 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 10644760499 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.104200 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 704421 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 704421 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 31973 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 8106758999 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.099471 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11868.979380 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 7487466 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7487466 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 15089871498 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.119118 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 1012499 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1012499 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 44617 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 11487771500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113869 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 672448 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11292.658537 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 967882 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11795.081967 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.007622 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 41 # number of cycles access was blocked +system.cpu0.icache.avg_refs 7.736856 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 61 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 462999 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 719500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 6760263 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 8499965 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6760263 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15111.361670 # average overall miss latency +system.cpu0.icache.demand_accesses::total 8499965 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14903.591508 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6055842 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 7487466 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6055842 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 10644760499 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.104200 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 7487466 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 15089871498 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.119118 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 704421 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 1012499 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 704421 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 31973 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 8106758999 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.099471 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 1012499 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 44617 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 11487771500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.113869 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 672448 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 967882 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995774 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.836147 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 6760263 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995784 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.841410 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 8499965 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6760263 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15111.361670 # average overall miss latency +system.cpu0.icache.overall_accesses::total 8499965 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14903.591508 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6055842 # number of overall hits +system.cpu0.icache.overall_hits::0 7487466 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6055842 # number of overall hits -system.cpu0.icache.overall_miss_latency 10644760499 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.104200 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 7487466 # number of overall hits +system.cpu0.icache.overall_miss_latency 15089871498 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.119118 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 704421 # number of overall misses +system.cpu0.icache.overall_misses::0 1012499 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 704421 # number of overall misses -system.cpu0.icache.overall_mshr_hits 31973 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 8106758999 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.099471 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 1012499 # number of overall misses +system.cpu0.icache.overall_mshr_hits 44617 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 11487771500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.113869 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 672448 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 967882 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 671790 # number of replacements -system.cpu0.icache.sampled_refs 672302 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 967254 # number of replacements +system.cpu0.icache.sampled_refs 967766 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.836147 # Cycle average of tags in use -system.cpu0.icache.total_refs 6055842 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25289603000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 509.841410 # Cycle average of tags in use +system.cpu0.icache.total_refs 7487466 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25290449000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30875932 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6794464 # Number of branches executed -system.cpu0.iew.EXEC:nop 2650714 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.405657 # Inst execution rate -system.cpu0.iew.EXEC:refs 12475412 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4878585 # Number of stores executed +system.cpu0.idleCycles 34173281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8768783 # Number of branches executed +system.cpu0.iew.EXEC:nop 3557044 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.415997 # Inst execution rate +system.cpu0.iew.EXEC:refs 16085074 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 6233455 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 25547065 # num instructions consuming a value -system.cpu0.iew.WB:count 42445288 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.775506 # average fanout of values written-back +system.cpu0.iew.WB:consumers 32865773 # num instructions consuming a value +system.cpu0.iew.WB:count 54347309 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.764091 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 19811901 # num instructions producing a value -system.cpu0.iew.WB:rate 0.401609 # insts written-back per cycle -system.cpu0.iew.WB:sent 42518285 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 591859 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7490199 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 8008916 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1306307 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 773924 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5151785 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 48752960 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7596827 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 385648 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 42873082 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 34285 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 25112440 # num instructions producing a value +system.cpu0.iew.WB:rate 0.412088 # insts written-back per cycle +system.cpu0.iew.WB:sent 54432899 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 782239 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9442019 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 10379600 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1744642 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 949306 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 6581023 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 62660146 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 9851619 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 507857 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 54862889 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 45824 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4894 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1147003 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 462624 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 5354 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1498947 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 539585 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 256589 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 371728 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8138 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 260747 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 417328 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 12574 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 36722 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12836 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1224201 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 429808 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 36722 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 290524 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 301335 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.375941 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.375941 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 29744442 68.76% 68.77% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 44172 0.10% 68.87% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 13702 0.03% 68.90% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.90% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.90% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.90% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1883 0.00% 68.91% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.91% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 7844859 18.13% 87.04% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4914921 11.36% 98.40% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 690973 1.60% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 44391 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18291 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1545502 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 551979 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 44391 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 381079 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 401160 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.384841 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.384841 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 37941800 68.52% 68.53% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 60296 0.11% 68.64% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15720 0.03% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1656 0.00% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 10184712 18.39% 87.06% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 6276896 11.34% 98.40% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 886350 1.60% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 43258732 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 310534 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007179 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 55370746 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 397277 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007175 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 34104 10.98% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 200961 64.71% 75.70% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 75469 24.30% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 49080 12.35% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 256090 64.46% 76.82% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 92107 23.18% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 97709472 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.566688 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.134817 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 52955077 70.78% 70.78% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 11074556 14.80% 85.59% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 4848896 6.48% 92.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 2948908 3.94% 96.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 1827398 2.44% 98.45% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 727506 0.97% 99.43% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 332197 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 81828 0.11% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 70054320 71.70% 71.70% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 13865334 14.19% 85.89% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 6040088 6.18% 92.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3813933 3.90% 95.97% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2397035 2.45% 98.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 977877 1.00% 99.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 439666 0.45% 99.88% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 101836 0.10% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 19383 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 74812186 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.409306 # Inst issue rate -system.cpu0.iq.iqInstsAdded 44617182 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 43258732 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1485064 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6087251 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24441 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 998970 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3229124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 97709472 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.419848 # Inst issue rate +system.cpu0.iq.iqInstsAdded 57116410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 55370746 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1986692 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 7999373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 32356 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1343974 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 4128104 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 930014 # ITB accesses -system.cpu0.itb.fetch_acv 893 # ITB acv -system.cpu0.itb.fetch_hits 898869 # ITB hits -system.cpu0.itb.fetch_misses 31145 # ITB misses +system.cpu0.itb.fetch_accesses 1054719 # ITB accesses +system.cpu0.itb.fetch_acv 886 # ITB acv +system.cpu0.itb.fetch_hits 1025087 # ITB hits +system.cpu0.itb.fetch_misses 29632 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -451,550 +453,550 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2652 1.92% 1.99% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 2.03% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 2.04% # number of callpals executed -system.cpu0.kern.callpal::swpipl 124030 89.84% 91.88% # number of callpals executed -system.cpu0.kern.callpal::rdps 6358 4.61% 96.48% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.48% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.49% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.49% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.50% # number of callpals executed -system.cpu0.kern.callpal::rti 4305 3.12% 99.61% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 138052 # number of callpals executed +system.cpu0.kern.callpal::wripir 98 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3879 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 170561 91.53% 93.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6398 3.43% 97.13% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.13% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.13% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::rti 4815 2.58% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 186345 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 153418 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4853 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 51417 39.39% 39.39% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.18% 39.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1931 1.48% 41.06% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 76919 58.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 130520 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 50665 48.95% 48.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.23% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1931 1.87% 51.05% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 50649 48.94% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 103498 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871325988500 98.09% 98.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 101211000 0.01% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398014500 0.02% 98.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8513500 0.00% 98.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35854604500 1.88% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907688332000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.985374 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201175 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6392 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 72147 40.63% 40.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 239 0.13% 40.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1932 1.09% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 7 0.00% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103229 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 177554 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70781 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 239 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1932 1.34% 50.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 7 0.00% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70775 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 143734 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865669134000 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 102063500 0.01% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 400489500 0.02% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4470500 0.00% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42089413000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1908265570500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981066 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.658472 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.ipl_used::31 0.685612 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 6220 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7354 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.220257 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.174463 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905422249500 99.88% 99.88% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2266074500 0.12% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1906087309000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2155018500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2653 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2188476 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1997712 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 8008916 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5151785 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 105688118 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 11112209 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 28779848 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 792454 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 28590888 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1753238 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16675 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 62049686 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 50763826 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 34216131 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9514762 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1147003 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3857610 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5436281 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 20589712 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1236784 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 9152277 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 192000 # count of temporary serializing insts renamed -system.cpu0.timesIdled 961954 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 3880 # number of times the context was actually changed +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2868331 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2616560 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 10379600 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6581023 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 131882753 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 13878265 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 36623956 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1040563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 38000902 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 2220107 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 18213 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 79075810 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 65194392 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 43691484 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11998481 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1498947 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 5027996 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 7067528 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 27304879 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1597966 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 12274299 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 247715 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1299056 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1953599 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 4355656 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 14923 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 286606 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 4049478 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 4938226 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 376891 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 2617539 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 356362 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 641418 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 1453120 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 4656 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 99987 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 1369738 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 1655319 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 114912 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 786729 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 111651 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 33118489 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 9662936 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.576830 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.391062 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 25969028 78.41% 78.41% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 3179753 9.60% 88.01% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 1522948 4.60% 92.61% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 936064 2.83% 95.44% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 628296 1.90% 97.34% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 237537 0.72% 98.05% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 164527 0.50% 98.55% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 123974 0.37% 98.92% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 7270313 75.24% 75.24% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 1222307 12.65% 87.89% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 443469 4.59% 92.48% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 257393 2.66% 95.14% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 152904 1.58% 96.72% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 87632 0.91% 97.63% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 71404 0.74% 98.37% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 45863 0.47% 98.84% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 111651 1.16% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 33118489 # Number of insts commited each cycle -system.cpu1.commit.COM:count 17440586 # Number of instructions committed -system.cpu1.commit.COM:loads 3166581 # Number of loads committed -system.cpu1.commit.COM:membars 77258 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5179825 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 9662936 # Number of insts commited each cycle +system.cpu1.commit.COM:count 5573873 # Number of instructions committed +system.cpu1.commit.COM:loads 1110708 # Number of loads committed +system.cpu1.commit.COM:membars 18999 # Number of memory barriers committed +system.cpu1.commit.COM:refs 1809440 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 272102 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 17440586 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 227930 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3329840 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 16438996 # Number of Instructions Simulated -system.cpu1.committedInsts_total 16438996 # Number of Instructions Simulated -system.cpu1.cpi 2.304097 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.304097 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 63271 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 63271 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14821.069300 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 95993 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 5573873 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 71139 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1244666 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 5361238 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5361238 # Number of Instructions Simulated +system.cpu1.cpi 2.006382 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.006382 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 15265 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 15265 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14429.127726 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11124.971610 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 52535 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 52535 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 159119000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.169683 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 10736 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10736 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 1930 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97966500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.139179 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10666.666667 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 13981 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 13981 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 18527000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.084114 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 1284 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1284 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 240 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11136000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.068392 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 8806 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 3203716 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3203716 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15842.853412 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 1044 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 1203979 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1203979 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 18427.853599 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12100.517465 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13573.416201 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2644617 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2644617 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 8857723500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.174516 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 559099 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 559099 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 185547 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 4520172500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.116600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1110045 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1110045 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 1731002000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.078020 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 93934 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 93934 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 53146 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 553632500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.033878 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 373552 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298583500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 59498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54415.622389 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 40788 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 15686000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 14051 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 14051 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 45874.534161 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51415.622389 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 45134 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 45134 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 781626000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.241420 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 14364 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 14364 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 738534000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.241420 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 42893.537697 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 11636 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11636 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 110787000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.171874 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2415 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2415 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 103545000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.171803 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 14364 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1946502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1946502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 49498.272766 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 2414 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 679686 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 679686 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 48846.469056 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54160.909528 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 52388.154254 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1381655 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1381655 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 27958950877 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.290186 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 564847 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 564847 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 446490 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 6410322769 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.060805 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 517989 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 517989 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 7898327507 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.237900 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 161697 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 161697 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 135111 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 1392791469 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.039115 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 118357 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526362000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13351.888091 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 9.264017 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 24797 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 331086769 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18500 # number of cycles access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 26586 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 309596000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12811.786863 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 28.408620 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 11875 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 152139969 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 5150218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 1883665 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5150218 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 32756.622095 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 1883665 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 37668.864523 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 4026272 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 1628034 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4026272 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 36816674377 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.218233 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 1628034 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 9629329507 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.135709 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 1123946 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 255631 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1123946 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 632037 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 10930495269 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.095512 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 255631 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 188257 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 1946423969 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.035768 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 491909 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 67374 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.951616 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 487.227171 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 5150218 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.773778 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 396.174503 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 1883665 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5150218 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 32756.622095 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 1883665 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 37668.864523 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 4026272 # number of overall hits +system.cpu1.dcache.overall_hits::0 1628034 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 4026272 # number of overall hits -system.cpu1.dcache.overall_miss_latency 36816674377 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.218233 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 1628034 # number of overall hits +system.cpu1.dcache.overall_miss_latency 9629329507 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.135709 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 1123946 # number of overall misses +system.cpu1.dcache.overall_misses::0 255631 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1123946 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 632037 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 10930495269 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.095512 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 255631 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 188257 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 1946423969 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.035768 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 491909 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 824945500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 67374 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 325282000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 455363 # number of replacements -system.cpu1.dcache.sampled_refs 455691 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 58281 # number of replacements +system.cpu1.dcache.sampled_refs 58793 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 487.227171 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4221529 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 41371153000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 131807 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 15690044 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 15658 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 221514 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 23293804 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 13052984 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4174567 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 566096 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 47077 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 200893 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 379955 # DTB accesses -system.cpu1.dtb.data_acv 65 # DTB access violations -system.cpu1.dtb.data_hits 5542909 # DTB hits -system.cpu1.dtb.data_misses 13981 # DTB misses +system.cpu1.dcache.tagsinuse 396.174503 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1670228 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1884260206000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 26579 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 4231249 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 4060 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 70345 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 7846841 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 3945555 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 1457789 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 213951 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 12437 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 28342 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 436826 # DTB accesses +system.cpu1.dtb.data_acv 92 # DTB access violations +system.cpu1.dtb.data_hits 2033744 # DTB hits +system.cpu1.dtb.data_misses 11106 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 276518 # DTB read accesses -system.cpu1.dtb.read_acv 12 # DTB read access violations -system.cpu1.dtb.read_hits 3445692 # DTB read hits -system.cpu1.dtb.read_misses 11718 # DTB read misses -system.cpu1.dtb.write_accesses 103437 # DTB write accesses -system.cpu1.dtb.write_acv 53 # DTB write access violations -system.cpu1.dtb.write_hits 2097217 # DTB write hits -system.cpu1.dtb.write_misses 2263 # DTB write misses -system.cpu1.fetch.Branches 4938226 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 2741713 # Number of cache lines fetched -system.cpu1.fetch.Cycles 7194016 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 172775 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 23780795 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 326197 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.130375 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 2741713 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2330490 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.627842 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 33684585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 315884 # DTB read accesses +system.cpu1.dtb.read_acv 16 # DTB read access violations +system.cpu1.dtb.read_hits 1299460 # DTB read hits +system.cpu1.dtb.read_misses 8720 # DTB read misses +system.cpu1.dtb.write_accesses 120942 # DTB write accesses +system.cpu1.dtb.write_acv 76 # DTB write access violations +system.cpu1.dtb.write_hits 734284 # DTB write hits +system.cpu1.dtb.write_misses 2386 # DTB write misses +system.cpu1.fetch.Branches 1655319 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 983571 # Number of cache lines fetched +system.cpu1.fetch.Cycles 2495244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 54744 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 8005120 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 119648 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.153887 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 983571 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 756330 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.744199 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 9876887 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.810490 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.152603 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 8372049 84.76% 84.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 99748 1.01% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 205638 2.08% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 130058 1.32% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 234183 2.37% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 78658 0.80% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 103423 1.05% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 71678 0.73% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 581452 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 33684585 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 2741713 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2741713 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14618.155893 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 9876887 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 983571 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 983571 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14895.250407 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11660.018500 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 2328949 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2328949 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6033848499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.150550 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 412764 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 412764 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 18169 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 4600985000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143923 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11864.081295 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 879141 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 879141 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1555511000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.106174 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 104430 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 104430 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 4006 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 1191438500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.102101 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 394595 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11340.909091 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 100424 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6636.363636 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.902933 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu1.icache.avg_refs 8.759351 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 249500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 73000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 2741713 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 983571 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2741713 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14618.155893 # average overall miss latency +system.cpu1.icache.demand_accesses::total 983571 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14895.250407 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 2328949 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 879141 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2328949 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6033848499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.150550 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 879141 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1555511000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.106174 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 412764 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 104430 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 412764 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 18169 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 4600985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.143923 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 104430 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 4006 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1191438500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.102101 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 394595 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 100424 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.984930 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 504.284109 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 2741713 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.866895 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 443.850090 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 983571 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2741713 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14618.155893 # average overall miss latency +system.cpu1.icache.overall_accesses::total 983571 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14895.250407 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 2328949 # number of overall hits +system.cpu1.icache.overall_hits::0 879141 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 2328949 # number of overall hits -system.cpu1.icache.overall_miss_latency 6033848499 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.150550 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 879141 # number of overall hits +system.cpu1.icache.overall_miss_latency 1555511000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.106174 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 412764 # number of overall misses +system.cpu1.icache.overall_misses::0 104430 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 412764 # number of overall misses -system.cpu1.icache.overall_mshr_hits 18169 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 4600985000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.143923 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 104430 # number of overall misses +system.cpu1.icache.overall_mshr_hits 4006 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1191438500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.102101 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 394595 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 100424 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 394030 # number of replacements -system.cpu1.icache.sampled_refs 394541 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 99855 # number of replacements +system.cpu1.icache.sampled_refs 100366 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.284109 # Cycle average of tags in use -system.cpu1.icache.total_refs 2328949 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 54145022000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 443.850090 # Cycle average of tags in use +system.cpu1.icache.total_refs 879141 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897353320500 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4192462 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 2856676 # Number of branches executed -system.cpu1.iew.EXEC:nop 1154303 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.475940 # Inst execution rate -system.cpu1.iew.EXEC:refs 5695199 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2106410 # Number of stores executed +system.cpu1.idleCycles 879803 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 868251 # Number of branches executed +system.cpu1.iew.EXEC:nop 253715 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.554813 # Inst execution rate +system.cpu1.iew.EXEC:refs 2051713 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 739910 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 11059026 # num instructions consuming a value -system.cpu1.iew.WB:count 17811363 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.729393 # average fanout of values written-back +system.cpu1.iew.WB:consumers 3750224 # num instructions consuming a value +system.cpu1.iew.WB:count 5855863 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.732329 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 8066373 # num instructions producing a value -system.cpu1.iew.WB:rate 0.470242 # insts written-back per cycle -system.cpu1.iew.WB:sent 17846809 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 295481 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2247167 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 3784809 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 705322 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 304722 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2229881 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 20840957 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 3588789 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 201614 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 18027204 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 12484 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 2746396 # num instructions producing a value +system.cpu1.iew.WB:rate 0.544393 # insts written-back per cycle +system.cpu1.iew.WB:sent 5874071 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 104878 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 312048 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 1391930 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 267781 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 126811 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 802099 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 6897856 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 1311803 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 68901 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 5967953 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 3132 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2361 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 566096 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 83136 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 1266 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 213951 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 8244 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 73212 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 122514 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 56759 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 34660 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 1926 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 16678 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 6458 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 618228 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 216637 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 16678 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 152685 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 142796 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.434009 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.434009 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3528 0.02% 0.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 11967153 65.65% 65.67% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 27009 0.15% 65.82% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.82% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 12064 0.07% 65.88% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.01% 65.89% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.89% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 3711124 20.36% 86.25% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2127008 11.67% 97.92% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 379173 2.08% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 7014 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 360 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 281222 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 103367 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 7014 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 58993 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 45885 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.498410 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.498410 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3973 0.07% 0.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 3726705 61.73% 61.80% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 10086 0.17% 61.97% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.97% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 10031 0.17% 62.13% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.03% 62.16% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.16% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 1347365 22.32% 84.48% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 752050 12.46% 96.94% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 184660 3.06% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 18228818 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 196946 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010804 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 6036856 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 101607 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.016831 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 13962 7.09% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.09% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 116519 59.16% 66.25% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 66465 33.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 3728 3.67% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 63305 62.30% 65.97% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 34574 34.03% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 9876887 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.611210 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.231461 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 25088136 74.48% 74.48% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 4124812 12.25% 86.72% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1756786 5.22% 91.94% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 1209447 3.59% 95.53% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 865609 2.57% 98.10% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 413218 1.23% 99.33% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 164057 0.49% 99.81% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 50935 0.15% 99.97% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 7028128 71.16% 71.16% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 1406586 14.24% 85.40% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 558070 5.65% 91.05% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 375734 3.80% 94.85% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 282352 2.86% 97.71% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 133259 1.35% 99.06% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 62266 0.63% 99.69% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 26307 0.27% 99.96% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 4185 0.04% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 33684585 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.481263 # Inst issue rate -system.cpu1.iq.iqInstsAdded 18897687 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 18228818 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 788967 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3125649 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 15583 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 561037 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1602623 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 9876887 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.561219 # Inst issue rate +system.cpu1.iq.iqInstsAdded 6356285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 6036856 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 287856 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1234181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 8959 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 216717 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 734853 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 472041 # ITB accesses -system.cpu1.itb.fetch_acv 106 # ITB acv -system.cpu1.itb.fetch_hits 466299 # ITB hits -system.cpu1.itb.fetch_misses 5742 # ITB misses +system.cpu1.itb.fetch_accesses 347409 # ITB accesses +system.cpu1.itb.fetch_acv 92 # ITB acv +system.cpu1.itb.fetch_hits 340665 # ITB hits +system.cpu1.itb.fetch_misses 6744 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1004,95 +1006,95 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1586 2.01% 2.04% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.04% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.05% # number of callpals executed -system.cpu1.kern.callpal::swpipl 71639 90.87% 92.92% # number of callpals executed -system.cpu1.kern.callpal::rdps 2407 3.05% 95.97% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.97% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 95.97% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.98% # number of callpals executed -system.cpu1.kern.callpal::rti 3007 3.81% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.15% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 357 1.17% 1.20% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 25115 82.21% 83.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2369 7.75% 91.20% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.20% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.21% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.22% # number of callpals executed +system.cpu1.kern.callpal::rti 2501 8.19% 99.41% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.45% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 78839 # number of callpals executed +system.cpu1.kern.callpal::total 30551 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 84815 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3812 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 30474 39.75% 39.75% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 2.51% 42.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 96 0.13% 42.39% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 44173 57.61% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 76671 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 29849 48.44% 48.44% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 3.13% 51.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 96 0.16% 51.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 29753 48.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 61626 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872267971000 98.16% 98.16% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 351911000 0.02% 98.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 40319500 0.00% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 34610873000 1.81% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907271074500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979491 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 37164 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2263 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 9735 32.84% 32.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1929 6.51% 39.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 98 0.33% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17882 60.32% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 29644 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9724 45.49% 45.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1929 9.02% 54.51% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 98 0.46% 54.97% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9626 45.03% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 21377 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1880211308500 98.51% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 349210000 0.02% 98.53% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 40269500 0.00% 98.53% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28079728000 1.47% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1908680516000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998870 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.673556 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 424 -system.cpu1.kern.mode_good::user 366 -system.cpu1.kern.mode_good::idle 58 -system.cpu1.kern.mode_switch::kernel 1953 # number of protection mode switches -system.cpu1.kern.mode_switch::user 366 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.217102 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.538307 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 485 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 22 +system.cpu1.kern.mode_switch::kernel 814 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.595823 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028473 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.245575 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 44394454000 2.33% 2.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 886105500 0.05% 2.37% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1861549295500 97.63% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1587 # number of times the context was actually changed -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 820507 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 719564 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 3784809 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2229881 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 37877047 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3238650 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 11736980 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 293624 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 13473240 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 554151 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 942 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 26045586 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 21738411 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 14384581 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 3820320 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 566096 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1590671 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2647601 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 10995606 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 652471 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4381532 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 75403 # count of temporary serializing insts renamed -system.cpu1.timesIdled 422616 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.010753 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.606576 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2177635500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 994853500 0.05% 0.17% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905508019000 99.83% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 358 # number of times the context was actually changed +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 249198 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 232138 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 1391930 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 802099 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 10756690 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 465609 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 3852724 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 44260 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 4077020 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 64277 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 71 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 8954426 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 7268297 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 4874919 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 1341579 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 213951 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 396189 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1022193 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 3382537 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 292831 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 1228786 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 20447 # count of temporary serializing insts renamed +system.cpu1.timesIdled 85032 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1105,282 +1107,282 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115252.862069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63252.862069 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20053998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11005998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137849.677657 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137839.112582 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85846.237437 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727929806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85835.459039 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727490806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3567082858 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566634994 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6166.374068 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6168.251363 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10455 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64487940 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64489068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137755.447539 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137743.123583 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85739.485538 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747983804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747882804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.demand_misses::1 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3578088856 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577822992 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.028124 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.449991 # Average occupied blocks per context +system.iocache.occ_%::1 0.029808 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.476933 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137755.447539 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137743.123583 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85739.485538 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747983804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747882804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.overall_misses::1 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3578088856 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577822992 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41696 # number of replacements -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.replacements 41697 # number of replacements +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.449991 # Cycle average of tags in use +system.iocache.tagsinuse 0.476933 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717168496000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses::0 236243 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 78291 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 314534 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 69731.847293 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 210415.766819 # average ReadExReq miss latency +system.iocache.warmup_cycle 1716189422000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 41520 # number of writebacks +system.l2c.ReadExReq_accesses::0 284402 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21091 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305493 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 56244.064064 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 758424.176568 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40217.604332 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16473660800 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40208.821305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15995924308 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 236243 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 78291 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 314534 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12649803961 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.331400 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 4.017499 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 284402 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 21091 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 305493 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12283513447 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.074159 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 14.484519 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 314534 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1423603 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 771316 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2194919 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53400.832785 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1985457.471546 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 305493 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2026908 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 138381 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2165289 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52781.333033 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3774241.528394 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39990.811057 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.812855 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1119803 # number of ReadReq hits -system.l2c.ReadReq_hits::1 763145 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882948 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16223173000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.213402 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.010594 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 303800 # number of ReadReq misses -system.l2c.ReadReq_misses::1 8171 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311971 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12475173500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.219128 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.404440 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1720929 # number of ReadReq hits +system.l2c.ReadReq_hits::1 134102 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1855031 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16149979500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.150959 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.030922 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 305979 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4279 # number of ReadReq misses +system.l2c.ReadReq_misses::total 310258 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12415436500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.153061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.241926 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 17600 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 13825 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 31425 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 92935.170455 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 118311.681736 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 310240 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840591500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 27679 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 1917 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29596 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 55685.899057 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 804032.342201 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40007.112172 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1635659000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40005.270983 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1541330000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 17600 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 13825 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 31425 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1257223500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.785511 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.273056 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 27679 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 1917 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29596 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1183996000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.069258 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.438706 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 31425 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 68860 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 40587 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 109447 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 80683.066918 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 136887.081775 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 29596 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 95047 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4764 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 99811 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 53254.442497 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 1062484.256087 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40119.011942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5555835988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40129.945597 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5061674996 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 68860 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 40587 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 109447 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4390905500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.589413 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.696602 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 95047 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 4764 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 99811 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4005410000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.050123 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 20.951092 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 109447 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 99811 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 451661 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 451661 # number of Writeback hits -system.l2c.Writeback_hits::total 451661 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1422860998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 431189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 431189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 431189 # number of Writeback hits +system.l2c.Writeback_hits::total 431189 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.797703 # Average number of references to valid blocks. +system.l2c.avg_refs 4.720550 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1659846 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 849607 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2311310 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 159472 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2509453 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 60544.871057 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 378164.208554 # average overall miss latency +system.l2c.demand_accesses::total 2470782 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 54449.421319 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1267083.319196 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency -system.l2c.demand_hits::0 1119803 # number of demand (read+write) hits -system.l2c.demand_hits::1 763145 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency +system.l2c.demand_hits::0 1720929 # number of demand (read+write) hits +system.l2c.demand_hits::1 134102 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1882948 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32696833800 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.325357 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.101767 # miss rate for demand accesses +system.l2c.demand_hits::total 1855031 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32145903808 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255431 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.159087 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 540043 # number of demand (read+write) misses -system.l2c.demand_misses::1 86462 # number of demand (read+write) misses +system.l2c.demand_misses::0 590381 # number of demand (read+write) misses +system.l2c.demand_misses::1 25370 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 626505 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25124977461 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.377436 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.737382 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 615751 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24698949947 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.266400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 3.861073 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 626485 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 615733 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.066802 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.029576 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.372873 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4377.904620 # Average occupied blocks per context -system.l2c.occ_blocks::1 1938.298251 # Average occupied blocks per context -system.l2c.occ_blocks::2 24436.623036 # Average occupied blocks per context -system.l2c.overall_accesses::0 1659846 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 849607 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.092624 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.002915 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.372149 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 6070.232669 # Average occupied blocks per context +system.l2c.occ_blocks::1 191.043265 # Average occupied blocks per context +system.l2c.occ_blocks::2 24389.134195 # Average occupied blocks per context +system.l2c.overall_accesses::0 2311310 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 159472 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2509453 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 60544.871057 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 378164.208554 # average overall miss latency +system.l2c.overall_accesses::total 2470782 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 54449.421319 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1267083.319196 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1119803 # number of overall hits -system.l2c.overall_hits::1 763145 # number of overall hits +system.l2c.overall_hits::0 1720929 # number of overall hits +system.l2c.overall_hits::1 134102 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1882948 # number of overall hits -system.l2c.overall_miss_latency 32696833800 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.325357 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.101767 # miss rate for overall accesses +system.l2c.overall_hits::total 1855031 # number of overall hits +system.l2c.overall_miss_latency 32145903808 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255431 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.159087 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 540043 # number of overall misses -system.l2c.overall_misses::1 86462 # number of overall misses +system.l2c.overall_misses::0 590381 # number of overall misses +system.l2c.overall_misses::1 25370 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 626505 # number of overall misses -system.l2c.overall_mshr_hits 20 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25124977461 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.377436 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.737382 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 615751 # number of overall misses +system.l2c.overall_mshr_hits 18 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24698949947 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.266400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 3.861073 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 626485 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2263111998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 615733 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2263452498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 402176 # number of replacements -system.l2c.sampled_refs 435074 # Sample count of references to valid blocks. +system.l2c.replacements 399449 # number of replacements +system.l2c.sampled_refs 433881 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30752.825907 # Cycle average of tags in use -system.l2c.total_refs 2087356 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278644000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124146 # number of writebacks +system.l2c.tagsinuse 30650.410129 # Cycle average of tags in use +system.l2c.total_refs 2048157 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278771000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 122161 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index dea7a38d9..adcdc6213 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:39:35 -M5 executing on phenom +M5 compiled Aug 3 2010 18:29:42 +M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch +M5 started Aug 3 2010 18:34:19 +M5 executing on harpertown2 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867360295500 because m5_exit instruction encountered +Exiting @ tick 1866391592500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 330dece92..c77305609 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,388 +1,388 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 205161 # Simulator instruction rate (inst/s) -host_mem_usage 276364 # Number of bytes of host memory used -host_seconds 258.74 # Real time elapsed on the host -host_tick_rate 7217130781 # Simulator tick rate (ticks/s) +host_inst_rate 152752 # Simulator instruction rate (inst/s) +host_mem_usage 285144 # Number of bytes of host memory used +host_seconds 347.60 # Real time elapsed on the host +host_tick_rate 5369308609 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53083414 # Number of instructions simulated -sim_seconds 1.867360 # Number of seconds simulated -sim_ticks 1867360295500 # Number of ticks simulated +sim_insts 53097060 # Number of instructions simulated +sim_seconds 1.866392 # Number of seconds simulated +sim_ticks 1866391592500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461193 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6779171 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 13000438 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41604 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 815663 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12121236 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14552347 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1031270 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8463090 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 978521 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 100404039 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.560651 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.326562 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 76371825 75.99% 75.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10652369 10.60% 86.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5995069 5.96% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2948172 2.93% 95.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2094039 2.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 649751 0.65% 98.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 415244 0.41% 98.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 382142 0.38% 99.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 76245214 75.94% 75.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10678082 10.64% 86.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5963966 5.94% 92.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2979105 2.97% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2071048 2.06% 97.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 686360 0.68% 98.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 408066 0.41% 98.63% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 393677 0.39% 99.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 978521 0.97% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle -system.cpu.commit.COM:count 56277376 # Number of instructions committed -system.cpu.commit.COM:loads 9307406 # Number of loads committed -system.cpu.commit.COM:membars 227986 # Number of memory barriers committed -system.cpu.commit.COM:refs 15698987 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 100404039 # Number of insts commited each cycle +system.cpu.commit.COM:count 56291624 # Number of instructions committed +system.cpu.commit.COM:loads 9309237 # Number of loads committed +system.cpu.commit.COM:membars 227993 # Number of memory barriers committed +system.cpu.commit.COM:refs 15703046 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53083414 # Number of Instructions Simulated -system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated -system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 774037 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56291624 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667808 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9441068 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53097060 # Number of Instructions Simulated +system.cpu.committedInsts_total 53097060 # Number of Instructions Simulated +system.cpu.cpi 2.576227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.576227 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15521.971818 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.528617 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192726 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192726 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 343687500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22142 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22142 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4670 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206388500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081315 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17472 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9342824 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9342824 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23958.883948 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22784.089495 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7810369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810369 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36715911500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.164025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1532455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1532455 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 447788 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24713150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116096 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084667 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904940500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219839 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219839 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.793292 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.793292 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 189903 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189903 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1686378500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136172 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29936 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29936 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1596570500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136172 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 29936 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6158819 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6158819 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 48967.756734 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54205.115025 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3929838 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3929838 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109148199373 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.361917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2228981 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2228981 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1831921 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21522682972 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064470 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 397060 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235704997 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9948.209554 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 34000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.830631 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 138723 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1380045474 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 102000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15501643 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15501643 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38778.836294 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11740207 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11740207 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145864110873 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.242648 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3761436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3761436 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2279709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46235832972 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095585 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1481727 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context -system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.015267 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995427 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -7.816935 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15501643 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15501643 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38778.836294 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11736813 # number of overall hits +system.cpu.dcache.overall_hits::0 11740207 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11736813 # number of overall hits -system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11740207 # number of overall hits +system.cpu.dcache.overall_miss_latency 145864110873 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.242648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3764535 # number of overall misses +system.cpu.dcache.overall_misses::0 3761436 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3764535 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3761436 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2279709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46235832972 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095585 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1481727 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140645497 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1401152 # number of replacements -system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401867 # number of replacements +system.cpu.dcache.sampled_refs 1402379 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use -system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 508.086965 # Cycle average of tags in use +system.cpu.dcache.total_refs 12383892 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430200 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1232975 # DTB accesses -system.cpu.dtb.data_acv 823 # DTB access violations -system.cpu.dtb.data_hits 16785642 # DTB hits -system.cpu.dtb.data_misses 44486 # DTB misses +system.cpu.dcache.writebacks 430752 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48365906 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42626 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 618516 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72644608 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37897287 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12992433 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1631262 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 135583 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1148412 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1233977 # DTB accesses +system.cpu.dtb.data_acv 814 # DTB access violations +system.cpu.dtb.data_hits 16773992 # DTB hits +system.cpu.dtb.data_misses 45116 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 911401 # DTB read accesses -system.cpu.dtb.read_acv 582 # DTB read access violations -system.cpu.dtb.read_hits 10188595 # DTB read hits -system.cpu.dtb.read_misses 36193 # DTB read misses -system.cpu.dtb.write_accesses 321574 # DTB write accesses -system.cpu.dtb.write_acv 241 # DTB write access violations -system.cpu.dtb.write_hits 6597047 # DTB write hits -system.cpu.dtb.write_misses 8293 # DTB write misses -system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched -system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 912580 # DTB read accesses +system.cpu.dtb.read_acv 580 # DTB read access violations +system.cpu.dtb.read_hits 10175278 # DTB read hits +system.cpu.dtb.read_misses 36864 # DTB read misses +system.cpu.dtb.write_accesses 321397 # DTB write accesses +system.cpu.dtb.write_acv 234 # DTB write access violations +system.cpu.dtb.write_hits 6598714 # DTB write hits +system.cpu.dtb.write_misses 8252 # DTB write misses +system.cpu.fetch.Branches 14552347 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8974775 # Number of cache lines fetched +system.cpu.fetch.Cycles 23368319 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 459035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74152954 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 956539 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106385 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8974775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7810441 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542093 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 102035301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.726738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.024554 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 87682148 85.93% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1045613 1.02% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1977723 1.94% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 941704 0.92% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2994515 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 665574 0.65% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 793530 0.78% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1216279 1.19% 95.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4718215 4.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 102035301 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8974775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8974775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14904.774114 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.268781 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7927523 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7927523 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15609054500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116688 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1047252 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1047252 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51900 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11853914500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110906 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 995352 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 11612.068966 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.966054 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 673500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8974775 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency +system.cpu.icache.demand_accesses::total 8974775 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14904.774114 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7927523 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7927523 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15609054500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116688 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1047252 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1047252 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51900 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11853914500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.110906 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 995352 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995668 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.782027 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8974775 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency +system.cpu.icache.overall_accesses::total 8974775 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14904.774114 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7937479 # number of overall hits +system.cpu.icache.overall_hits::0 7927523 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7937479 # number of overall hits -system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7927523 # number of overall hits +system.cpu.icache.overall_miss_latency 15609054500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116688 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1046444 # number of overall misses +system.cpu.icache.overall_misses::0 1047252 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1046444 # number of overall misses -system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1047252 # number of overall misses +system.cpu.icache.overall_mshr_hits 51900 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11853914500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.110906 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 995352 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 995232 # number of replacements -system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks. +system.cpu.icache.replacements 994652 # number of replacements +system.cpu.icache.sampled_refs 995163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use -system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.782027 # Cycle average of tags in use +system.cpu.icache.total_refs 7927522 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25287688000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9170733 # Number of branches executed -system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate -system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6620272 # Number of stores executed +system.cpu.idleCycles 34754768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9169930 # Number of branches executed +system.cpu.iew.EXEC:nop 3653116 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.421040 # Inst execution rate +system.cpu.iew.EXEC:refs 17057862 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6621868 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value -system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back +system.cpu.iew.WB:consumers 34608006 # num instructions consuming a value +system.cpu.iew.WB:count 57003958 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763082 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26414846 # num instructions producing a value -system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle -system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26408756 # num instructions producing a value +system.cpu.iew.WB:rate 0.416726 # insts written-back per cycle +system.cpu.iew.WB:sent 57103806 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 838722 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9720732 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11045282 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1800818 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1012071 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7016985 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65863384 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10435994 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 546687 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57594091 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 49608 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6610 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1631262 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 548180 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 312153 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 424842 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8566 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 45938 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15913 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1736045 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 623176 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45938 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 406349 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 432373 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.388165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.388165 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7290 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39624499 68.15% 68.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62169 0.11% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued @@ -390,60 +390,60 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10788203 18.56% 86.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6676137 11.48% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953234 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58140780 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 443526 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007628 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 49984 11.27% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 286610 64.62% 75.89% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 106932 24.11% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 102035301 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569810 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137806 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 73060847 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14641510 14.33% 85.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6377407 6.24% 92.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3918998 3.84% 95.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2506307 2.45% 98.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1046173 1.02% 99.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 456673 0.45% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 116088 0.11% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 72990338 71.53% 71.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14544721 14.25% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6428267 6.30% 92.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3926151 3.85% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2521969 2.47% 98.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1036804 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 448412 0.44% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 110408 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 28231 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate -system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 102035301 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.425037 # Inst issue rate +system.cpu.iq.iqInstsAdded 60158404 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58140780 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2051864 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8719443 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 37043 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1384056 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4669750 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1302209 # ITB accesses -system.cpu.itb.fetch_acv 948 # ITB acv -system.cpu.itb.fetch_hits 1264828 # ITB hits -system.cpu.itb.fetch_misses 37381 # ITB misses +system.cpu.itb.fetch_accesses 1303496 # ITB accesses +system.cpu.itb.fetch_acv 936 # ITB acv +system.cpu.itb.fetch_hits 1264039 # ITB hits +system.cpu.itb.fetch_misses 39457 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -459,7 +459,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::swpipl 175675 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -468,42 +468,42 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192631 # number of callpals executed +system.cpu.kern.callpal::total 192644 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211803 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105940 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183022 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149304 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1823811543000 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102514500 0.01% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392104500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42084556500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1866390718500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.ipl_used::31 0.694629 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5969 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.319987 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 1.401132 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31305722000 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3191321000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1831893667500 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -536,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136912971 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed -system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3074116 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2796142 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11045282 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7016985 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136790069 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14275602 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38263165 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1103259 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39498573 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2244862 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15668 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83383655 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68588182 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45977130 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12625374 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1631262 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5234920 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7713963 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28769568 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1705106 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12848723 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 257016 # count of temporary serializing insts renamed +system.cpu.timesIdled 1324942 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -589,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137775.337072 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85771.897333 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5724840806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3563993878 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6162.366934 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64556956 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137682.056417 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85678.630941 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5744783804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -627,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3574940876 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -635,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context +system.iocache.occ_%::1 0.078734 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.259751 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137682.056417 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85678.630941 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles +system.iocache.overall_miss_latency 5744783804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -656,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3574940876 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -666,152 +666,152 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267376 # Cycle average of tags in use +system.iocache.tagsinuse 1.259751 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716179733000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 301983 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301983 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52369.131153 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40216.934384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15814587333 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses::0 301983 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 301983 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12144830496 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 301983 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2095788 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2095788 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52047.755815 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.737067 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785564 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785564 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16146463000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.148023 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 310224 # number of ReadReq misses +system.l2c.ReadReq_misses::total 310224 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12413802000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.148022 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 29987 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29987 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.338813 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 310223 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810507500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 29936 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29936 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.500401 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.217194 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1568930000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.486505 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1566266500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 29987 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29987 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1199516500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_misses::0 29936 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29936 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1197484500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 29987 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 100109 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 100109 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52260.720754 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 29936 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 99242 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 99242 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52253.672780 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.157488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5231768494 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.292296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5185758994 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 100109 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 100109 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4016989500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 99242 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 99242 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 3982213500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 100109 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 99242 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430200 # number of Writeback hits -system.l2c.Writeback_hits::total 430200 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116157498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 430752 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430752 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430752 # number of Writeback hits +system.l2c.Writeback_hits::total 430752 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.595902 # Average number of references to valid blocks. +system.l2c.avg_refs 4.598953 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2397771 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency +system.l2c.demand_accesses::total 2397771 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52206.280446 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency -system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40114.981715 # average overall mshr miss latency +system.l2c.demand_hits::0 1785564 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses +system.l2c.demand_hits::total 1785564 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31961050333 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255323 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 611922 # number of demand (read+write) misses +system.l2c.demand_misses::0 612207 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 611922 # number of demand (read+write) misses +system.l2c.demand_misses::total 612207 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24558632496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.255323 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 612206 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context -system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context -system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.090384 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.378384 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5923.436811 # Average occupied blocks per context +system.l2c.occ_blocks::1 24797.788563 # Average occupied blocks per context +system.l2c.overall_accesses::0 2397771 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency +system.l2c.overall_accesses::total 2397771 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52206.280446 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40114.981715 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1785718 # number of overall hits +system.l2c.overall_hits::0 1785564 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1785718 # number of overall hits -system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses +system.l2c.overall_hits::total 1785564 # number of overall hits +system.l2c.overall_miss_latency 31961050333 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255323 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 611922 # number of overall misses +system.l2c.overall_misses::0 612207 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 611922 # number of overall misses +system.l2c.overall_misses::total 612207 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24558632496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.255323 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 612206 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926664998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396067 # number of replacements -system.l2c.sampled_refs 427735 # Sample count of references to valid blocks. +system.l2c.replacements 396159 # number of replacements +system.l2c.sampled_refs 427780 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use -system.l2c.total_refs 1965828 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119080 # number of writebacks +system.l2c.tagsinuse 30721.225374 # Cycle average of tags in use +system.l2c.total_refs 1967340 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645112000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119153 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |