diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:14:03 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:14:03 -0700 |
| commit | 5577048bcf1da7f569f055a323efe12535919313 (patch) | |
| tree | 5608506c046e64750edebff65e8b5a7cfffbbbc9 /tests | |
| parent | c2e1458746278b761917f62eb890eefbf4bbc938 (diff) | |
| download | gem5-5577048bcf1da7f569f055a323efe12535919313.tar.xz | |
test: Update stats for python object iteration.
Small changes in tests with data races due to new object creation
order.
Diffstat (limited to 'tests')
32 files changed, 6871 insertions, 6901 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 1abe4a9de..75c83d350 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -5,3 +5,7 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe + +gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 3215ccd26..eb2ca2ce0 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:28:17 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp +M5 compiled Jul 1 2010 14:37:40 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:37:50 +M5 executing on phenom +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 17c7f3b49..78c1b80b2 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,27 +1,27 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1192031 # Simulator instruction rate (inst/s) -host_mem_usage 196580 # Number of bytes of host memory used -host_seconds 1.68 # Real time elapsed on the host -host_tick_rate 440023932 # Simulator tick rate (ticks/s) +host_inst_rate 1240283 # Simulator instruction rate (inst/s) +host_mem_usage 197852 # Number of bytes of host memory used +host_seconds 1.61 # Real time elapsed on the host +host_tick_rate 457858198 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated sim_ticks 738387000 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses @@ -30,38 +30,38 @@ system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180136 # number of overall hits -system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles +system.cpu0.dcache.overall_hits 180140 # number of overall hits +system.cpu0.dcache.overall_miss_latency 35212000 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses system.cpu0.dcache.overall_misses 635 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -69,70 +69,70 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses 0 system.cpu0.dcache.replacements 61 # number of replacements system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 272.921161 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.data_accesses 180789 # DTB accesses +system.cpu0.dtb.data_accesses 180793 # DTB accesses system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_hits 180771 # DTB hits +system.cpu0.dtb.data_hits 180775 # DTB hits system.cpu0.dtb.data_misses 18 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 124440 # DTB read accesses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_hits 124432 # DTB read hits +system.cpu0.dtb.read_hits 124435 # DTB read hits system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.write_accesses 56349 # DTB write accesses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_hits 56339 # DTB write hits +system.cpu0.dtb.write_hits 56340 # DTB write hits system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency -system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.421784 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 215.953225 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.421796 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 215.959580 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 499537 # number of overall hits -system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles +system.cpu0.icache.overall_hits 499557 # number of overall hits +system.cpu0.icache.overall_miss_latency 23479000 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu0.icache.overall_misses 463 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,8 +140,8 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0 system.cpu0.icache.replacements 152 # number of replacements system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use -system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 215.959580 # Cycle average of tags in use +system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0 # Percentage of idle cycles @@ -149,9 +149,9 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 500013 # ITB accesses +system.cpu0.itb.fetch_accesses 500033 # ITB accesses system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_hits 500000 # ITB hits +system.cpu0.itb.fetch_hits 500020 # ITB hits system.cpu0.itb.fetch_misses 13 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -163,63 +163,63 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 1476774 # number of cpu cycles simulated -system.cpu0.num_insts 499981 # Number of instructions executed -system.cpu0.num_refs 182218 # Number of memory references +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 182222 # Number of memory references system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 124109 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_accesses 180772 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180137 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 180772 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180133 # number of overall hits -system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles +system.cpu1.dcache.overall_hits 180137 # number of overall hits +system.cpu1.dcache.overall_miss_latency 35229000 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses system.cpu1.dcache.overall_misses 635 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -227,70 +227,70 @@ system.cpu1.dcache.overall_mshr_uncacheable_misses 0 system.cpu1.dcache.replacements 61 # number of replacements system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 272.916356 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180309 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.data_accesses 180786 # DTB accesses +system.cpu1.dtb.data_accesses 180790 # DTB accesses system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_hits 180768 # DTB hits +system.cpu1.dtb.data_hits 180772 # DTB hits system.cpu1.dtb.data_misses 18 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 124437 # DTB read accesses +system.cpu1.dtb.read_accesses 124441 # DTB read accesses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124429 # DTB read hits +system.cpu1.dtb.read_hits 124433 # DTB read hits system.cpu1.dtb.read_misses 8 # DTB read misses system.cpu1.dtb.write_accesses 56349 # DTB write accesses system.cpu1.dtb.write_acv 0 # DTB write access violations system.cpu1.dtb.write_hits 56339 # DTB write hits system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 499540 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 1078.920086 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency -system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_accesses 500003 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu1.icache.demand_hits 499540 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.421779 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 215.951034 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.421787 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 215.955045 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 500003 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499531 # number of overall hits -system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles +system.cpu1.icache.overall_hits 499540 # number of overall hits +system.cpu1.icache.overall_miss_latency 23482000 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu1.icache.overall_misses 463 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -298,8 +298,8 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0 system.cpu1.icache.replacements 152 # number of replacements system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use -system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 215.955045 # Cycle average of tags in use +system.cpu1.icache.total_refs 499540 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0 # Percentage of idle cycles @@ -307,9 +307,9 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 500007 # ITB accesses +system.cpu1.itb.fetch_accesses 500016 # ITB accesses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_hits 499994 # ITB hits +system.cpu1.itb.fetch_hits 500003 # ITB hits system.cpu1.itb.fetch_misses 13 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -321,23 +321,23 @@ system.cpu1.itb.write_hits 0 # DT system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.numCycles 1476774 # number of cpu cycles simulated -system.cpu1.num_insts 499975 # Number of instructions executed -system.cpu1.num_refs 182214 # Number of memory references +system.cpu1.num_insts 499984 # Number of instructions executed +system.cpu1.num_refs 182219 # Number of memory references system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 124108 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits 56028 # number of WriteReq hits system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses @@ -346,38 +346,38 @@ system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 389.434125 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_accesses 180771 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180136 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 180771 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180140 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles +system.cpu2.dcache.overall_hits 180136 # number of overall hits +system.cpu2.dcache.overall_miss_latency 35230000 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses system.cpu2.dcache.overall_misses 635 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -385,70 +385,70 @@ system.cpu2.dcache.overall_mshr_uncacheable_misses 0 system.cpu2.dcache.replacements 61 # number of replacements system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 272.914158 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180308 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.data_accesses 180793 # DTB accesses +system.cpu2.dtb.data_accesses 180789 # DTB accesses system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_hits 180775 # DTB hits +system.cpu2.dtb.data_hits 180771 # DTB hits system.cpu2.dtb.data_misses 18 # DTB misses system.cpu2.dtb.fetch_accesses 0 # ITB accesses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_accesses 124440 # DTB read accesses system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_hits 124432 # DTB read hits system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_accesses 56349 # DTB write accesses system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_hits 56339 # DTB write hits system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 499537 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 1078.913607 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency -system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency +system.cpu2.icache.demand_hits 499537 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.421796 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 215.959580 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.421784 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 215.953225 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499557 # number of overall hits -system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles +system.cpu2.icache.overall_hits 499537 # number of overall hits +system.cpu2.icache.overall_miss_latency 23485000 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu2.icache.overall_misses 463 # number of overall misses system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -456,8 +456,8 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0 system.cpu2.icache.replacements 152 # number of replacements system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use -system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 215.953225 # Cycle average of tags in use +system.cpu2.icache.total_refs 499537 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks system.cpu2.idle_fraction 0 # Percentage of idle cycles @@ -465,9 +465,9 @@ system.cpu2.itb.data_accesses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_hits 0 # DTB hits system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.fetch_accesses 500033 # ITB accesses +system.cpu2.itb.fetch_accesses 500013 # ITB accesses system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_hits 500020 # ITB hits +system.cpu2.itb.fetch_hits 500000 # ITB hits system.cpu2.itb.fetch_misses 13 # ITB misses system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -479,63 +479,63 @@ system.cpu2.itb.write_hits 0 # DT system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.numCycles 1476774 # number of cpu cycles simulated -system.cpu2.num_insts 500001 # Number of instructions executed -system.cpu2.num_refs 182222 # Number of memory references +system.cpu2.num_insts 499981 # Number of instructions executed +system.cpu2.num_refs 182218 # Number of memory references system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 124105 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 389.427646 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_accesses 180768 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180133 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 180768 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180137 # number of overall hits -system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles +system.cpu3.dcache.overall_hits 180133 # number of overall hits +system.cpu3.dcache.overall_miss_latency 35220000 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses system.cpu3.dcache.overall_misses 635 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -543,70 +543,70 @@ system.cpu3.dcache.overall_mshr_uncacheable_misses 0 system.cpu3.dcache.replacements 61 # number of replacements system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 272.910830 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180305 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.data_accesses 180790 # DTB accesses +system.cpu3.dtb.data_accesses 180786 # DTB accesses system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_hits 180772 # DTB hits +system.cpu3.dtb.data_hits 180768 # DTB hits system.cpu3.dtb.data_misses 18 # DTB misses system.cpu3.dtb.fetch_accesses 0 # ITB accesses system.cpu3.dtb.fetch_acv 0 # ITB acv system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.read_accesses 124441 # DTB read accesses +system.cpu3.dtb.read_accesses 124437 # DTB read accesses system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124433 # DTB read hits +system.cpu3.dtb.read_hits 124429 # DTB read hits system.cpu3.dtb.read_misses 8 # DTB read misses system.cpu3.dtb.write_accesses 56349 # DTB write accesses system.cpu3.dtb.write_acv 0 # DTB write access violations system.cpu3.dtb.write_hits 56339 # DTB write hits system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 499531 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 1078.900648 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency -system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_accesses 499994 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency +system.cpu3.icache.demand_hits 499531 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.421787 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 215.955045 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.421779 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 215.951034 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 499994 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499540 # number of overall hits -system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles +system.cpu3.icache.overall_hits 499531 # number of overall hits +system.cpu3.icache.overall_miss_latency 23504000 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_misses 463 # number of overall misses system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -614,8 +614,8 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0 system.cpu3.icache.replacements 152 # number of replacements system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use -system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 215.951034 # Cycle average of tags in use +system.cpu3.icache.total_refs 499531 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks system.cpu3.idle_fraction 0 # Percentage of idle cycles @@ -623,9 +623,9 @@ system.cpu3.itb.data_accesses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_hits 0 # DTB hits system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.fetch_accesses 500016 # ITB accesses +system.cpu3.itb.fetch_accesses 500007 # ITB accesses system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_hits 500003 # ITB hits +system.cpu3.itb.fetch_hits 499994 # ITB hits system.cpu3.itb.fetch_misses 13 # ITB misses system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.read_acv 0 # DTB read access violations @@ -637,8 +637,8 @@ system.cpu3.itb.write_hits 0 # DT system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.numCycles 1476774 # number of cpu cycles simulated -system.cpu3.num_insts 499984 # Number of instructions executed -system.cpu3.num_refs 182219 # Number of memory references +system.cpu3.num_insts 499975 # Number of instructions executed +system.cpu3.num_refs 182214 # Number of memory references system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) @@ -787,10 +787,10 @@ system.l2c.occ_%::1 0.005650 # Av system.l2c.occ_%::2 0.005650 # Average percentage of cache occupancy system.l2c.occ_%::3 0.005650 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000464 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 370.294638 # Average occupied blocks per context -system.l2c.occ_blocks::1 370.290796 # Average occupied blocks per context -system.l2c.occ_blocks::2 370.305065 # Average occupied blocks per context -system.l2c.occ_blocks::3 370.297695 # Average occupied blocks per context +system.l2c.occ_blocks::0 370.305065 # Average occupied blocks per context +system.l2c.occ_blocks::1 370.297695 # Average occupied blocks per context +system.l2c.occ_blocks::2 370.294638 # Average occupied blocks per context +system.l2c.occ_blocks::3 370.290796 # Average occupied blocks per context system.l2c.occ_blocks::4 30.383926 # Average occupied blocks per context system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 0e7688e7e..fe6b6401b 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout -Redirecting stderr to build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 04:01:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 04:01:52 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +M5 compiled Jul 1 2010 14:40:18 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:40:33 +M5 executing on phenom +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 92d40c8bd..68fb0ebc9 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,612 +1,615 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 56892 # Simulator instruction rate (inst/s) -host_mem_usage 214340 # Number of bytes of host memory used -host_seconds 7.63 # Real time elapsed on the host -host_tick_rate 28431751 # Simulator tick rate (ticks/s) +host_inst_rate 52624 # Simulator instruction rate (inst/s) +host_mem_usage 204896 # Number of bytes of host memory used +host_seconds 8.25 # Real time elapsed on the host +host_tick_rate 26298944 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 434213 # Number of instructions simulated sim_seconds 0.000217 # Number of seconds simulated sim_ticks 217002500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 52073 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 66680 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 68672 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 81408 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 81408 # Number of BP lookups +system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 70853 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 70853 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 25190 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 23275 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 262750 75.72% 75.72% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 55494 15.99% 91.71% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 23803 6.86% 98.57% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 1293 0.37% 98.94% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 820 0.24% 99.18% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 559 0.16% 99.34% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 1671 0.48% 99.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 40 0.01% 99.83% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 264099 71.08% 71.08% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 83154 22.38% 93.46% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 22390 6.03% 99.48% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 687 0.18% 99.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 334 0.09% 99.76% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle -system.cpu0.commit.COM:count 127984 # Number of instructions committed -system.cpu0.commit.COM:loads 30137 # Number of loads committed -system.cpu0.commit.COM:membars 7796 # Number of memory barriers committed -system.cpu0.commit.COM:refs 41570 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle +system.cpu0.commit.COM:count 136879 # Number of instructions committed +system.cpu0.commit.COM:loads 41762 # Number of loads committed +system.cpu0.commit.COM:membars 84 # Number of memory barriers committed +system.cpu0.commit.COM:refs 63149 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 30422 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 127984 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 104211 # Number of Instructions Simulated -system.cpu0.committedInsts_total 104211 # Number of Instructions Simulated -system.cpu0.cpi 3.794734 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.794734 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 28373 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 209 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 57 # number of SwapReq misses -system.cpu0.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu0.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 11234 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 128 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.commit.branchMispredicts 42322 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 136879 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 116789 # Number of Instructions Simulated +system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated +system.cpu0.cpi 3.716155 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.716155 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 24347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 318 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 20768 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 577 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 708.483871 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 162.931818 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 39944 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 39607 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 337 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 45115 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 895 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 39944 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 39607 # number of overall hits -system.cpu0.dcache.overall_miss_latency 7104000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 337 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 53 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 284 # number of overall MSHR misses +system.cpu0.dcache.overall_hits 45115 # number of overall hits +system.cpu0.dcache.overall_miss_latency 36067000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 895 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 467 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 10 # number of replacements +system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 29.152957 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21963 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 141.792519 # Cycle average of tags in use +system.cpu0.dcache.total_refs 28676 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 144226 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 81408 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 81347 # Number of cache lines fetched -system.cpu0.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 412447 # Number of instructions fetch has processed -system.cpu0.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.205860 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 1.042974 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) +system.cpu0.dcache.writebacks 6 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 154431 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 70853 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 87025 # Number of cache lines fetched +system.cpu0.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 457882 # Number of instructions fetch has processed +system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.163254 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 1.055013 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 80599 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 748 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu0.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 86155 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 127.530063 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.avg_refs 128.781764 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 81347 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency -system.cpu0.icache.demand_hits 80599 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.009195 # miss rate for demand accesses -system.cpu0.icache.demand_misses 748 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 87025 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu0.icache.demand_hits 86155 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses +system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.191179 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 97.883584 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 81347 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.526442 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 269.538121 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 87025 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 80599 # number of overall hits -system.cpu0.icache.overall_miss_latency 14184500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.009195 # miss rate for overall accesses -system.cpu0.icache.overall_misses 748 # number of overall misses -system.cpu0.icache.overall_mshr_hits 116 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 632 # number of overall MSHR misses +system.cpu0.icache.overall_hits 86155 # number of overall hits +system.cpu0.icache.overall_miss_latency 32248500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses +system.cpu0.icache.overall_misses 870 # number of overall misses +system.cpu0.icache.overall_mshr_hits 200 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 670 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 522 # number of replacements -system.cpu0.icache.sampled_refs 632 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 363 # number of replacements +system.cpu0.icache.sampled_refs 669 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 97.883584 # Cycle average of tags in use -system.cpu0.icache.total_refs 80599 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 269.538121 # Cycle average of tags in use +system.cpu0.icache.total_refs 86155 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 37149 # Number of branches executed -system.cpu0.iew.EXEC:nop 47058 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.419532 # Inst execution rate -system.cpu0.iew.EXEC:refs 49104 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 13043 # Number of stores executed +system.cpu0.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 44503 # Number of branches executed +system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.434987 # Inst execution rate +system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 22312 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 81150 # num instructions consuming a value -system.cpu0.iew.WB:count 162295 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.931855 # average fanout of values written-back +system.cpu0.iew.WB:consumers 95172 # num instructions consuming a value +system.cpu0.iew.WB:count 187212 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.972912 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 75620 # num instructions producing a value -system.cpu0.iew.WB:rate 0.410403 # insts written-back per cycle -system.cpu0.iew.WB:sent 162544 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 36061 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 165905 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 92594 # num instructions producing a value +system.cpu0.iew.WB:rate 0.431358 # insts written-back per cycle +system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 44335 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 188787 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 698 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.263523 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.263523 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.269095 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.269095 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.57% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 272942 69.93% 69.93% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 69416 17.79% 87.72% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 25173 6.45% 94.16% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 14490 3.71% 97.88% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 162 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 281858 67.78% 67.78% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 66212 15.92% 83.70% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.31% 94.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.24% 99.25% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 926 0.22% 99.90% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 279 0.07% 99.96% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.506068 # Inst issue rate -system.cpu0.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 200126 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 7669 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 92 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 395453 # number of cpu cycles simulated -system.cpu0.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle -system.cpu0.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 131636 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed -system.cpu0.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.534016 # Inst issue rate +system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 19721 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 434006 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 133139 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed +system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 48405 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 65841 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 65870 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 82266 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 82266 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 83669 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 83669 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 25082 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached +system.cpu1.commit.COM:branches 25470 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 257870 74.41% 74.41% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 60023 17.32% 91.73% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 23680 6.83% 98.57% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 1288 0.37% 98.94% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 802 0.23% 99.17% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 567 0.16% 99.33% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 1691 0.49% 99.82% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 39 0.01% 99.83% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 266836 76.21% 76.21% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 54270 15.50% 91.71% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 24066 6.87% 98.58% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 1288 0.37% 98.95% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 810 0.23% 99.18% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 561 0.16% 99.34% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 1684 0.48% 99.82% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 40 0.01% 99.84% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle -system.cpu1.commit.COM:count 132317 # Number of instructions committed -system.cpu1.commit.COM:loads 32415 # Number of loads committed -system.cpu1.commit.COM:membars 5314 # Number of memory barriers committed -system.cpu1.commit.COM:refs 46218 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle +system.cpu1.commit.COM:count 127311 # Number of instructions committed +system.cpu1.commit.COM:loads 29520 # Number of loads committed +system.cpu1.commit.COM:membars 8970 # Number of memory barriers committed +system.cpu1.commit.COM:refs 40059 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 32660 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 132317 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 111128 # Number of Instructions Simulated -system.cpu1.committedInsts_total 111128 # Number of Instructions Simulated -system.cpu1.cpi 3.555675 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 3.555675 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 28295 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 190 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses +system.cpu1.commit.branchMispredicts 29792 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 127311 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 102085 # Number of Instructions Simulated +system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated +system.cpu1.cpi 3.876926 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 3.876926 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 28662 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 204 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 13609 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 10338 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 810.166667 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 701.333333 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 42223 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 41904 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 319 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 39333 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 39000 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 333 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 42223 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 41904 # number of overall hits -system.cpu1.dcache.overall_miss_latency 6082500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 319 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 52 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 267 # number of overall MSHR misses +system.cpu1.dcache.overall_hits 39000 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6895500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 333 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 47 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 286 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 28.067737 # Cycle average of tags in use -system.cpu1.dcache.total_refs 24305 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.232391 # Cycle average of tags in use +system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 145919 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 144955 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 82266 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 80954 # Number of cache lines fetched -system.cpu1.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 435938 # Number of instructions fetch has processed -system.cpu1.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.208197 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.103263 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.Branches 83669 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 82467 # Number of cache lines fetched +system.cpu1.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed +system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.211405 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.037284 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 80218 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 736 # number of ReadReq misses +system.cpu1.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 81734 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 733 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 125.536776 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 128.512579 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 80954 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency -system.cpu1.icache.demand_hits 80218 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.009092 # miss rate for demand accesses -system.cpu1.icache.demand_misses 736 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 82467 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency +system.cpu1.icache.demand_hits 81734 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.008888 # miss rate for demand accesses +system.cpu1.icache.demand_misses 733 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.188794 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 96.662446 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 80954 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.182938 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 93.664377 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 80218 # number of overall hits -system.cpu1.icache.overall_miss_latency 10255000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.009092 # miss rate for overall accesses -system.cpu1.icache.overall_misses 736 # number of overall misses +system.cpu1.icache.overall_hits 81734 # number of overall hits +system.cpu1.icache.overall_miss_latency 10621000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.008888 # miss rate for overall accesses +system.cpu1.icache.overall_misses 733 # number of overall misses system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 639 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 636 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 527 # number of replacements -system.cpu1.icache.sampled_refs 639 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 524 # number of replacements +system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 96.662446 # Cycle average of tags in use -system.cpu1.icache.total_refs 80218 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 93.664377 # Cycle average of tags in use +system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 39408 # Number of branches executed -system.cpu1.iew.EXEC:nop 47237 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.449348 # Inst execution rate -system.cpu1.iew.EXEC:refs 53769 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 15425 # Number of stores executed +system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 36547 # Number of branches executed +system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.410224 # Inst execution rate +system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 12164 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 88234 # num instructions consuming a value -system.cpu1.iew.WB:count 173934 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.937246 # average fanout of values written-back +system.cpu1.iew.WB:consumers 78764 # num instructions consuming a value +system.cpu1.iew.WB:count 158732 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.929676 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 82697 # num instructions producing a value -system.cpu1.iew.WB:rate 0.440189 # insts written-back per cycle -system.cpu1.iew.WB:sent 174194 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute +system.cpu1.iew.WB:producers 73225 # num instructions producing a value +system.cpu1.iew.WB:rate 0.401065 # insts written-back per cycle +system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 38344 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 177553 # Number of executed instructions +system.cpu1.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 35451 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 162357 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing +system.cpu1.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 701 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.281241 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.281241 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.257936 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.257936 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available @@ -621,652 +624,649 @@ system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # at system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 270914 69.00% 69.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 66150 16.85% 85.85% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 30383 7.74% 93.59% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 16859 4.29% 97.88% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 276221 70.31% 70.31% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.17% 88.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.38% 99.27% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.542923 # Inst issue rate -system.cpu1.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 214528 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.495050 # Inst issue rate +system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 10938 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 96 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 395135 # number of cpu cycles simulated -system.cpu1.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle +system.cpu1.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 6760 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 395776 # number of cpu cycles simulated +system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 130989 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed -system.cpu1.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 133245 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed +system.cpu1.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 44089 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 68672 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 52073 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 66680 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 70853 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 70853 # Number of BP lookups +system.cpu2.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect +system.cpu2.BPredUnit.condPredicted 81408 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 81408 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 23275 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 25190 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0 264099 71.08% 71.08% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1 83154 22.38% 93.46% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2 22390 6.03% 99.48% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3 687 0.18% 99.67% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4 334 0.09% 99.76% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0 262750 75.72% 75.72% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1 55494 15.99% 91.71% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2 23803 6.86% 98.57% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3 1293 0.37% 98.94% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4 820 0.24% 99.18% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5 559 0.16% 99.34% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6 1671 0.48% 99.82% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7 40 0.01% 99.83% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle -system.cpu2.commit.COM:count 136879 # Number of instructions committed -system.cpu2.commit.COM:loads 41762 # Number of loads committed -system.cpu2.commit.COM:membars 84 # Number of memory barriers committed -system.cpu2.commit.COM:refs 63149 # Number of memory references committed +system.cpu2.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle +system.cpu2.commit.COM:count 127984 # Number of instructions committed +system.cpu2.commit.COM:loads 30137 # Number of loads committed +system.cpu2.commit.COM:membars 7796 # Number of memory barriers committed +system.cpu2.commit.COM:refs 41570 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.branchMispredicts 42322 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 136879 # The number of committed instructions -system.cpu2.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 116789 # Number of Instructions Simulated -system.cpu2.committedInsts_total 116789 # Number of Instructions Simulated -system.cpu2.cpi 3.716155 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.716155 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 24347 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 318 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 20768 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 577 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked +system.cpu2.commit.branchMispredicts 30422 # The number of times a branch was mispredicted +system.cpu2.commit.commitCommittedInsts 127984 # The number of committed instructions +system.cpu2.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 104211 # Number of Instructions Simulated +system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated +system.cpu2.cpi 3.794734 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.794734 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 28373 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 209 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_misses 57 # number of SwapReq misses +system.cpu2.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 11234 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 128 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 162.931818 # Average number of references to valid blocks. -system.cpu2.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.dcache.avg_refs 708.483871 # Average number of references to valid blocks. +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 46010 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 45115 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 895 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 39944 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 39607 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 337 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 46010 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 45115 # number of overall hits -system.cpu2.dcache.overall_miss_latency 36067000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 895 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 467 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 428 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 39607 # number of overall hits +system.cpu2.dcache.overall_miss_latency 7104000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 337 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 284 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 10 # number of replacements -system.cpu2.dcache.sampled_refs 176 # Sample count of references to valid blocks. +system.cpu2.dcache.replacements 2 # number of replacements +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 141.792519 # Cycle average of tags in use -system.cpu2.dcache.total_refs 28676 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 29.152957 # Cycle average of tags in use +system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 154431 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 70853 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 87025 # Number of cache lines fetched -system.cpu2.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 457882 # Number of instructions fetch has processed -system.cpu2.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.163254 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.055013 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) +system.cpu2.dcache.writebacks 1 # number of writebacks +system.cpu2.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 144226 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 81408 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 81347 # Number of cache lines fetched +system.cpu2.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed +system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.205860 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.042974 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) -system.cpu2.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 86155 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 870 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked +system.cpu2.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) +system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 80599 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 748 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses +system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 128.781764 # Average number of references to valid blocks. -system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu2.icache.avg_refs 127.530063 # Average number of references to valid blocks. +system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 87025 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency -system.cpu2.icache.demand_hits 86155 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.009997 # miss rate for demand accesses -system.cpu2.icache.demand_misses 870 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_accesses 81347 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency +system.cpu2.icache.demand_hits 80599 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.009195 # miss rate for demand accesses +system.cpu2.icache.demand_misses 748 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.526442 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 269.538121 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 87025 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.191179 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 97.883584 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 86155 # number of overall hits -system.cpu2.icache.overall_miss_latency 32248500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.009997 # miss rate for overall accesses -system.cpu2.icache.overall_misses 870 # number of overall misses -system.cpu2.icache.overall_mshr_hits 200 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 670 # number of overall MSHR misses +system.cpu2.icache.overall_hits 80599 # number of overall hits +system.cpu2.icache.overall_miss_latency 14184500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.009195 # miss rate for overall accesses +system.cpu2.icache.overall_misses 748 # number of overall misses +system.cpu2.icache.overall_mshr_hits 116 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 632 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 363 # number of replacements -system.cpu2.icache.sampled_refs 669 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 522 # number of replacements +system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 269.538121 # Cycle average of tags in use -system.cpu2.icache.total_refs 86155 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 97.883584 # Cycle average of tags in use +system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 44503 # Number of branches executed -system.cpu2.iew.EXEC:nop 59775 # number of nop insts executed -system.cpu2.iew.EXEC:rate 0.434987 # Inst execution rate -system.cpu2.iew.EXEC:refs 66647 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 22312 # Number of stores executed +system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 37149 # Number of branches executed +system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed +system.cpu2.iew.EXEC:rate 0.419532 # Inst execution rate +system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 13043 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 95172 # num instructions consuming a value -system.cpu2.iew.WB:count 187212 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.972912 # average fanout of values written-back +system.cpu2.iew.WB:consumers 81150 # num instructions consuming a value +system.cpu2.iew.WB:count 162295 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.931855 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 92594 # num instructions producing a value -system.cpu2.iew.WB:rate 0.431358 # insts written-back per cycle -system.cpu2.iew.WB:sent 187507 # cumulative count of insts sent to commit -system.cpu2.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 44335 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 188787 # Number of executed instructions -system.cpu2.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.WB:producers 75620 # num instructions producing a value +system.cpu2.iew.WB:rate 0.410403 # insts written-back per cycle +system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit +system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu2.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 36061 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 165905 # Number of executed instructions +system.cpu2.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing -system.cpu2.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu2.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing +system.cpu2.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 197 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 0.269095 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.269095 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly +system.cpu2.ipc 0.263523 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.263523 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued -system.cpu2.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued +system.cpu2.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu2.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.57% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0 281858 67.78% 67.78% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1 66212 15.92% 83.70% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2 42876 10.31% 94.01% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3 21783 5.24% 99.25% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5 926 0.22% 99.90% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6 279 0.07% 99.96% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0 272942 69.93% 69.93% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.79% 87.72% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.45% 94.16% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.71% 97.88% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::7 162 0.04% 99.99% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 0.534016 # Inst issue rate -system.cpu2.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 231766 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 19721 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 107 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 434006 # number of cpu cycles simulated -system.cpu2.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle -system.cpu2.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 133139 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed -system.cpu2.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 0.506068 # Inst issue rate +system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 7669 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. +system.cpu2.numCycles 395453 # number of cpu cycles simulated +system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle +system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 131636 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed +system.cpu2.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 53713 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 65870 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 48405 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 65841 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 83669 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 83669 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 82266 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 82266 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 25470 # Number of branches committed -system.cpu3.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached +system.cpu3.commit.COM:branches 25082 # Number of branches committed +system.cpu3.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0 266836 76.21% 76.21% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1 54270 15.50% 91.71% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2 24066 6.87% 98.58% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3 1288 0.37% 98.95% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4 810 0.23% 99.18% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5 561 0.16% 99.34% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6 1684 0.48% 99.82% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::7 40 0.01% 99.84% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0 257870 74.41% 74.41% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1 60023 17.32% 91.73% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2 23680 6.83% 98.57% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3 1288 0.37% 98.94% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4 802 0.23% 99.17% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5 567 0.16% 99.33% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6 1691 0.49% 99.82% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::7 39 0.01% 99.83% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle -system.cpu3.commit.COM:count 127311 # Number of instructions committed -system.cpu3.commit.COM:loads 29520 # Number of loads committed -system.cpu3.commit.COM:membars 8970 # Number of memory barriers committed -system.cpu3.commit.COM:refs 40059 # Number of memory references committed +system.cpu3.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle +system.cpu3.commit.COM:count 132317 # Number of instructions committed +system.cpu3.commit.COM:loads 32415 # Number of loads committed +system.cpu3.commit.COM:membars 5314 # Number of memory barriers committed +system.cpu3.commit.COM:refs 46218 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 29792 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 127311 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 102085 # Number of Instructions Simulated -system.cpu3.committedInsts_total 102085 # Number of Instructions Simulated -system.cpu3.cpi 3.876926 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 3.876926 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 28662 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 204 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses +system.cpu3.commit.branchMispredicts 32660 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 132317 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 111128 # Number of Instructions Simulated +system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated +system.cpu3.cpi 3.555675 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 3.555675 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 28295 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 190 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 10338 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 13609 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 701.333333 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 810.166667 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 39333 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 39000 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 333 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 42223 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 41904 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 319 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 39333 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 39000 # number of overall hits -system.cpu3.dcache.overall_miss_latency 6895500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 333 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 47 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 286 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 41904 # number of overall hits +system.cpu3.dcache.overall_miss_latency 6082500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 319 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 27.232391 # Cycle average of tags in use -system.cpu3.dcache.total_refs 21040 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 28.067737 # Cycle average of tags in use +system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 144955 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 145919 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 83669 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 82467 # Number of cache lines fetched -system.cpu3.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 410532 # Number of instructions fetch has processed -system.cpu3.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.211405 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.037284 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.Branches 82266 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 80954 # Number of cache lines fetched +system.cpu3.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed +system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing +system.cpu3.fetch.branchRate 0.208197 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.103263 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) -system.cpu3.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 81734 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 733 # number of ReadReq misses +system.cpu3.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) +system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 80218 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 736 # number of ReadReq misses system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 128.512579 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 125.536776 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 82467 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency -system.cpu3.icache.demand_hits 81734 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.008888 # miss rate for demand accesses -system.cpu3.icache.demand_misses 733 # number of demand (read+write) misses +system.cpu3.icache.demand_accesses 80954 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency +system.cpu3.icache.demand_hits 80218 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.009092 # miss rate for demand accesses +system.cpu3.icache.demand_misses 736 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.182938 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 93.664377 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 82467 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.188794 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 96.662446 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 81734 # number of overall hits -system.cpu3.icache.overall_miss_latency 10621000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.008888 # miss rate for overall accesses -system.cpu3.icache.overall_misses 733 # number of overall misses +system.cpu3.icache.overall_hits 80218 # number of overall hits +system.cpu3.icache.overall_miss_latency 10255000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.009092 # miss rate for overall accesses +system.cpu3.icache.overall_misses 736 # number of overall misses system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 636 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 639 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 524 # number of replacements -system.cpu3.icache.sampled_refs 636 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 527 # number of replacements +system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 93.664377 # Cycle average of tags in use -system.cpu3.icache.total_refs 81734 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 96.662446 # Cycle average of tags in use +system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 36547 # Number of branches executed -system.cpu3.iew.EXEC:nop 47873 # number of nop insts executed -system.cpu3.iew.EXEC:rate 0.410224 # Inst execution rate -system.cpu3.iew.EXEC:refs 47615 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 12164 # Number of stores executed +system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 39408 # Number of branches executed +system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed +system.cpu3.iew.EXEC:rate 0.449348 # Inst execution rate +system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 15425 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 78764 # num instructions consuming a value -system.cpu3.iew.WB:count 158732 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.929676 # average fanout of values written-back +system.cpu3.iew.WB:consumers 88234 # num instructions consuming a value +system.cpu3.iew.WB:count 173934 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.937246 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 73225 # num instructions producing a value -system.cpu3.iew.WB:rate 0.401065 # insts written-back per cycle -system.cpu3.iew.WB:sent 158983 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute +system.cpu3.iew.WB:producers 82697 # num instructions producing a value +system.cpu3.iew.WB:rate 0.440189 # insts written-back per cycle +system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 35451 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 162357 # Number of executed instructions +system.cpu3.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 38344 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 177553 # Number of executed instructions system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing +system.cpu3.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 694 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 0.257936 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.257936 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly +system.cpu3.ipc 0.281241 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.281241 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available @@ -1281,59 +1281,59 @@ system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # at system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0 276221 70.31% 70.31% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1 71375 18.17% 88.48% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4 5437 1.38% 99.27% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0 270914 69.00% 69.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.85% 85.85% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.74% 93.59% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.29% 97.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 0.495050 # Inst issue rate -system.cpu3.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 195929 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 0.542923 # Inst issue rate +system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 6760 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 87 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 395776 # number of cpu cycles simulated -system.cpu3.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle +system.cpu3.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 10938 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. +system.cpu3.numCycles 395135 # number of cpu cycles simulated +system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 133245 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer -system.cpu3.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed -system.cpu3.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses::0 13 # number of ReadExReq accesses(hits+misses) +system.cpu3.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 130989 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed +system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 528730.769231 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 73122.340426 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 73122.340426 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 528730.769231 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency @@ -1343,62 +1343,62 @@ system.l2c.ReadExReq_miss_rate::1 1 # mi system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 1.393617 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 646 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 653 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 362318.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 4830916.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 63425.601751 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 2229653.846154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 63425.601751 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 2229653.846154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 362318.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 4830916.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 566 # number of ReadReq hits -system.l2c.ReadReq_hits::1 647 # number of ReadReq hits -system.l2c.ReadReq_hits::2 295 # number of ReadReq hits -system.l2c.ReadReq_hits::3 637 # number of ReadReq hits +system.l2c.ReadReq_hits::0 295 # number of ReadReq hits +system.l2c.ReadReq_hits::1 637 # number of ReadReq hits +system.l2c.ReadReq_hits::2 566 # number of ReadReq hits +system.l2c.ReadReq_hits::3 647 # number of ReadReq hits system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.123839 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009188 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.607713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.020000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::0 0.607713 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 80 # number of ReadReq misses -system.l2c.ReadReq_misses::1 6 # number of ReadReq misses -system.l2c.ReadReq_misses::2 457 # number of ReadReq misses -system.l2c.ReadReq_misses::3 13 # number of ReadReq misses +system.l2c.ReadReq_misses::0 457 # number of ReadReq misses +system.l2c.ReadReq_misses::1 13 # number of ReadReq misses +system.l2c.ReadReq_misses::2 80 # number of ReadReq misses +system.l2c.ReadReq_misses::3 6 # number of ReadReq misses system.l2c.ReadReq_misses::total 556 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.854489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.845329 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.734043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 0.849231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.734043 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.849231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.854489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.845329 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 53 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 53 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 59500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 24698.113208 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 62333.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 24698.113208 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 62333.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 62333.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 59500 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles @@ -1407,16 +1407,16 @@ system.l2c.UpgradeReq_miss_rate::1 1 # mi system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 53 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 53 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 5.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.318182 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 2.207547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 2.207547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.318182 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) @@ -1431,88 +1431,88 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 659 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 665 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 846 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 662 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 846 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 385580.645161 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1992166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 65079.854809 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 65079.854809 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1434360 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 385580.645161 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1992166.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency -system.l2c.demand_hits::0 566 # number of demand (read+write) hits -system.l2c.demand_hits::1 647 # number of demand (read+write) hits -system.l2c.demand_hits::2 295 # number of demand (read+write) hits -system.l2c.demand_hits::3 637 # number of demand (read+write) hits +system.l2c.demand_hits::0 295 # number of demand (read+write) hits +system.l2c.demand_hits::1 637 # number of demand (read+write) hits +system.l2c.demand_hits::2 566 # number of demand (read+write) hits +system.l2c.demand_hits::3 647 # number of demand (read+write) hits system.l2c.demand_hits::total 2145 # number of demand (read+write) hits system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.141123 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.027068 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.651300 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.037764 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.651300 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses -system.l2c.demand_misses::0 93 # number of demand (read+write) misses -system.l2c.demand_misses::1 18 # number of demand (read+write) misses -system.l2c.demand_misses::2 551 # number of demand (read+write) misses -system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::0 551 # number of demand (read+write) misses +system.l2c.demand_misses::1 25 # number of demand (read+write) misses +system.l2c.demand_misses::2 93 # number of demand (read+write) misses +system.l2c.demand_misses::3 18 # number of demand (read+write) misses system.l2c.demand_misses::total 687 # number of demand (read+write) misses system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 1.036419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.027068 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0.807329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.031722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.807329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.031722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.036419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.027068 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.001067 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000056 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005570 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.000152 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.005570 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000152 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.001067 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000056 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 69.921003 # Average occupied blocks per context -system.l2c.occ_blocks::1 3.643564 # Average occupied blocks per context -system.l2c.occ_blocks::2 365.031703 # Average occupied blocks per context -system.l2c.occ_blocks::3 9.942146 # Average occupied blocks per context +system.l2c.occ_blocks::0 365.031703 # Average occupied blocks per context +system.l2c.occ_blocks::1 9.942146 # Average occupied blocks per context +system.l2c.occ_blocks::2 69.921003 # Average occupied blocks per context +system.l2c.occ_blocks::3 3.643564 # Average occupied blocks per context system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context -system.l2c.overall_accesses::0 659 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 665 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 846 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 662 # number of overall (read+write) accesses +system.l2c.overall_accesses::0 846 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 662 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 659 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 665 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 385580.645161 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1992166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 65079.854809 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 65079.854809 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1434360 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 385580.645161 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1992166.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 566 # number of overall hits -system.l2c.overall_hits::1 647 # number of overall hits -system.l2c.overall_hits::2 295 # number of overall hits -system.l2c.overall_hits::3 637 # number of overall hits +system.l2c.overall_hits::0 295 # number of overall hits +system.l2c.overall_hits::1 637 # number of overall hits +system.l2c.overall_hits::2 566 # number of overall hits +system.l2c.overall_hits::3 647 # number of overall hits system.l2c.overall_hits::total 2145 # number of overall hits system.l2c.overall_miss_latency 35859000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.141123 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.027068 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.651300 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.037764 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.651300 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.037764 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.141123 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.027068 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses -system.l2c.overall_misses::0 93 # number of overall misses -system.l2c.overall_misses::1 18 # number of overall misses -system.l2c.overall_misses::2 551 # number of overall misses -system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::0 551 # number of overall misses +system.l2c.overall_misses::1 25 # number of overall misses +system.l2c.overall_misses::2 93 # number of overall misses +system.l2c.overall_misses::3 18 # number of overall misses system.l2c.overall_misses::total 687 # number of overall misses system.l2c.overall_mshr_hits 4 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 1.036419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.027068 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0.807329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.031722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.807329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.031722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.036419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.027068 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 683 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 43b76147e..b2a4f9d96 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:16 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +M5 compiled Jul 1 2010 14:40:18 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:40:33 +M5 executing on phenom +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 61e7810b9..41fb8c75a 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1722968 # Simulator instruction rate (inst/s) -host_mem_usage 1115976 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 222951866 # Simulator tick rate (ticks/s) +host_inst_rate 339283 # Simulator instruction rate (inst/s) +host_mem_usage 1120212 # Number of bytes of host memory used +host_seconds 2.00 # Real time elapsed on the host +host_tick_rate 43931389 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated sim_ticks 87713500 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 42192 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu0.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu0.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 15998 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 109 # number of WriteReq misses +system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses +system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits +system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses +system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 27561 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 194 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 58461 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 58190 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 81992 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 271 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -42,48 +42,48 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.055509 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 58461 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 58190 # number of overall hits +system.cpu0.dcache.overall_hits 81992 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 271 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 345 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 9 # number of replacements +system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 28.420699 # Cycle average of tags in use -system.cpu0.dcache.total_refs 33771 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use +system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 167008 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 358 # number of ReadReq misses +system.cpu0.dcache.writebacks 6 # number of writebacks +system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 167366 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.demand_hits 167008 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.002139 # miss rate for demand accesses -system.cpu0.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses +system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -91,62 +91,62 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.146046 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 74.775474 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 167366 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.435073 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 167008 # number of overall hits +system.cpu0.icache.overall_hits 174934 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.002139 # miss rate for overall accesses -system.cpu0.icache.overall_misses 358 # number of overall misses +system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses +system.cpu0.icache.overall_misses 467 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 278 # number of replacements -system.cpu0.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 215 # number of replacements +system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 74.775474 # Cycle average of tags in use -system.cpu0.icache.total_refs 167008 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use +system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.045871 # Percentage of idle cycles -system.cpu0.not_idle_fraction 0.954129 # Percentage of non-idle cycles -system.cpu0.numCycles 173308 # number of cpu cycles simulated -system.cpu0.num_insts 167334 # Number of instructions executed -system.cpu0.num_refs 58537 # Number of memory references +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 175428 # number of cpu cycles simulated +system.cpu0.num_insts 175339 # Number of instructions executed +system.cpu0.num_refs 82398 # Number of memory references system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 41299 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 159 # number of ReadReq misses -system.cpu1.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu1.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 14260 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 102 # number of WriteReq misses +system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 176 # number of ReadReq misses +system.cpu1.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 57 # number of SwapReq misses +system.cpu1.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 12563 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 55820 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses 53313 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits 55559 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits 53031 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 261 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 282 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -154,16 +154,16 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.053884 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 55820 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.056783 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 55559 # number of overall hits +system.cpu1.dcache.overall_hits 53031 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 261 # number of overall misses +system.cpu1.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 282 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -171,31 +171,31 @@ system.cpu1.dcache.overall_mshr_misses 0 # nu system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 27.588376 # Cycle average of tags in use -system.cpu1.dcache.total_refs 30309 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use +system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 166942 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 359 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 167301 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.demand_hits 166942 # number of demand (read+write) hits +system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.002146 # miss rate for demand accesses -system.cpu1.icache.demand_misses 359 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -203,61 +203,61 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.142322 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 72.869097 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 167301 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.149895 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 166942 # number of overall hits +system.cpu1.icache.overall_hits 167072 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.002146 # miss rate for overall accesses -system.cpu1.icache.overall_misses 359 # number of overall misses +system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_misses 358 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 279 # number of replacements -system.cpu1.icache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 278 # number of replacements +system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 72.869097 # Cycle average of tags in use -system.cpu1.icache.total_refs 166942 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use +system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.046241 # Percentage of idle cycles -system.cpu1.not_idle_fraction 0.953759 # Percentage of non-idle cycles -system.cpu1.numCycles 173307 # number of cpu cycles simulated -system.cpu1.num_insts 167269 # Number of instructions executed -system.cpu1.num_refs 55900 # Number of memory references -system.cpu2.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_hits 54431 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 151 # number of ReadReq misses -system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 27 # number of SwapReq misses -system.cpu2.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_hits 27561 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 194 # number of WriteReq misses +system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles +system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles +system.cpu1.numCycles 173308 # number of cpu cycles simulated +system.cpu1.num_insts 167398 # Number of instructions executed +system.cpu1.num_refs 53394 # Number of memory references +system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses +system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_misses 55 # number of SwapReq misses +system.cpu2.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 15998 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 362.347059 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 82337 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses 58461 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.demand_hits 81992 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits 58190 # number of demand (read+write) hits system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 345 # number of demand (read+write) misses +system.cpu2.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 271 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -265,48 +265,48 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.284595 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 82337 # number of overall (read+write) accesses +system.cpu2.dcache.occ_%::0 0.055509 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 81992 # number of overall hits +system.cpu2.dcache.overall_hits 58190 # number of overall hits system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 345 # number of overall misses +system.cpu2.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 271 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 9 # number of replacements -system.cpu2.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu2.dcache.replacements 2 # number of replacements +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 145.712770 # Cycle average of tags in use -system.cpu2.dcache.total_refs 61599 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_hits 174934 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 467 # number of ReadReq misses +system.cpu2.dcache.writebacks 1 # number of writebacks +system.cpu2.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 167008 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 374.591006 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 175401 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses 167366 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.demand_hits 174934 # number of demand (read+write) hits +system.cpu2.icache.demand_hits 167008 # number of demand (read+write) hits system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.002662 # miss rate for demand accesses -system.cpu2.icache.demand_misses 467 # number of demand (read+write) misses +system.cpu2.icache.demand_miss_rate 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -314,61 +314,61 @@ system.cpu2.icache.demand_mshr_misses 0 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.435073 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 222.757301 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 175401 # number of overall (read+write) accesses +system.cpu2.icache.occ_%::0 0.146046 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 74.775474 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 167366 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 174934 # number of overall hits +system.cpu2.icache.overall_hits 167008 # number of overall hits system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.002662 # miss rate for overall accesses -system.cpu2.icache.overall_misses 467 # number of overall misses +system.cpu2.icache.overall_miss_rate 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_misses 358 # number of overall misses system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 215 # number of replacements -system.cpu2.icache.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 278 # number of replacements +system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 222.757301 # Cycle average of tags in use -system.cpu2.icache.total_refs 174934 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use +system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 175428 # number of cpu cycles simulated -system.cpu2.num_insts 175339 # Number of instructions executed -system.cpu2.num_refs 82398 # Number of memory references -system.cpu3.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_hits 40468 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 176 # number of ReadReq misses -system.cpu3.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 57 # number of SwapReq misses -system.cpu3.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_hits 12563 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses +system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles +system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles +system.cpu2.numCycles 173308 # number of cpu cycles simulated +system.cpu2.num_insts 167334 # Number of instructions executed +system.cpu2.num_refs 58537 # Number of memory references +system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 159 # number of ReadReq misses +system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses +system.cpu3.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 14260 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 102 # number of WriteReq misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 960.321429 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 53313 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses 55820 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.demand_hits 53031 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits 55559 # number of demand (read+write) hits system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 282 # number of demand (read+write) misses +system.cpu3.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 261 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -376,16 +376,16 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.056783 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 53313 # number of overall (read+write) accesses +system.cpu3.dcache.occ_%::0 0.053884 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 53031 # number of overall hits +system.cpu3.dcache.overall_hits 55559 # number of overall hits system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 282 # number of overall misses +system.cpu3.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 261 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -393,31 +393,31 @@ system.cpu3.dcache.overall_mshr_misses 0 # nu system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 29.073016 # Cycle average of tags in use -system.cpu3.dcache.total_refs 26889 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_hits 167072 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 358 # number of ReadReq misses +system.cpu3.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 166942 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 167430 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses 167301 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.demand_hits 167072 # number of demand (read+write) hits +system.cpu3.icache.demand_hits 166942 # number of demand (read+write) hits system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.002138 # miss rate for demand accesses -system.cpu3.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu3.icache.demand_miss_rate 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -425,72 +425,72 @@ system.cpu3.icache.demand_mshr_misses 0 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.149895 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 76.746014 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 167430 # number of overall (read+write) accesses +system.cpu3.icache.occ_%::0 0.142322 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 72.869097 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 167301 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 167072 # number of overall hits +system.cpu3.icache.overall_hits 166942 # number of overall hits system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.002138 # miss rate for overall accesses -system.cpu3.icache.overall_misses 358 # number of overall misses +system.cpu3.icache.overall_miss_rate 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_misses 359 # number of overall misses system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 278 # number of replacements -system.cpu3.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 279 # number of replacements +system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 76.746014 # Cycle average of tags in use -system.cpu3.icache.total_refs 167072 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use +system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0.045506 # Percentage of idle cycles -system.cpu3.not_idle_fraction 0.954494 # Percentage of non-idle cycles -system.cpu3.numCycles 173308 # number of cpu cycles simulated -system.cpu3.num_insts 167398 # Number of instructions executed -system.cpu3.num_refs 53394 # Number of memory references -system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles +system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles +system.cpu3.numCycles 173307 # number of cpu cycles simulated +system.cpu3.num_insts 167269 # Number of instructions executed +system.cpu3.num_refs 55900 # Number of memory references +system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 367 # number of ReadReq hits -system.l2c.ReadReq_hits::1 368 # number of ReadReq hits -system.l2c.ReadReq_hits::2 190 # number of ReadReq hits -system.l2c.ReadReq_hits::3 301 # number of ReadReq hits +system.l2c.ReadReq_hits::0 190 # number of ReadReq hits +system.l2c.ReadReq_hits::1 301 # number of ReadReq hits +system.l2c.ReadReq_hits::2 367 # number of ReadReq hits +system.l2c.ReadReq_hits::3 368 # number of ReadReq hits system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.008108 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.008086 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.646840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.186486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 3 # number of ReadReq misses -system.l2c.ReadReq_misses::1 3 # number of ReadReq misses -system.l2c.ReadReq_misses::2 348 # number of ReadReq misses -system.l2c.ReadReq_misses::3 69 # number of ReadReq misses +system.l2c.ReadReq_misses::0 348 # number of ReadReq misses +system.l2c.ReadReq_misses::1 69 # number of ReadReq misses +system.l2c.ReadReq_misses::2 3 # number of ReadReq misses +system.l2c.ReadReq_misses::3 3 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 106 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses @@ -498,9 +498,9 @@ system.l2c.UpgradeReq_miss_rate::1 1 # mi system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 48 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 48 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 106 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) @@ -515,9 +515,9 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency @@ -526,21 +526,21 @@ system.l2c.demand_avg_miss_latency::2 0 # av system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 367 # number of demand (read+write) hits -system.l2c.demand_hits::1 368 # number of demand (read+write) hits -system.l2c.demand_hits::2 190 # number of demand (read+write) hits -system.l2c.demand_hits::3 301 # number of demand (read+write) hits +system.l2c.demand_hits::0 190 # number of demand (read+write) hits +system.l2c.demand_hits::1 301 # number of demand (read+write) hits +system.l2c.demand_hits::2 367 # number of demand (read+write) hits +system.l2c.demand_hits::3 368 # number of demand (read+write) hits system.l2c.demand_hits::total 1226 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.039267 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.039164 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.701727 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.214099 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses -system.l2c.demand_misses::0 15 # number of demand (read+write) misses -system.l2c.demand_misses::1 15 # number of demand (read+write) misses -system.l2c.demand_misses::2 447 # number of demand (read+write) misses -system.l2c.demand_misses::3 82 # number of demand (read+write) misses +system.l2c.demand_misses::0 447 # number of demand (read+write) misses +system.l2c.demand_misses::1 82 # number of demand (read+write) misses +system.l2c.demand_misses::2 15 # number of demand (read+write) misses +system.l2c.demand_misses::3 15 # number of demand (read+write) misses system.l2c.demand_misses::total 559 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles @@ -553,19 +553,19 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.000044 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000029 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.004314 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.001011 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.004314 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.001011 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.000044 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000029 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000098 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 2.865859 # Average occupied blocks per context -system.l2c.occ_blocks::1 1.883074 # Average occupied blocks per context -system.l2c.occ_blocks::2 282.753459 # Average occupied blocks per context -system.l2c.occ_blocks::3 66.228089 # Average occupied blocks per context +system.l2c.occ_blocks::0 282.753459 # Average occupied blocks per context +system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context +system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context -system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses +system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency @@ -575,21 +575,21 @@ system.l2c.overall_avg_miss_latency::3 0 # av system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 367 # number of overall hits -system.l2c.overall_hits::1 368 # number of overall hits -system.l2c.overall_hits::2 190 # number of overall hits -system.l2c.overall_hits::3 301 # number of overall hits +system.l2c.overall_hits::0 190 # number of overall hits +system.l2c.overall_hits::1 301 # number of overall hits +system.l2c.overall_hits::2 367 # number of overall hits +system.l2c.overall_hits::3 368 # number of overall hits system.l2c.overall_hits::total 1226 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.039267 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.039164 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.701727 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.214099 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses -system.l2c.overall_misses::0 15 # number of overall misses -system.l2c.overall_misses::1 15 # number of overall misses -system.l2c.overall_misses::2 447 # number of overall misses -system.l2c.overall_misses::3 82 # number of overall misses +system.l2c.overall_misses::0 447 # number of overall misses +system.l2c.overall_misses::1 82 # number of overall misses +system.l2c.overall_misses::2 15 # number of overall misses +system.l2c.overall_misses::3 15 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index a76dcd8cb..e3768c24f 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:17 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +M5 compiled Jul 1 2010 14:40:18 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:40:36 +M5 executing on phenom +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a432347b0..20f477582 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,563 +1,563 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 920855 # Simulator instruction rate (inst/s) -host_mem_usage 198472 # Number of bytes of host memory used -host_seconds 0.71 # Real time elapsed on the host -host_tick_rate 372636983 # Simulator tick rate (ticks/s) +host_inst_rate 940671 # Simulator instruction rate (inst/s) +host_mem_usage 202704 # Number of bytes of host memory used +host_seconds 0.69 # Real time elapsed on the host +host_tick_rate 380696818 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000263 # Number of seconds simulated sim_ticks 263312000 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 15941.935484 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12941.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 40712 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 2471000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.003793 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 155 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2006000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003793 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 305000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.822581 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 51 # number of SwapReq misses -system.cpu0.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 16022 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 18411.214953 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 15411.214953 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 15915 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 1970000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.006678 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 1649000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.006678 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 48758 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses +system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 41030 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38030 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 24724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 8206000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.008024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 200 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 7606000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008024 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 1200.035714 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 56889 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 16950.381679 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 56627 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 4441000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.004605 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 262 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 35787.292818 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 73482 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 12955000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.004902 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 362 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 3655000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.004605 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 11869000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.004902 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.048480 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 24.821539 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 56889 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.275555 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 141.084106 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 56627 # number of overall hits -system.cpu0.dcache.overall_miss_latency 4441000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.004605 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 262 # number of overall misses +system.cpu0.dcache.overall_hits 73482 # number of overall hits +system.cpu0.dcache.overall_miss_latency 12955000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.004902 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 362 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 3655000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.004605 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 262 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_miss_latency 11869000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.004902 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 9 # number of replacements +system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 24.821539 # Cycle average of tags in use -system.cpu0.dcache.total_refs 33601 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 141.084106 # Cycle average of tags in use +system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.icache.ReadReq_accesses 161568 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14758.379888 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11758.379888 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 161210 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 5283500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.002216 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 4209500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.002216 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses +system.cpu0.dcache.writebacks 6 # number of writebacks +system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 450.307263 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 161568 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14758.379888 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency -system.cpu0.icache.demand_hits 161210 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 5283500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.002216 # miss rate for demand accesses -system.cpu0.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency +system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses +system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 4209500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.002216 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.127582 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 65.321793 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 161568 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.414415 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 212.180630 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 161210 # number of overall hits -system.cpu0.icache.overall_miss_latency 5283500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.002216 # miss rate for overall accesses -system.cpu0.icache.overall_misses 358 # number of overall misses +system.cpu0.icache.overall_hits 157949 # number of overall hits +system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses +system.cpu0.icache.overall_misses 467 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 4209500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.002216 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 278 # number of replacements -system.cpu0.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 215 # number of replacements +system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 65.321793 # Cycle average of tags in use -system.cpu0.icache.total_refs 161210 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.180630 # Cycle average of tags in use +system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.134570 # Percentage of idle cycles -system.cpu0.not_idle_fraction 0.865430 # Percentage of non-idle cycles -system.cpu0.numCycles 515092 # number of cpu cycles simulated -system.cpu0.num_insts 161536 # Number of instructions executed -system.cpu0.num_refs 56961 # Number of memory references +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 526624 # number of cpu cycles simulated +system.cpu0.num_insts 158353 # Number of instructions executed +system.cpu0.num_refs 73905 # Number of memory references system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 16115.384615 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13115.384615 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 40580 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2514000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.003830 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 156 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2046000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003830 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 326000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.830769 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 15453 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 18537.735849 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15537.735849 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 15347 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1965000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.006860 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1647000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.006860 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 38632 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17316.666667 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 38452 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3657000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.004659 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 180 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 3117000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004659 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 180 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 18 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 415000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.783133 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 65 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 8194 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 18489.583333 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15489.583333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 8098 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 1775000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.011716 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 96 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 1120.620690 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 640.392857 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 56189 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 17095.419847 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 55927 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 4479000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.004663 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 262 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 46826 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 19681.159420 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 46550 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 5432000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.005894 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 276 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 3693000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.004663 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 4604000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.005894 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.049924 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 25.561342 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 56189 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.051885 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 26.564950 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 46826 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 55927 # number of overall hits -system.cpu1.dcache.overall_miss_latency 4479000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.004663 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 262 # number of overall misses +system.cpu1.dcache.overall_hits 46550 # number of overall hits +system.cpu1.dcache.overall_miss_latency 5432000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.005894 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 276 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 3693000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.004663 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 262 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_miss_latency 4604000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.005894 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 276 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 25.561342 # Cycle average of tags in use -system.cpu1.dcache.total_refs 32498 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 26.564950 # Cycle average of tags in use +system.cpu1.dcache.total_refs 17931 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.icache.ReadReq_accesses 162202 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14391.364903 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11391.364903 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 161843 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 5166500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.002213 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 4089500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.002213 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 168396 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 21104.748603 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18103.351955 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 168038 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 7555500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.002126 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 6481000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.002126 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 450.816156 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 469.379888 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 162202 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14391.364903 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency -system.cpu1.icache.demand_hits 161843 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 5166500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.002213 # miss rate for demand accesses -system.cpu1.icache.demand_misses 359 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 168396 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 21104.748603 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency +system.cpu1.icache.demand_hits 168038 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 7555500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.002126 # miss rate for demand accesses +system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 4089500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.002213 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 6481000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.002126 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.131739 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 67.450287 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 162202 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.136289 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 69.779720 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 168396 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 161843 # number of overall hits -system.cpu1.icache.overall_miss_latency 5166500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.002213 # miss rate for overall accesses -system.cpu1.icache.overall_misses 359 # number of overall misses +system.cpu1.icache.overall_hits 168038 # number of overall hits +system.cpu1.icache.overall_miss_latency 7555500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.002126 # miss rate for overall accesses +system.cpu1.icache.overall_misses 358 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 4089500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.002213 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 359 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 6481000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.002126 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 358 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 279 # number of replacements -system.cpu1.icache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 278 # number of replacements +system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 67.450287 # Cycle average of tags in use -system.cpu1.icache.total_refs 161843 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 69.779720 # Cycle average of tags in use +system.cpu1.icache.total_refs 168038 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.135045 # Percentage of idle cycles -system.cpu1.not_idle_fraction 0.864955 # Percentage of non-idle cycles -system.cpu1.numCycles 515100 # number of cpu cycles simulated -system.cpu1.num_insts 162170 # Number of instructions executed -system.cpu1.num_refs 56264 # Number of memory references -system.cpu2.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 48758 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 41030 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 38030 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 24724 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 8206000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.008024 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 200 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_miss_latency 7606000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.008024 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses +system.cpu1.idle_fraction 0.134073 # Percentage of idle cycles +system.cpu1.not_idle_fraction 0.865927 # Percentage of non-idle cycles +system.cpu1.numCycles 515096 # number of cpu cycles simulated +system.cpu1.num_insts 168364 # Number of instructions executed +system.cpu1.num_refs 46919 # Number of memory references +system.cpu2.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 40712 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 2471000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.003793 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 155 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_miss_latency 2006000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003793 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu2.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_miss_latency 305000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_rate 0.822581 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_misses 51 # number of SwapReq misses +system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 16022 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 18411.214953 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15411.214953 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 15915 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 1970000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.006678 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 107 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 1649000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006678 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 329.464706 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1200.035714 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 73844 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 35787.292818 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 73482 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 12955000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.004902 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 362 # number of demand (read+write) misses +system.cpu2.dcache.demand_accesses 56889 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 16950.381679 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 56627 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 4441000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.004605 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 262 # number of demand (read+write) misses system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 11869000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.004902 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_miss_latency 3655000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.004605 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.275555 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 141.084106 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 73844 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.048480 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 24.821539 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 56889 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 73482 # number of overall hits -system.cpu2.dcache.overall_miss_latency 12955000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.004902 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 362 # number of overall misses +system.cpu2.dcache.overall_hits 56627 # number of overall hits +system.cpu2.dcache.overall_miss_latency 4441000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.004605 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 262 # number of overall misses system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 11869000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.004902 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 362 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_miss_latency 3655000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.004605 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 9 # number of replacements -system.cpu2.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu2.dcache.replacements 2 # number of replacements +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 141.084106 # Cycle average of tags in use -system.cpu2.dcache.total_refs 56009 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 24.821539 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33601 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 157949 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses +system.cpu2.dcache.writebacks 1 # number of writebacks +system.cpu2.icache.ReadReq_accesses 161568 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 14758.379888 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 11758.379888 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 161210 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 5283500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.002216 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_miss_latency 4209500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.002216 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 338.220557 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 450.307263 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 158416 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu2.icache.demand_hits 157949 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.002948 # miss rate for demand accesses -system.cpu2.icache.demand_misses 467 # number of demand (read+write) misses +system.cpu2.icache.demand_accesses 161568 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 14758.379888 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency +system.cpu2.icache.demand_hits 161210 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 5283500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.002216 # miss rate for demand accesses +system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_miss_latency 4209500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.002216 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.414415 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 212.180630 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 158416 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.127582 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 65.321793 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 161568 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 157949 # number of overall hits -system.cpu2.icache.overall_miss_latency 18524000 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.002948 # miss rate for overall accesses -system.cpu2.icache.overall_misses 467 # number of overall misses +system.cpu2.icache.overall_hits 161210 # number of overall hits +system.cpu2.icache.overall_miss_latency 5283500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.002216 # miss rate for overall accesses +system.cpu2.icache.overall_misses 358 # number of overall misses system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 467 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_miss_latency 4209500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.002216 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 358 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 215 # number of replacements -system.cpu2.icache.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 278 # number of replacements +system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 212.180630 # Cycle average of tags in use -system.cpu2.icache.total_refs 157949 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.321793 # Cycle average of tags in use +system.cpu2.icache.total_refs 161210 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 526624 # number of cpu cycles simulated -system.cpu2.num_insts 158353 # Number of instructions executed -system.cpu2.num_refs 73905 # Number of memory references -system.cpu3.dcache.ReadReq_accesses 38632 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 20316.666667 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 17316.666667 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 38452 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 3657000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.004659 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 180 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 3117000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004659 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 180 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 18 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 415000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.783133 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 65 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 8194 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 18489.583333 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15489.583333 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 8098 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 1775000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.011716 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 1487000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses +system.cpu2.idle_fraction 0.134570 # Percentage of idle cycles +system.cpu2.not_idle_fraction 0.865430 # Percentage of non-idle cycles +system.cpu2.numCycles 515092 # number of cpu cycles simulated +system.cpu2.num_insts 161536 # Number of instructions executed +system.cpu2.num_refs 56961 # Number of memory references +system.cpu3.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 40580 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 2514000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.003830 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 156 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_miss_latency 2046000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003830 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 326000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.830769 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 15453 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 18537.735849 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15537.735849 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 15347 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 1965000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.006860 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1647000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006860 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 640.392857 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1120.620690 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 46826 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 19681.159420 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 46550 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 5432000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.005894 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 276 # number of demand (read+write) misses +system.cpu3.dcache.demand_accesses 56189 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 17095.419847 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 55927 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 4479000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.004663 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 262 # number of demand (read+write) misses system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 4604000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.005894 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_miss_latency 3693000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.004663 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 262 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.051885 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 26.564950 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 46826 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.049924 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 25.561342 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 56189 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 46550 # number of overall hits -system.cpu3.dcache.overall_miss_latency 5432000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.005894 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 276 # number of overall misses +system.cpu3.dcache.overall_hits 55927 # number of overall hits +system.cpu3.dcache.overall_miss_latency 4479000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.004663 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 262 # number of overall misses system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 4604000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.005894 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 276 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_miss_latency 3693000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.004663 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 262 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 26.564950 # Cycle average of tags in use -system.cpu3.dcache.total_refs 17931 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.561342 # Cycle average of tags in use +system.cpu3.dcache.total_refs 32498 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.icache.ReadReq_accesses 168396 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 21104.748603 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 18103.351955 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 168038 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 7555500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.002126 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 6481000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.002126 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_accesses 162202 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14391.364903 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11391.364903 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 161843 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 5166500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_miss_latency 4089500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 469.379888 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 450.816156 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 168396 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 21104.748603 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency -system.cpu3.icache.demand_hits 168038 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 7555500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.002126 # miss rate for demand accesses -system.cpu3.icache.demand_misses 358 # number of demand (read+write) misses +system.cpu3.icache.demand_accesses 162202 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14391.364903 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency +system.cpu3.icache.demand_hits 161843 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 5166500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.002213 # miss rate for demand accesses +system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 6481000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.002126 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_miss_latency 4089500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.136289 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 69.779720 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 168396 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.131739 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 67.450287 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 162202 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 168038 # number of overall hits -system.cpu3.icache.overall_miss_latency 7555500 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.002126 # miss rate for overall accesses -system.cpu3.icache.overall_misses 358 # number of overall misses +system.cpu3.icache.overall_hits 161843 # number of overall hits +system.cpu3.icache.overall_miss_latency 5166500 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.002213 # miss rate for overall accesses +system.cpu3.icache.overall_misses 359 # number of overall misses system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 6481000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.002126 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_miss_latency 4089500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.002213 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 278 # number of replacements -system.cpu3.icache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 279 # number of replacements +system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 69.779720 # Cycle average of tags in use -system.cpu3.icache.total_refs 168038 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.450287 # Cycle average of tags in use +system.cpu3.icache.total_refs 161843 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0.134073 # Percentage of idle cycles -system.cpu3.not_idle_fraction 0.865927 # Percentage of non-idle cycles -system.cpu3.numCycles 515096 # number of cpu cycles simulated -system.cpu3.num_insts 168364 # Number of instructions executed -system.cpu3.num_refs 46919 # Number of memory references -system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.cpu3.idle_fraction 0.135045 # Percentage of idle cycles +system.cpu3.not_idle_fraction 0.864955 # Percentage of non-idle cycles +system.cpu3.numCycles 515100 # number of cpu cycles simulated +system.cpu3.num_insts 162170 # Number of instructions executed +system.cpu3.num_refs 56264 # Number of memory references +system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 589333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 589333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 71434.343434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 544000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 71434.343434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 544000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 589333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 589333.333333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 1794101.010101 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 7072000 # number of ReadExReq miss cycles @@ -566,62 +566,62 @@ system.l2c.ReadExReq_miss_rate::1 1 # mi system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5440000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 11.333333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 11.333333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 1.373737 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.461538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1.373737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 10.461538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 11.333333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 11.333333 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 34.501943 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 136 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 3183285.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 5570750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 63484.330484 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 332582.089552 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 63484.330484 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 332582.089552 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 3183285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 5570750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 9150102.134322 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40007.092199 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 363 # number of ReadReq hits -system.l2c.ReadReq_hits::1 367 # number of ReadReq hits -system.l2c.ReadReq_hits::2 187 # number of ReadReq hits -system.l2c.ReadReq_hits::3 303 # number of ReadReq hits +system.l2c.ReadReq_hits::0 187 # number of ReadReq hits +system.l2c.ReadReq_hits::1 303 # number of ReadReq hits +system.l2c.ReadReq_hits::2 363 # number of ReadReq hits +system.l2c.ReadReq_hits::3 367 # number of ReadReq hits system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits system.l2c.ReadReq_miss_latency 22283000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.018919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.010782 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.652416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.181081 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::0 0.652416 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.181081 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.018919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.010782 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.863198 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 7 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4 # number of ReadReq misses -system.l2c.ReadReq_misses::2 351 # number of ReadReq misses -system.l2c.ReadReq_misses::3 67 # number of ReadReq misses +system.l2c.ReadReq_misses::0 351 # number of ReadReq misses +system.l2c.ReadReq_misses::1 67 # number of ReadReq misses +system.l2c.ReadReq_misses::2 7 # number of ReadReq misses +system.l2c.ReadReq_misses::3 4 # number of ReadReq misses system.l2c.ReadReq_misses::total 429 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 16923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 1.143243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.140162 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.786245 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.786245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.140162 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 4.212894 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 47 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 91 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 65000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 65000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 22127.659574 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 86666.666667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 22127.659574 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 86666.666667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 65000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 65000 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 238794.326241 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles @@ -630,16 +630,16 @@ system.l2c.UpgradeReq_miss_rate::1 1 # mi system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 47 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 47 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 16 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 91 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 3640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 5.687500 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.687500 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 1.936170 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 7.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.936170 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 7.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 5.687500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.687500 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 20.894504 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 91 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) @@ -654,87 +654,87 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 1545000 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1834687.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 65233.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 65233.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 366937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 1545000 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1834687.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency -system.l2c.demand_hits::0 363 # number of demand (read+write) hits -system.l2c.demand_hits::1 367 # number of demand (read+write) hits -system.l2c.demand_hits::2 187 # number of demand (read+write) hits -system.l2c.demand_hits::3 303 # number of demand (read+write) hits +system.l2c.demand_hits::0 187 # number of demand (read+write) hits +system.l2c.demand_hits::1 303 # number of demand (read+write) hits +system.l2c.demand_hits::2 363 # number of demand (read+write) hits +system.l2c.demand_hits::3 367 # number of demand (read+write) hits system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.demand_miss_latency 29355000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.049738 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.041775 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.706436 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.208877 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.706436 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.208877 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.049738 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.041775 # miss rate for demand accesses system.l2c.demand_miss_rate::total 1.006827 # miss rate for demand accesses -system.l2c.demand_misses::0 19 # number of demand (read+write) misses -system.l2c.demand_misses::1 16 # number of demand (read+write) misses -system.l2c.demand_misses::2 450 # number of demand (read+write) misses -system.l2c.demand_misses::3 80 # number of demand (read+write) misses +system.l2c.demand_misses::0 450 # number of demand (read+write) misses +system.l2c.demand_misses::1 80 # number of demand (read+write) misses +system.l2c.demand_misses::2 19 # number of demand (read+write) misses +system.l2c.demand_misses::3 16 # number of demand (read+write) misses system.l2c.demand_misses::total 565 # number of demand (read+write) misses system.l2c.demand_mshr_hits 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 22363000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 1.463351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.877551 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 1.459530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0.877551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.463351 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::3 1.459530 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 5.259962 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 559 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.000040 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000026 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.004171 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.000879 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.004171 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000879 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.000040 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000026 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000085 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 2.602775 # Average occupied blocks per context -system.l2c.occ_blocks::1 1.727475 # Average occupied blocks per context -system.l2c.occ_blocks::2 273.330650 # Average occupied blocks per context -system.l2c.occ_blocks::3 57.582989 # Average occupied blocks per context +system.l2c.occ_blocks::0 273.330650 # Average occupied blocks per context +system.l2c.occ_blocks::1 57.582989 # Average occupied blocks per context +system.l2c.occ_blocks::2 2.602775 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.727475 # Average occupied blocks per context system.l2c.occ_blocks::4 5.583152 # Average occupied blocks per context -system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses +system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 1545000 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1834687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 65233.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 65233.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 366937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 1545000 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1834687.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 363 # number of overall hits -system.l2c.overall_hits::1 367 # number of overall hits -system.l2c.overall_hits::2 187 # number of overall hits -system.l2c.overall_hits::3 303 # number of overall hits +system.l2c.overall_hits::0 187 # number of overall hits +system.l2c.overall_hits::1 303 # number of overall hits +system.l2c.overall_hits::2 363 # number of overall hits +system.l2c.overall_hits::3 367 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.overall_miss_latency 29355000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.049738 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.041775 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.706436 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.208877 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.706436 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.208877 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.049738 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.041775 # miss rate for overall accesses system.l2c.overall_miss_rate::total 1.006827 # miss rate for overall accesses -system.l2c.overall_misses::0 19 # number of overall misses -system.l2c.overall_misses::1 16 # number of overall misses -system.l2c.overall_misses::2 450 # number of overall misses -system.l2c.overall_misses::3 80 # number of overall misses +system.l2c.overall_misses::0 450 # number of overall misses +system.l2c.overall_misses::1 80 # number of overall misses +system.l2c.overall_misses::2 19 # number of overall misses +system.l2c.overall_misses::3 16 # number of overall misses system.l2c.overall_misses::total 565 # number of overall misses system.l2c.overall_mshr_hits 6 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 22363000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 1.463351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.877551 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 1.459530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0.877551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.463351 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::3 1.459530 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 5.259962 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 559 # number of overall MSHR misses diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini index d4c356ae3..e8166d3de 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini @@ -22,7 +22,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest @@ -37,7 +37,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest @@ -52,7 +52,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest @@ -67,7 +67,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest @@ -82,7 +82,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest @@ -97,7 +97,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest @@ -112,7 +112,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest @@ -127,7 +127,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports7.port[0] [system.funcmem] type=PhysicalMemory @@ -147,11 +147,11 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer block_size_bytes=64 clock=1 debug=system.ruby.debug @@ -164,6 +164,102 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + [system.ruby.debug] type=RubyDebug filter_string=none @@ -202,41 +298,28 @@ weight=1 [system.ruby.network.topology.ext_links0.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports0 to_l2_latency=1 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -254,41 +337,28 @@ weight=1 [system.ruby.network.topology.ext_links1.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports1 to_l2_latency=1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -306,41 +376,28 @@ weight=1 [system.ruby.network.topology.ext_links2.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports2 to_l2_latency=1 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -358,41 +415,28 @@ weight=1 [system.ruby.network.topology.ext_links3.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports3 to_l2_latency=1 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -410,41 +454,28 @@ weight=1 [system.ruby.network.topology.ext_links4.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports4 to_l2_latency=1 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -462,41 +493,28 @@ weight=1 [system.ruby.network.topology.ext_links5.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports5 to_l2_latency=1 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -514,41 +532,28 @@ weight=1 [system.ruby.network.topology.ext_links6.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports6 to_l2_latency=1 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -566,41 +571,28 @@ weight=1 [system.ruby.network.topology.ext_links7.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports7 to_l2_latency=1 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 3e866be1e..813d40bbf 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:37:29 +Real time: Jul/01/2010 14:40:21 Profiler Stats -------------- -Elapsed_time_in_seconds: 43 -Elapsed_time_in_minutes: 0.716667 -Elapsed_time_in_hours: 0.0119444 -Elapsed_time_in_days: 0.000497685 +Elapsed_time_in_seconds: 36 +Elapsed_time_in_minutes: 0.6 +Elapsed_time_in_hours: 0.01 +Elapsed_time_in_days: 0.000416667 -Virtual_time_in_seconds: 42.96 -Virtual_time_in_minutes: 0.716 -Virtual_time_in_hours: 0.0119333 -Virtual_time_in_days: 0.000497222 +Virtual_time_in_seconds: 35.01 +Virtual_time_in_minutes: 0.5835 +Virtual_time_in_hours: 0.009725 +Virtual_time_in_days: 0.000405208 -Ruby_current_time: 3719757 +Ruby_current_time: 3725190 Ruby_start_time: 0 -Ruby_cycles: 3719757 +Ruby_cycles: 3725190 -mbytes_resident: 31.1289 -mbytes_total: 332.066 -resident_ratio: 0.0937548 +mbytes_resident: 32.2461 +mbytes_total: 324.797 +resident_ratio: 0.0992928 -ruby_cycles_executed: [ 3719758 3719758 3719758 3719758 3719758 3719758 3719758 3719758 ] +ruby_cycles_executed: [ 3725191 3725191 3725191 3725191 3725191 3725191 3725191 3725191 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,13 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1207997 average: 1.94937 | standard deviation: 0.21925 | 0 61165 1146832 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1208922 average: 1.94905 | standard deviation: 0.219893 | 0 61593 1147329 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1096 count: 1207982 average: 47.2632 | standard deviation: 87.5809 | 820246 0 0 12973 11256 8994 17847 40609 25225 42554 9212 3741 16692 9471 11172 15656 163 11587 19417 8757 12623 971 6786 8002 7495 3787 2265 8848 5127 7731 3455 937 5328 4126 3619 4052 242 2825 4110 2460 2617 358 2236 2202 2247 1258 401 1959 1336 1484 1007 157 1157 1014 866 802 80 656 659 574 477 94 467 375 407 241 42 307 241 254 168 29 168 140 127 117 15 95 111 93 72 14 78 46 65 41 3 33 33 22 18 7 19 17 14 7 1 8 7 15 10 1 2 3 5 3 1 6 6 1 1 3 3 5 4 1 0 2 1 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 989 count: 785672 average: 30.8191 | standard deviation: 72.2854 | 626312 0 0 2843 2491 355 17847 15354 10445 19140 268 3733 7267 2205 5283 5517 159 5561 8454 3320 4992 966 1947 3616 2571 478 2264 3550 2053 3343 615 937 2397 1381 1550 1485 241 1150 1699 921 935 357 794 905 854 257 400 756 504 634 249 157 485 391 373 252 80 258 275 208 141 94 188 157 165 65 42 119 96 102 50 29 65 60 50 36 15 39 46 35 16 14 31 23 26 18 3 18 12 6 5 7 5 7 5 2 1 2 2 9 4 1 2 1 3 0 1 4 3 1 1 3 3 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 1096 count: 422310 average: 77.856 | standard deviation: 103.83 | 193934 0 0 10130 8765 8639 0 25255 14780 23414 8944 8 9425 7266 5889 10139 4 6026 10963 5437 7631 5 4839 4386 4924 3309 1 5298 3074 4388 2840 0 2931 2745 2069 2567 1 1675 2411 1539 1682 1 1442 1297 1393 1001 1 1203 832 850 758 0 672 623 493 550 0 398 384 366 336 0 279 218 242 176 0 188 145 152 118 0 103 80 77 81 0 56 65 58 56 0 47 23 39 23 0 15 21 16 13 0 14 10 9 5 0 6 5 6 6 0 0 2 2 3 0 2 3 0 0 0 0 4 3 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1236 count: 1208906 average: 47.2964 | standard deviation: 87.6519 | 820562 0 0 12801 11531 8846 17926 41165 25176 42518 9192 3581 16689 9654 11109 15654 179 11470 19382 8928 12543 981 6769 7960 7766 3717 2229 8680 5114 7916 3472 918 5454 4144 3683 4067 204 2886 3913 2437 2740 403 2323 2099 2111 1159 428 1944 1349 1530 988 155 1089 1034 847 865 77 656 640 552 475 81 515 444 389 282 37 336 235 215 200 29 194 171 135 105 16 91 109 70 51 12 63 49 53 38 4 44 29 26 30 3 26 26 25 12 1 4 10 9 7 0 6 7 5 2 0 6 0 5 2 0 1 2 2 0 0 4 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 8 max: 1236 count: 786532 average: 30.7984 | standard deviation: 72.1119 | 626837 0 0 2820 2557 350 17926 15549 10430 19240 248 3575 7162 2230 5155 5701 177 5572 8288 3522 5103 977 2062 3583 2648 426 2229 3471 2058 3348 603 916 2377 1392 1591 1434 204 1177 1674 955 944 403 807 863 826 242 427 778 533 622 262 154 497 367 346 296 77 256 272 197 140 81 186 164 136 73 37 145 91 95 67 29 71 72 56 30 16 38 34 35 14 12 23 17 19 10 4 17 9 7 8 3 13 8 9 4 1 0 4 1 1 0 1 3 2 2 0 2 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 8 max: 1156 count: 422374 average: 78.0186 | standard deviation: 104.189 | 193725 0 0 9981 8974 8496 0 25616 14746 23278 8944 6 9527 7424 5954 9953 2 5898 11094 5406 7440 4 4707 4377 5118 3291 0 5209 3056 4568 2869 2 3077 2752 2092 2633 0 1709 2239 1482 1796 0 1516 1236 1285 917 1 1166 816 908 726 1 592 667 501 569 0 400 368 355 335 0 329 280 253 209 0 191 144 120 133 0 123 99 79 75 0 53 75 35 37 0 40 32 34 28 0 27 20 19 22 0 13 18 16 8 0 4 6 8 6 0 5 4 3 0 0 4 0 4 2 0 0 2 1 0 0 3 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -87,12 +87,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1070 count: 1901917 average: 23.6676 | standard deviation: 66.5163 | 1605803 77057 36746 50742 28570 31081 16600 13024 11911 7715 8177 3975 2999 2315 1628 1395 701 445 347 259 191 78 56 23 29 17 9 14 5 0 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1192255 average: 0.00257328 | standard deviation: 0.0573328 | 1189606 2240 399 10 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1070 count: 709662 average: 63.4255 | standard deviation: 96.6231 | 413548 77057 36746 50742 28570 31081 16600 13024 11911 7715 8177 3975 2999 2315 1628 1395 701 445 347 259 191 78 56 23 29 17 9 14 5 0 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 32 max: 1210 count: 1905105 average: 23.6634 | standard deviation: 66.5532 | 1608990 76937 36796 50533 28576 31102 16782 13165 11810 7909 7836 4054 2949 2343 1644 1494 693 507 326 210 185 91 78 27 23 21 7 5 5 2 0 2 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1194440 average: 0.00238773 | standard deviation: 0.054808 | 1191946 2149 332 13 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 1210 count: 710665 average: 63.4314 | standard deviation: 96.7027 | 414550 76937 36796 50533 28576 31102 16782 13165 11810 7909 7836 4054 2949 2343 1644 1494 693 507 326 210 185 91 78 27 23 21 7 5 5 2 0 2 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 469671 average: 0.00546127 | standard deviation: 0.0851706 | 467524 1739 398 10 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 722584 average: 0.000696113 | standard deviation: 0.0264364 | 722082 501 1 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 470535 average: 0.00501132 | standard deviation: 0.0808664 | 468529 1667 326 13 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 723905 average: 0.00068241 | standard deviation: 0.0264384 | 723417 482 6 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -103,240 +103,240 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1192255 average: 0.00257328 Resource Usage -------------- page_size: 4096 -user_time: 42 +user_time: 34 system_time: 0 -page_reclaims: 8989 +page_reclaims: 8476 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 16 +block_outputs: 88 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.416622 - links_utilized_percent_switch_0_link_0: 0.1753 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.657944 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.416862 + links_utilized_percent_switch_0_link_0: 0.175057 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.658668 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Request_Control: 59677 477416 [ 59677 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 47767 3439224 [ 0 47767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 32078 256624 [ 0 32078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 49180 393440 [ 49180 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 40975 2950200 [ 0 40975 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 71523 572184 [ 0 30612 40911 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Request_Control: 59786 478288 [ 59786 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 47776 3439872 [ 0 47776 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 31925 255400 [ 0 31925 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 49209 393672 [ 49209 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 41091 2958552 [ 0 41091 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 71705 573640 [ 0 30706 40999 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.413921 - links_utilized_percent_switch_1_link_0: 0.174086 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.653756 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.417081 + links_utilized_percent_switch_1_link_0: 0.174646 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.659515 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 59368 474944 [ 59368 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 47459 3417048 [ 0 47459 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 31548 252384 [ 0 31548 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 48980 391840 [ 48980 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 40679 2928888 [ 0 40679 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 71272 570176 [ 0 30597 40675 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 59730 477840 [ 59730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 47651 3430872 [ 0 47651 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 31883 255064 [ 0 31883 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 49127 393016 [ 49127 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 41190 2965680 [ 0 41190 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 71527 572216 [ 0 30620 40907 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.408998 - links_utilized_percent_switch_2_link_0: 0.173244 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.644752 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.411516 + links_utilized_percent_switch_2_link_0: 0.173509 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.649523 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 58740 469920 [ 58740 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 47251 3402072 [ 0 47251 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 31542 252336 [ 0 31542 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 48715 389720 [ 48715 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 40048 2883456 [ 0 40048 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 70517 564136 [ 0 30181 40336 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 59117 472936 [ 59117 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 47372 3410784 [ 0 47372 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 48775 390200 [ 48775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 40476 2914272 [ 0 40476 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 70860 566880 [ 0 30387 40473 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.411754 - links_utilized_percent_switch_3_link_0: 0.172789 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.65072 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.41051 + links_utilized_percent_switch_3_link_0: 0.172967 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.648053 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Request_Control: 58992 471936 [ 58992 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 47078 3389616 [ 0 47078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 48495 387960 [ 48495 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 40552 2919744 [ 0 40552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 70641 565128 [ 0 30354 40287 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Request_Control: 58969 471752 [ 58969 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 47235 3400920 [ 0 47235 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 31383 251064 [ 0 31383 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 48705 389640 [ 48705 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 40369 2906568 [ 0 40369 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 70798 566384 [ 0 30334 40464 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.410354 - links_utilized_percent_switch_4_link_0: 0.172598 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.64811 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.409606 + links_utilized_percent_switch_4_link_0: 0.172646 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.646567 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Request_Control: 58702 469616 [ 58702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 46983 3382776 [ 0 46983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 32068 256544 [ 0 32068 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 48464 387712 [ 48464 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 40376 2907072 [ 0 40376 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 70314 562512 [ 0 30046 40268 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Request_Control: 58775 470200 [ 58775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 47067 3388824 [ 0 47067 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 32132 257056 [ 0 32132 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 48558 388464 [ 48558 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 40298 2901456 [ 0 40298 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 70477 563816 [ 0 30185 40292 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.406591 - links_utilized_percent_switch_5_link_0: 0.170992 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.642191 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.405919 + links_utilized_percent_switch_5_link_0: 0.171186 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.640652 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 58275 466200 [ 58275 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 46593 3354696 [ 0 46593 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 31226 249808 [ 0 31226 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 47996 383968 [ 47996 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 39989 2879208 [ 0 39989 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 69862 558896 [ 0 29968 39894 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 58294 466352 [ 58294 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 46694 3361968 [ 0 46694 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 48108 384864 [ 48108 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 39921 2874312 [ 0 39921 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 69913 559304 [ 0 29973 39940 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.403555 - links_utilized_percent_switch_6_link_0: 0.170507 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.636603 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.403773 + links_utilized_percent_switch_6_link_0: 0.170945 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.636601 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Request_Control: 57883 463064 [ 57883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 46461 3345192 [ 0 46461 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 47887 383096 [ 47887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 39582 2849904 [ 0 39582 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 69477 555816 [ 0 29723 39754 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Request_Control: 58092 464736 [ 58092 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 46651 3358872 [ 0 46651 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 48107 384856 [ 48107 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 39615 2852280 [ 0 39615 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 69650 557200 [ 0 29918 39732 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.404768 - links_utilized_percent_switch_7_link_0: 0.170843 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.638692 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.401324 + links_utilized_percent_switch_7_link_0: 0.17008 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.632569 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Request_Control: 58034 464272 [ 58034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 46530 3350160 [ 0 46530 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 31591 252728 [ 0 31591 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 48033 384264 [ 48033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 39723 2860056 [ 0 39723 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 69616 556928 [ 0 29815 39801 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Request_Control: 57772 462176 [ 57772 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 46420 3342240 [ 0 46420 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 31312 250496 [ 0 31312 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 47770 382160 [ 47770 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 39360 2833920 [ 0 39360 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 69278 554224 [ 0 29764 39514 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 1.37857 - links_utilized_percent_switch_8_link_0: 0.521419 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 2.23573 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 1.37991 + links_utilized_percent_switch_8_link_0: 0.521364 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 2.23846 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 387750 3102000 [ 387750 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 93552 6735744 [ 0 93552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 321925 2575400 [ 0 0 321925 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 388358 3106864 [ 388358 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 93674 6744528 [ 0 93674 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 322320 2578560 [ 0 0 322320 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 321925 2575400 [ 321925 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 147748 10637856 [ 0 147748 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 11614 92912 [ 0 11614 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 322321 2578568 [ 322321 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 148215 10671480 [ 0 148215 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 11479 91832 [ 0 11479 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.24336e-05 - links_utilized_percent_switch_9_link_0: 6.72087e-07 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.41951e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.24155e-05 + links_utilized_percent_switch_9_link_0: 6.71107e-07 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.41598e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.760712 - links_utilized_percent_switch_10_link_0: 0.701199 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.696345 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.692977 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.691155 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.690391 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.683967 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.68203 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.683371 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 2.08568 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 2.68835e-06 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 59677 477416 [ 59677 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 47767 3439224 [ 0 47767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 32078 256624 [ 0 32078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 59368 474944 [ 59368 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 47459 3417048 [ 0 47459 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 31548 252384 [ 0 31548 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 58740 469920 [ 58740 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 47251 3402072 [ 0 47251 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 31542 252336 [ 0 31542 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 58992 471936 [ 58992 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 47078 3389616 [ 0 47078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 58702 469616 [ 58702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 46983 3382776 [ 0 46983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 32068 256544 [ 0 32068 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 58275 466200 [ 58275 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 46593 3354696 [ 0 46593 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 31226 249808 [ 0 31226 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 57883 463064 [ 57883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 46461 3345192 [ 0 46461 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 58034 464272 [ 58034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 46530 3350160 [ 0 46530 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 31591 252728 [ 0 31591 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 387750 3102000 [ 387750 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 93552 6735744 [ 0 93552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 321925 2575400 [ 0 0 321925 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.76096 + links_utilized_percent_switch_10_link_0: 0.700226 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.698585 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.694037 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.691867 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.690582 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.684742 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.683781 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.68032 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 2.08546 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 2.68443e-06 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 59786 478288 [ 59786 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 47776 3439872 [ 0 47776 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 31925 255400 [ 0 31925 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 59730 477840 [ 59730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 47651 3430872 [ 0 47651 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 31883 255064 [ 0 31883 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 59117 472936 [ 59117 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 47372 3410784 [ 0 47372 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 58969 471752 [ 58969 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 47235 3400920 [ 0 47235 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 31383 251064 [ 0 31383 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 58775 470200 [ 58775 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 47067 3388824 [ 0 47067 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 32132 257056 [ 0 32132 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 58294 466352 [ 58294 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 46694 3361968 [ 0 46694 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 31619 252952 [ 0 31619 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 58092 464736 [ 58092 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 46651 3358872 [ 0 46651 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 57772 462176 [ 57772 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 46420 3342240 [ 0 46420 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 31312 250496 [ 0 31312 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 388359 3106872 [ 388359 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 93674 6744528 [ 0 93674 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 322321 2578568 [ 0 0 322321 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 0 --- - Event Counts - -Load 99861 +Load 100001 Ifetch 0 -Store 53771 -Inv 30612 +Store 53802 +Inv 30706 L1_Replacement 0 -Fwd_GETX 17155 -Fwd_GETS 11910 +Fwd_GETX 17069 +Fwd_GETS 12011 Fwd_GET_INSTR 0 -Data 10502 +Data 10461 Data_Exclusive 0 -DataS_fromL1 11846 -Data_all_Acks 25419 -Ack 20165 -Ack_all 11913 +DataS_fromL1 11918 +Data_all_Acks 25397 +Ack 20032 +Ack_all 11893 WB_Ack 0 - Transitions - -NP Load 1 +NP Load 2 NP Ifetch 0 <-- -NP Store 1 +NP Store 0 <-- NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 20113 +I Load 20126 I Ifetch 0 <-- -I Store 11009 +I Store 10788 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 33892 +S Load 34065 S Ifetch 0 <-- -S Store 18056 -S Inv 11768 +S Store 18293 +S Inv 11715 S L1_Replacement 0 <-- E Load 0 <-- @@ -348,40 +348,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 45855 +M Load 45808 M Ifetch 0 <-- -M Store 24705 +M Store 24721 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 17155 -M Fwd_GETS 11910 +M Fwd_GETX 17069 +M Fwd_GETS 12011 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2199 +IS Inv 2130 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11846 -IS Data_all_Acks 6068 +IS DataS_fromL1 11918 +IS Data_all_Acks 6079 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10502 -IM Data_all_Acks 17152 +IM Data 10461 +IM Data_all_Acks 17188 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16645 +SM Inv 16861 SM L1_Replacement 0 <-- -SM Ack 20165 -SM Ack_all 11913 +SM Ack 20032 +SM Ack_all 11893 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -390,7 +390,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2199 +IS_I Data_all_Acks 2130 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -407,40 +407,40 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 1 --- - Event Counts - -Load 100000 +Load 99730 Ifetch 0 -Store 53094 -Inv 30597 +Store 53653 +Inv 30620 L1_Replacement 0 -Fwd_GETX 16861 -Fwd_GETS 11910 +Fwd_GETX 17030 +Fwd_GETS 12080 Fwd_GET_INSTR 0 -Data 10170 +Data 10364 Data_Exclusive 0 -DataS_fromL1 11904 -Data_all_Acks 25385 -Ack 19858 -Ack_all 11690 +DataS_fromL1 11797 +Data_all_Acks 25490 +Ack 20045 +Ack_all 11838 WB_Ack 0 - Transitions - @@ -450,16 +450,16 @@ NP Store 2 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 20208 +I Load 20015 I Ifetch 0 <-- -I Store 10728 +I Store 10764 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 34188 +S Load 33729 S Ifetch 0 <-- -S Store 18042 -S Inv 11866 +S Store 18346 +S Inv 11564 S L1_Replacement 0 <-- E Load 0 <-- @@ -471,40 +471,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 45604 +M Load 45986 M Ifetch 0 <-- -M Store 24322 +M Store 24541 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16861 -M Fwd_GETS 11910 +M Fwd_GETX 17030 +M Fwd_GETS 12080 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2209 +IS Inv 2185 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11904 -IS Data_all_Acks 6095 +IS DataS_fromL1 11797 +IS Data_all_Acks 6033 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10170 -IM Data_all_Acks 17081 +IM Data 10364 +IM Data_all_Acks 17272 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16522 +SM Inv 16871 SM L1_Replacement 0 <-- -SM Ack 19858 -SM Ack_all 11690 +SM Ack 20045 +SM Ack_all 11838 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -513,7 +513,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2209 +IS_I Data_all_Acks 2185 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -530,40 +530,40 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 2 --- - Event Counts - -Load 98032 +Load 99194 Ifetch 0 -Store 52759 -Inv 30181 +Store 53073 +Inv 30387 L1_Replacement 0 -Fwd_GETX 17070 -Fwd_GETS 11489 +Fwd_GETX 16984 +Fwd_GETS 11746 Fwd_GET_INSTR 0 -Data 10282 +Data 10273 Data_Exclusive 0 -DataS_fromL1 11777 -Data_all_Acks 25192 -Ack 19798 -Ack_all 11744 +DataS_fromL1 11743 +Data_all_Acks 25356 +Ack 19945 +Ack_all 11674 WB_Ack 0 - Transitions - @@ -573,16 +573,16 @@ NP Store 1 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 20153 +I Load 20042 I Ifetch 0 <-- -I Store 10822 +I Store 10810 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 32864 +S Load 33640 S Ifetch 0 <-- -S Store 17738 -S Inv 11696 +S Store 17921 +S Inv 11754 S L1_Replacement 0 <-- E Load 0 <-- @@ -594,40 +594,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 45014 +M Load 45511 M Ifetch 0 <-- -M Store 24198 +M Store 24341 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 17070 -M Fwd_GETS 11489 +M Fwd_GETX 16984 +M Fwd_GETS 11746 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2209 +IS Inv 2114 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11777 -IS Data_all_Acks 6168 +IS DataS_fromL1 11743 +IS Data_all_Acks 6186 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10282 -IM Data_all_Acks 16815 +IM Data 10273 +IM Data_all_Acks 17056 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16276 +SM Inv 16519 SM L1_Replacement 0 <-- -SM Ack 19798 -SM Ack_all 11744 +SM Ack 19945 +SM Ack_all 11674 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -636,7 +636,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2209 +IS_I Data_all_Acks 2114 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -653,59 +653,59 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 3 --- - Event Counts - -Load 98574 +Load 98276 Ifetch 0 -Store 52923 -Inv 30354 +Store 53109 +Inv 30334 L1_Replacement 0 -Fwd_GETX 16724 -Fwd_GETS 11914 +Fwd_GETX 16901 +Fwd_GETS 11734 Fwd_GET_INSTR 0 -Data 10232 +Data 10144 Data_Exclusive 0 -DataS_fromL1 11649 -Data_all_Acks 25197 -Ack 19845 -Ack_all 11647 +DataS_fromL1 11829 +Data_all_Acks 25262 +Ack 19771 +Ack_all 11612 WB_Ack 0 - Transitions - -NP Load 2 +NP Load 1 NP Ifetch 0 <-- -NP Store 0 <-- +NP Store 1 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 19854 +I Load 20068 I Ifetch 0 <-- -I Store 10574 +I Store 10669 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 33422 +S Load 33256 S Ifetch 0 <-- -S Store 18065 -S Inv 11545 +S Store 17966 +S Inv 11705 S L1_Replacement 0 <-- E Load 0 <-- @@ -717,40 +717,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 45296 +M Load 44951 M Ifetch 0 <-- -M Store 24284 +M Store 24473 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16724 -M Fwd_GETS 11914 +M Fwd_GETX 16901 +M Fwd_GETS 11734 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2159 +IS Inv 2131 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11649 -IS Data_all_Acks 6047 +IS DataS_fromL1 11829 +IS Data_all_Acks 6108 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10232 -IM Data_all_Acks 16991 +IM Data 10144 +IM Data_all_Acks 17023 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16650 +SM Inv 16498 SM L1_Replacement 0 <-- -SM Ack 19845 -SM Ack_all 11647 +SM Ack 19771 +SM Ack_all 11612 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -759,7 +759,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2159 +IS_I Data_all_Acks 2131 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -776,59 +776,59 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 4 --- - Event Counts - -Load 97813 +Load 98292 Ifetch 0 -Store 53065 -Inv 30046 +Store 52852 +Inv 30185 L1_Replacement 0 -Fwd_GETX 16936 -Fwd_GETS 11720 +Fwd_GETX 16882 +Fwd_GETS 11708 Fwd_GET_INSTR 0 -Data 10345 +Data 10341 Data_Exclusive 0 -DataS_fromL1 11611 -Data_all_Acks 25027 -Ack 20243 -Ack_all 11825 +DataS_fromL1 11702 +Data_all_Acks 25024 +Ack 20302 +Ack_all 11830 WB_Ack 0 - Transitions - -NP Load 0 <-- +NP Load 2 NP Ifetch 0 <-- -NP Store 2 +NP Store 0 <-- NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 19807 +I Load 19965 I Ifetch 0 <-- -I Store 10748 +I Store 10757 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 32839 +S Load 33223 S Ifetch 0 <-- -S Store 17907 -S Inv 11513 +S Store 17834 +S Inv 11737 S L1_Replacement 0 <-- E Load 0 <-- @@ -840,40 +840,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 45167 +M Load 45102 M Ifetch 0 <-- -M Store 24408 +M Store 24261 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16936 -M Fwd_GETS 11720 +M Fwd_GETX 16882 +M Fwd_GETS 11708 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2106 +IS Inv 2103 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11611 -IS Data_all_Acks 6089 +IS DataS_fromL1 11702 +IS Data_all_Acks 6161 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10345 -IM Data_all_Acks 16832 +IM Data 10341 +IM Data_all_Acks 16760 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16427 +SM Inv 16345 SM L1_Replacement 0 <-- -SM Ack 20243 -SM Ack_all 11825 +SM Ack 20302 +SM Ack_all 11830 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -882,7 +882,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2106 +IS_I Data_all_Acks 2103 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -899,40 +899,40 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 5 --- - Event Counts - -Load 97539 +Load 97731 Ifetch 0 -Store 52365 -Inv 29968 +Store 52263 +Inv 29973 L1_Replacement 0 -Fwd_GETX 16625 -Fwd_GETS 11682 +Fwd_GETX 16721 +Fwd_GETS 11600 Fwd_GET_INSTR 0 -Data 10163 +Data 10293 Data_Exclusive 0 -DataS_fromL1 11587 -Data_all_Acks 24843 -Ack 19662 -Ack_all 11564 +DataS_fromL1 11619 +Data_all_Acks 24782 +Ack 19914 +Ack_all 11705 WB_Ack 0 - Transitions - @@ -942,16 +942,16 @@ NP Store 1 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 19687 +I Load 19786 I Ifetch 0 <-- -I Store 10596 +I Store 10688 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 33227 +S Load 33197 S Ifetch 0 <-- -S Store 17711 -S Inv 11590 +S Store 17632 +S Inv 11674 S L1_Replacement 0 <-- E Load 0 <-- @@ -963,40 +963,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 44624 +M Load 44747 M Ifetch 0 <-- -M Store 24057 +M Store 23942 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16625 -M Fwd_GETS 11682 +M Fwd_GETX 16721 +M Fwd_GETS 11600 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2068 +IS Inv 2079 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11587 -IS Data_all_Acks 6032 +IS DataS_fromL1 11619 +IS Data_all_Acks 6087 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10163 -IM Data_all_Acks 16743 +IM Data 10293 +IM Data_all_Acks 16616 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16310 +SM Inv 16220 SM L1_Replacement 0 <-- -SM Ack 19662 -SM Ack_all 11564 +SM Ack 19914 +SM Ack_all 11705 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -1005,7 +1005,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2068 +IS_I Data_all_Acks 2079 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -1022,59 +1022,59 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 6 --- - Event Counts - -Load 96539 +Load 97203 Ifetch 0 -Store 52066 -Inv 29723 +Store 51898 +Inv 29918 L1_Replacement 0 -Fwd_GETX 16738 -Fwd_GETS 11422 +Fwd_GETX 16733 +Fwd_GETS 11441 Fwd_GET_INSTR 0 -Data 10102 +Data 10195 Data_Exclusive 0 -DataS_fromL1 11594 -Data_all_Acks 24765 -Ack 19839 -Ack_all 11526 +DataS_fromL1 11558 +Data_all_Acks 24898 +Ack 19843 +Ack_all 11649 WB_Ack 0 - Transitions - -NP Load 2 +NP Load 0 <-- NP Ifetch 0 <-- -NP Store 0 <-- +NP Store 2 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 19723 +I Load 19932 I Ifetch 0 <-- -I Store 10567 +I Store 10583 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 32252 +S Load 32522 S Ifetch 0 <-- -S Store 17595 -S Inv 11486 +S Store 17590 +S Inv 11601 S L1_Replacement 0 <-- E Load 0 <-- @@ -1086,40 +1086,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 44562 +M Load 44749 M Ifetch 0 <-- -M Store 23904 +M Store 23723 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16738 -M Fwd_GETS 11422 +M Fwd_GETX 16733 +M Fwd_GETS 11441 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 2066 +IS Inv 2181 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11594 -IS Data_all_Acks 6065 +IS DataS_fromL1 11558 +IS Data_all_Acks 6192 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10102 -IM Data_all_Acks 16634 +IM Data 10195 +IM Data_all_Acks 16525 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16171 +SM Inv 16136 SM L1_Replacement 0 <-- -SM Ack 19839 -SM Ack_all 11526 +SM Ack 19843 +SM Ack_all 11649 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -1128,7 +1128,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2066 +IS_I Data_all_Acks 2181 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -1145,40 +1145,40 @@ E_I Ifetch 0 <-- E_I Store 0 <-- E_I L1_Replacement 0 <-- -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 7 --- - Event Counts - -Load 97318 +Load 96112 Ifetch 0 -Store 52277 -Inv 29815 +Store 51732 +Inv 29764 L1_Replacement 0 -Fwd_GETX 16715 -Fwd_GETS 11504 +Fwd_GETX 16656 +Fwd_GETS 11352 Fwd_GET_INSTR 0 -Data 10140 +Data 10123 Data_Exclusive 0 -DataS_fromL1 11582 -Data_all_Acks 24808 -Ack 19950 -Ack_all 11641 +DataS_fromL1 11506 +Data_all_Acks 24791 +Ack 19841 +Ack_all 11471 WB_Ack 0 - Transitions - @@ -1188,16 +1188,16 @@ NP Store 1 NP Inv 0 <-- NP L1_Replacement 0 <-- -I Load 19811 +I Load 19760 I Ifetch 0 <-- -I Store 10672 +I Store 10518 I Inv 0 <-- I L1_Replacement 0 <-- -S Load 33045 +S Load 32094 S Ifetch 0 <-- -S Store 17548 -S Inv 11790 +S Store 17490 +S Inv 11509 S L1_Replacement 0 <-- E Load 0 <-- @@ -1209,40 +1209,40 @@ E Fwd_GETX 0 <-- E Fwd_GETS 0 <-- E Fwd_GET_INSTR 0 <-- -M Load 44461 +M Load 44257 M Ifetch 0 <-- -M Store 24056 +M Store 23723 M Inv 0 <-- M L1_Replacement 0 <-- -M Fwd_GETX 16715 -M Fwd_GETS 11504 +M Fwd_GETX 16656 +M Fwd_GETS 11352 M Fwd_GET_INSTR 0 <-- IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- -IS Inv 1978 +IS Inv 2113 IS L1_Replacement 0 <-- IS Data_Exclusive 0 <-- -IS DataS_fromL1 11582 -IS Data_all_Acks 6252 +IS DataS_fromL1 11506 +IS Data_all_Acks 6141 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM Inv 0 <-- IM L1_Replacement 0 <-- -IM Data 10140 -IM Data_all_Acks 16578 +IM Data 10123 +IM Data_all_Acks 16537 IM Ack 0 <-- SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- -SM Inv 16047 +SM Inv 16142 SM L1_Replacement 0 <-- -SM Ack 19950 -SM Ack_all 11641 +SM Ack 19841 +SM Ack_all 11471 IS_I Load 0 <-- IS_I Ifetch 0 <-- @@ -1251,7 +1251,7 @@ IS_I Inv 0 <-- IS_I L1_Replacement 0 <-- IS_I Data_Exclusive 0 <-- IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 1978 +IS_I Data_all_Acks 2113 M_I Load 0 <-- M_I Ifetch 0 <-- @@ -1280,9 +1280,9 @@ Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory --- L2Cache 0 --- - Event Counts - L1_GET_INSTR 0 -L1_GETS 2024573 -L1_GETX 2549715 -L1_UPGRADE 314708 +L1_GETS 2024976 +L1_GETX 2555360 +L1_UPGRADE 315967 L1_PUTX 0 L1_PUTX_old 0 Fwd_L1_GETX 0 @@ -1292,26 +1292,26 @@ L2_Replacement 0 L2_Replacement_clean 0 Mem_Data 2 Mem_Ack 0 -WB_Data 93550 +WB_Data 93672 WB_Data_clean 0 Ack 0 Ack_all 0 -Unblock 93550 +Unblock 93672 Unblock_Cancel 0 -Exclusive_Unblock 228375 +Exclusive_Unblock 228648 MEM_Inv 0 - Transitions - NP L1_GET_INSTR 0 <-- -NP L1_GETS 0 <-- -NP L1_GETX 2 +NP L1_GETS 1 +NP L1_GETX 1 NP L1_PUTX 0 <-- NP L1_PUTX_old 0 <-- SS L1_GET_INSTR 0 <-- -SS L1_GETS 65810 -SS L1_GETX 81936 -SS L1_UPGRADE 11614 +SS L1_GETS 66019 +SS L1_GETX 82194 +SS L1_UPGRADE 11479 SS L1_PUTX 0 <-- SS L1_PUTX_old 0 <-- SS L2_Replacement 0 <-- @@ -1328,8 +1328,8 @@ M L2_Replacement_clean 0 <-- M MEM_Inv 0 <-- MT L1_GET_INSTR 0 <-- -MT L1_GETS 93551 -MT L1_GETX 134824 +MT L1_GETS 93672 +MT L1_GETX 134976 MT L1_PUTX 0 <-- MT L1_PUTX_old 0 <-- MT L2_Replacement 0 <-- @@ -1386,8 +1386,8 @@ S_I Ack_all 0 <-- S_I MEM_Inv 0 <-- ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- +ISS L1_GETS 1 +ISS L1_GETX 1 ISS L1_PUTX 0 <-- ISS L1_PUTX_old 0 <-- ISS L2_Replacement 0 <-- @@ -1396,47 +1396,47 @@ ISS Mem_Data 0 <-- ISS MEM_Inv 0 <-- IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- +IS L1_GETS 2 +IS L1_GETX 99 IS L1_PUTX 0 <-- IS L1_PUTX_old 0 <-- IS L2_Replacement 0 <-- IS L2_Replacement_clean 0 <-- -IS Mem_Data 0 <-- +IS Mem_Data 1 IS MEM_Inv 0 <-- IM L1_GET_INSTR 0 <-- -IM L1_GETS 244 -IM L1_GETX 183 +IM L1_GETS 144 +IM L1_GETX 108 IM L1_PUTX 0 <-- IM L1_PUTX_old 0 <-- IM L2_Replacement 0 <-- IM L2_Replacement_clean 0 <-- -IM Mem_Data 2 +IM Mem_Data 1 IM MEM_Inv 0 <-- SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 470476 -SS_MB L1_GETX 564705 -SS_MB L1_UPGRADE 262728 +SS_MB L1_GETS 469780 +SS_MB L1_GETX 567094 +SS_MB L1_UPGRADE 263602 SS_MB L1_PUTX 0 <-- SS_MB L1_PUTX_old 0 <-- SS_MB L2_Replacement 0 <-- SS_MB L2_Replacement_clean 0 <-- SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 93549 +SS_MB Exclusive_Unblock 93671 SS_MB MEM_Inv 0 <-- MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 855369 -MT_MB L1_GETX 1063853 +MT_MB L1_GETS 856977 +MT_MB L1_GETX 1064404 MT_MB L1_UPGRADE 0 <-- MT_MB L1_PUTX 0 <-- MT_MB L1_PUTX_old 0 <-- MT_MB L2_Replacement 0 <-- MT_MB L2_Replacement_clean 0 <-- MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 134826 +MT_MB Exclusive_Unblock 134977 MT_MB MEM_Inv 0 <-- M_MB L1_GET_INSTR 0 <-- @@ -1451,14 +1451,14 @@ M_MB Exclusive_Unblock 0 <-- M_MB MEM_Inv 0 <-- MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 384672 -MT_IIB L1_GETX 499786 +MT_IIB L1_GETS 384472 +MT_IIB L1_GETX 500985 MT_IIB L1_UPGRADE 0 <-- MT_IIB L1_PUTX 0 <-- MT_IIB L1_PUTX_old 0 <-- MT_IIB L2_Replacement 0 <-- MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 93550 +MT_IIB WB_Data 93672 MT_IIB WB_Data_clean 0 <-- MT_IIB Unblock 0 <-- MT_IIB MEM_Inv 0 <-- @@ -1477,14 +1477,14 @@ MT_IB Unblock_Cancel 0 <-- MT_IB MEM_Inv 0 <-- MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 154451 -MT_SB L1_GETX 204426 -MT_SB L1_UPGRADE 40366 +MT_SB L1_GETS 153908 +MT_SB L1_GETX 205498 +MT_SB L1_UPGRADE 40886 MT_SB L1_PUTX 0 <-- MT_SB L1_PUTX_old 0 <-- MT_SB L2_Replacement 0 <-- MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 93550 +MT_SB Unblock 93672 MT_SB MEM_Inv 0 <-- Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr index 780ce373e..a000ce3a0 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu7: completed 10000 read accesses @373359 -system.cpu1: completed 10000 read accesses @375374 -system.cpu0: completed 10000 read accesses @376725 -system.cpu2: completed 10000 read accesses @380778 -system.cpu5: completed 10000 read accesses @382682 -system.cpu3: completed 10000 read accesses @383505 -system.cpu4: completed 10000 read accesses @386561 -system.cpu6: completed 10000 read accesses @389125 -system.cpu1: completed 20000 read accesses @745885 -system.cpu0: completed 20000 read accesses @748353 -system.cpu2: completed 20000 read accesses @753861 -system.cpu7: completed 20000 read accesses @758042 -system.cpu5: completed 20000 read accesses @759129 -system.cpu3: completed 20000 read accesses @764814 -system.cpu4: completed 20000 read accesses @768939 -system.cpu6: completed 20000 read accesses @774936 -system.cpu1: completed 30000 read accesses @1121924 -system.cpu2: completed 30000 read accesses @1124427 -system.cpu0: completed 30000 read accesses @1125253 -system.cpu7: completed 30000 read accesses @1139134 -system.cpu4: completed 30000 read accesses @1139334 -system.cpu3: completed 30000 read accesses @1144574 -system.cpu5: completed 30000 read accesses @1145748 -system.cpu6: completed 30000 read accesses @1147208 -system.cpu0: completed 40000 read accesses @1492239 -system.cpu1: completed 40000 read accesses @1495604 -system.cpu2: completed 40000 read accesses @1499940 -system.cpu4: completed 40000 read accesses @1518641 -system.cpu7: completed 40000 read accesses @1518771 -system.cpu5: completed 40000 read accesses @1528667 -system.cpu6: completed 40000 read accesses @1530209 -system.cpu3: completed 40000 read accesses @1537371 -system.cpu0: completed 50000 read accesses @1865558 -system.cpu1: completed 50000 read accesses @1868280 -system.cpu2: completed 50000 read accesses @1884528 -system.cpu7: completed 50000 read accesses @1899621 -system.cpu4: completed 50000 read accesses @1903698 -system.cpu5: completed 50000 read accesses @1909143 -system.cpu3: completed 50000 read accesses @1910503 -system.cpu6: completed 50000 read accesses @1915590 -system.cpu0: completed 60000 read accesses @2235441 -system.cpu1: completed 60000 read accesses @2240292 -system.cpu2: completed 60000 read accesses @2270206 -system.cpu4: completed 60000 read accesses @2278819 -system.cpu7: completed 60000 read accesses @2284397 -system.cpu5: completed 60000 read accesses @2288761 -system.cpu3: completed 60000 read accesses @2289377 -system.cpu6: completed 60000 read accesses @2312599 -system.cpu0: completed 70000 read accesses @2605926 -system.cpu1: completed 70000 read accesses @2606409 -system.cpu4: completed 70000 read accesses @2648937 -system.cpu2: completed 70000 read accesses @2655948 -system.cpu5: completed 70000 read accesses @2662046 -system.cpu3: completed 70000 read accesses @2664803 -system.cpu7: completed 70000 read accesses @2675843 -system.cpu6: completed 70000 read accesses @2704307 -system.cpu1: completed 80000 read accesses @2972591 -system.cpu0: completed 80000 read accesses @2986258 -system.cpu3: completed 80000 read accesses @3027695 -system.cpu4: completed 80000 read accesses @3034526 -system.cpu2: completed 80000 read accesses @3036101 -system.cpu5: completed 80000 read accesses @3049670 -system.cpu7: completed 80000 read accesses @3053840 -system.cpu6: completed 80000 read accesses @3088364 -system.cpu1: completed 90000 read accesses @3348204 -system.cpu0: completed 90000 read accesses @3355393 -system.cpu3: completed 90000 read accesses @3393344 -system.cpu2: completed 90000 read accesses @3410223 -system.cpu4: completed 90000 read accesses @3417605 -system.cpu5: completed 90000 read accesses @3432894 -system.cpu7: completed 90000 read accesses @3437480 -system.cpu6: completed 90000 read accesses @3470461 -system.cpu1: completed 100000 read accesses @3719757 +system.cpu5: completed 10000 read accesses @370057 +system.cpu1: completed 10000 read accesses @372602 +system.cpu0: completed 10000 read accesses @380072 +system.cpu3: completed 10000 read accesses @380676 +system.cpu4: completed 10000 read accesses @383371 +system.cpu2: completed 10000 read accesses @385679 +system.cpu6: completed 10000 read accesses @386340 +system.cpu7: completed 10000 read accesses @389231 +system.cpu5: completed 20000 read accesses @746317 +system.cpu0: completed 20000 read accesses @748763 +system.cpu3: completed 20000 read accesses @752788 +system.cpu1: completed 20000 read accesses @753263 +system.cpu4: completed 20000 read accesses @763818 +system.cpu6: completed 20000 read accesses @765866 +system.cpu2: completed 20000 read accesses @771677 +system.cpu7: completed 20000 read accesses @772771 +system.cpu0: completed 30000 read accesses @1112242 +system.cpu1: completed 30000 read accesses @1129327 +system.cpu3: completed 30000 read accesses @1129794 +system.cpu5: completed 30000 read accesses @1131833 +system.cpu2: completed 30000 read accesses @1142425 +system.cpu4: completed 30000 read accesses @1144628 +system.cpu6: completed 30000 read accesses @1153431 +system.cpu7: completed 30000 read accesses @1154016 +system.cpu0: completed 40000 read accesses @1484294 +system.cpu1: completed 40000 read accesses @1505996 +system.cpu3: completed 40000 read accesses @1507887 +system.cpu2: completed 40000 read accesses @1512800 +system.cpu4: completed 40000 read accesses @1520410 +system.cpu5: completed 40000 read accesses @1522723 +system.cpu6: completed 40000 read accesses @1538655 +system.cpu7: completed 40000 read accesses @1539216 +system.cpu0: completed 50000 read accesses @1860160 +system.cpu3: completed 50000 read accesses @1882708 +system.cpu1: completed 50000 read accesses @1883329 +system.cpu2: completed 50000 read accesses @1891575 +system.cpu4: completed 50000 read accesses @1896200 +system.cpu5: completed 50000 read accesses @1912575 +system.cpu6: completed 50000 read accesses @1917985 +system.cpu7: completed 50000 read accesses @1929708 +system.cpu0: completed 60000 read accesses @2233080 +system.cpu1: completed 60000 read accesses @2253689 +system.cpu3: completed 60000 read accesses @2259715 +system.cpu2: completed 60000 read accesses @2264515 +system.cpu4: completed 60000 read accesses @2278281 +system.cpu5: completed 60000 read accesses @2291280 +system.cpu6: completed 60000 read accesses @2305718 +system.cpu7: completed 60000 read accesses @2318114 +system.cpu0: completed 70000 read accesses @2615296 +system.cpu1: completed 70000 read accesses @2621479 +system.cpu2: completed 70000 read accesses @2635267 +system.cpu3: completed 70000 read accesses @2642310 +system.cpu4: completed 70000 read accesses @2659144 +system.cpu5: completed 70000 read accesses @2668163 +system.cpu6: completed 70000 read accesses @2691243 +system.cpu7: completed 70000 read accesses @2706192 +system.cpu0: completed 80000 read accesses @2986810 +system.cpu1: completed 80000 read accesses @2994418 +system.cpu2: completed 80000 read accesses @3009400 +system.cpu3: completed 80000 read accesses @3028789 +system.cpu4: completed 80000 read accesses @3033010 +system.cpu5: completed 80000 read accesses @3042800 +system.cpu6: completed 80000 read accesses @3071603 +system.cpu7: completed 80000 read accesses @3108423 +system.cpu0: completed 90000 read accesses @3351259 +system.cpu1: completed 90000 read accesses @3361381 +system.cpu2: completed 90000 read accesses @3381198 +system.cpu4: completed 90000 read accesses @3406636 +system.cpu3: completed 90000 read accesses @3411857 +system.cpu5: completed 90000 read accesses @3424074 +system.cpu6: completed 90000 read accesses @3457139 +system.cpu7: completed 90000 read accesses @3490206 +system.cpu0: completed 100000 read accesses @3725190 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 5587c1dbc..d6fbf79bb 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:36:48 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:36:46 -M5 executing on cabr0210 -command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory +M5 compiled Jul 1 2010 14:38:07 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:39:45 +M5 executing on phenom +command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3719757 because maximum number of loads reached +Exiting @ tick 3725190 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index d4dd5f473..a684f8cc5 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340040 # Number of bytes of host memory used -host_seconds 42.78 # Real time elapsed on the host -host_tick_rate 86943 # Simulator tick rate (ticks/s) +host_mem_usage 332596 # Number of bytes of host memory used +host_seconds 35.19 # Real time elapsed on the host +host_tick_rate 105869 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003720 # Number of seconds simulated -sim_ticks 3719757 # Number of ticks simulated +sim_seconds 0.003725 # Number of seconds simulated +sim_ticks 3725190 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99860 # number of read accesses completed -system.cpu0.num_writes 53770 # number of write accesses completed +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 53802 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53093 # number of write accesses completed +system.cpu1.num_reads 99730 # number of read accesses completed +system.cpu1.num_writes 53651 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98032 # number of read accesses completed -system.cpu2.num_writes 52757 # number of write accesses completed +system.cpu2.num_reads 99194 # number of read accesses completed +system.cpu2.num_writes 53071 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98573 # number of read accesses completed -system.cpu3.num_writes 52922 # number of write accesses completed +system.cpu3.num_reads 98275 # number of read accesses completed +system.cpu3.num_writes 53108 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 97812 # number of read accesses completed -system.cpu4.num_writes 53065 # number of write accesses completed +system.cpu4.num_reads 98291 # number of read accesses completed +system.cpu4.num_writes 52851 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97538 # number of read accesses completed -system.cpu5.num_writes 52364 # number of write accesses completed +system.cpu5.num_reads 97729 # number of read accesses completed +system.cpu5.num_writes 52263 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 96539 # number of read accesses completed -system.cpu6.num_writes 52064 # number of write accesses completed +system.cpu6.num_reads 97202 # number of read accesses completed +system.cpu6.num_writes 51897 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97318 # number of read accesses completed -system.cpu7.num_writes 52275 # number of write accesses completed +system.cpu7.num_reads 96111 # number of read accesses completed +system.cpu7.num_writes 51731 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index 83d609efe..72fa2cdc0 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -22,7 +22,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest @@ -37,7 +37,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest @@ -52,7 +52,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest @@ -67,7 +67,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest @@ -82,7 +82,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest @@ -97,7 +97,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest @@ -112,7 +112,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest @@ -127,7 +127,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports7.port[0] [system.funcmem] type=PhysicalMemory @@ -147,11 +147,11 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer block_size_bytes=64 clock=1 debug=system.ruby.debug @@ -164,6 +164,102 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + [system.ruby.debug] type=RubyDebug filter_string=none @@ -202,39 +298,26 @@ weight=1 [system.ruby.network.topology.ext_links0.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -252,39 +335,26 @@ weight=1 [system.ruby.network.topology.ext_links1.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -302,39 +372,26 @@ weight=1 [system.ruby.network.topology.ext_links2.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -352,39 +409,26 @@ weight=1 [system.ruby.network.topology.ext_links3.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -402,39 +446,26 @@ weight=1 [system.ruby.network.topology.ext_links4.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -452,39 +483,26 @@ weight=1 [system.ruby.network.topology.ext_links5.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -502,39 +520,26 @@ weight=1 [system.ruby.network.topology.ext_links6.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -552,39 +557,26 @@ weight=1 [system.ruby.network.topology.ext_links7.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index 4ef91b4d1..afc84d0aa 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:38:52 +Real time: Jul/01/2010 14:40:10 Profiler Stats -------------- -Elapsed_time_in_seconds: 30 -Elapsed_time_in_minutes: 0.5 -Elapsed_time_in_hours: 0.00833333 -Elapsed_time_in_days: 0.000347222 +Elapsed_time_in_seconds: 25 +Elapsed_time_in_minutes: 0.416667 +Elapsed_time_in_hours: 0.00694444 +Elapsed_time_in_days: 0.000289352 -Virtual_time_in_seconds: 30.63 -Virtual_time_in_minutes: 0.5105 -Virtual_time_in_hours: 0.00850833 -Virtual_time_in_days: 0.000354514 +Virtual_time_in_seconds: 24.36 +Virtual_time_in_minutes: 0.406 +Virtual_time_in_hours: 0.00676667 +Virtual_time_in_days: 0.000281944 -Ruby_current_time: 3383480 +Ruby_current_time: 3358188 Ruby_start_time: 0 -Ruby_cycles: 3383480 +Ruby_cycles: 3358188 -mbytes_resident: 31.1758 -mbytes_total: 332.199 -resident_ratio: 0.0938584 +mbytes_resident: 32.3125 +mbytes_total: 325.066 +resident_ratio: 0.0994148 -ruby_cycles_executed: [ 3383481 3383481 3383481 3383481 3383481 3383481 3383481 3383481 ] +ruby_cycles_executed: [ 3358189 3358189 3358189 3358189 3358189 3358189 3358189 3358189 ] Busy Controller Counts: L2Cache-0:0 @@ -67,13 +67,13 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1224321 average: 1.94443 | standard deviation: 0.229099 | 0 68041 1156280 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1215398 average: 1.9442 | standard deviation: 0.229541 | 0 67822 1147576 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 3867 count: 1224307 average: 42.2125 | standard deviation: 176.83 | 1120193 100 18422 250 3697 208 20055 99 4698 333 9493 182 6212 231 4498 196 5380 146 3026 431 3578 201 1712 1300 2300 299 1246 1179 1311 691 911 859 562 1056 709 654 462 707 409 573 330 526 208 545 261 415 162 365 175 313 146 267 103 218 103 205 80 151 93 135 60 94 55 71 59 59 41 45 41 43 25 43 16 31 21 32 21 10 15 14 10 15 8 8 10 11 3 5 9 6 6 4 4 6 2 6 2 1 4 2 3 3 0 4 0 0 3 1 0 0 0 1 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 3867 count: 795461 average: 41.7693 | standard deviation: 175.853 | 728451 2 12003 191 2273 112 13052 34 3039 166 6174 100 3966 173 2859 112 3400 77 2124 112 2321 116 1129 856 1452 179 824 756 1029 226 579 535 370 687 463 438 297 467 315 303 212 351 132 368 156 264 104 243 137 191 94 174 61 126 56 132 56 96 69 83 39 57 32 46 30 39 31 29 27 22 22 23 12 25 9 21 12 7 10 7 7 11 7 7 5 7 3 3 9 6 1 1 1 4 1 5 0 0 2 1 2 2 0 3 0 0 1 1 0 0 0 1 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 32 max: 3728 count: 428846 average: 43.0346 | standard deviation: 178.625 | 391742 98 6419 59 1424 96 7003 65 1659 167 3319 82 2246 58 1639 84 1980 69 902 319 1257 85 583 444 848 120 422 423 282 465 332 324 192 369 246 216 165 240 94 270 118 175 76 177 105 151 58 122 38 122 52 93 42 92 47 73 24 55 24 52 21 37 23 25 29 20 10 16 14 21 3 20 4 6 12 11 9 3 5 7 3 4 1 1 5 4 0 2 0 0 5 3 3 2 1 1 2 1 2 1 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 3818 count: 1215384 average: 42.2024 | standard deviation: 176.766 | 1112077 89 18203 264 3632 204 20059 101 4609 316 9477 164 6271 231 4384 203 5321 133 2876 482 3614 199 1795 1183 2274 311 1255 1088 1275 707 917 894 528 1015 642 655 443 760 442 606 299 540 235 520 242 363 176 392 189 294 130 248 95 236 136 162 90 172 87 120 50 105 55 101 50 85 34 40 36 47 31 38 30 27 22 22 15 19 16 16 3 8 11 13 12 10 9 5 3 4 7 4 10 2 4 1 3 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 32 max: 3747 count: 790225 average: 41.6816 | standard deviation: 175.575 | 723783 1 11782 190 2290 112 13127 39 3042 155 6044 74 4067 176 2753 101 3392 79 2018 104 2293 131 1147 763 1424 189 833 676 1076 268 593 583 350 633 400 406 275 496 347 325 213 346 154 347 144 245 122 253 140 180 89 157 59 165 82 106 64 99 60 68 27 65 34 66 28 49 22 25 27 26 20 22 20 18 12 16 9 12 13 9 1 5 9 8 6 9 6 1 1 3 4 3 6 2 2 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 32 max: 3818 count: 425159 average: 43.1703 | standard deviation: 178.955 | 388294 88 6421 74 1342 92 6932 62 1567 161 3433 90 2204 55 1631 102 1929 54 858 378 1321 68 648 420 850 122 422 412 199 439 324 311 178 382 242 249 168 264 95 281 86 194 81 173 98 118 54 139 49 114 41 91 36 71 54 56 26 73 27 52 23 40 21 35 22 36 12 15 9 21 11 16 10 9 10 6 6 7 3 7 2 3 2 5 6 1 3 4 2 1 3 1 4 0 2 0 2 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,160 +103,160 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 30 +user_time: 24 system_time: 0 -page_reclaims: 9017 +page_reclaims: 8496 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 16 +block_outputs: 72 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.130563 - links_utilized_percent_switch_0_link_0: 0.0497661 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.211361 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.129534 + links_utilized_percent_switch_0_link_0: 0.0494002 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.209668 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12977 934344 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 4794 38352 [ 0 0 4794 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 12995 103960 [ 12995 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 12993 103944 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12797 921384 [ 0 0 12797 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 4642 37136 [ 0 0 4642 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Forwarded_Control: 12801 102408 [ 12801 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 12811 102488 [ 12811 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 12809 102472 [ 0 0 12809 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.131025 - links_utilized_percent_switch_1_link_0: 0.0500265 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.212023 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13047 939384 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 4825 38600 [ 0 0 4825 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 13041 104328 [ 13041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Invalidate_Control: 113 904 [ 113 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 13065 104520 [ 13065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 113 904 [ 0 0 113 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 13063 104504 [ 0 0 13063 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.132053 + links_utilized_percent_switch_1_link_0: 0.0504037 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.213702 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13049 939528 [ 0 0 13049 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 4824 38592 [ 0 0 4824 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 13045 104360 [ 13045 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 13062 104496 [ 13062 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13034 938448 [ 0 0 13034 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 13060 104480 [ 0 0 13060 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.130359 - links_utilized_percent_switch_2_link_0: 0.0496922 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.211027 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 12963 933336 [ 0 0 12963 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 4756 38048 [ 0 0 4756 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 12979 103832 [ 12979 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12972 933984 [ 0 0 12972 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 97 776 [ 0 0 97 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 12977 103816 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.132003 + links_utilized_percent_switch_2_link_0: 0.0503009 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.213705 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 4741 37928 [ 0 0 4741 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 13054 104432 [ 13054 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 13042 104336 [ 13042 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 13039 938808 [ 0 0 13039 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 13041 104328 [ 0 0 13041 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.13073 - links_utilized_percent_switch_3_link_0: 0.0497838 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.211677 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12985 934920 [ 0 0 12985 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 4762 38096 [ 0 0 4762 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 13023 104184 [ 13023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 12993 103944 [ 12993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13017 937224 [ 0 0 13017 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 12991 103928 [ 0 0 12991 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.131776 + links_utilized_percent_switch_3_link_0: 0.0501826 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.21337 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 4748 37984 [ 0 0 4748 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 13039 104312 [ 13039 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Invalidate_Control: 94 752 [ 94 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 13013 104104 [ 13013 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13021 937512 [ 0 0 13021 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 94 752 [ 0 0 94 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 13011 104088 [ 0 0 13011 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.131205 - links_utilized_percent_switch_4_link_0: 0.0500587 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.212351 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.130943 + links_utilized_percent_switch_4_link_0: 0.0499518 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.211934 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 13069 940968 [ 0 0 13069 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 4715 37720 [ 0 0 4715 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 13059 104472 [ 13059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12944 931968 [ 0 0 12944 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 4660 37280 [ 0 0 4660 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 12939 103512 [ 12939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_4_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 13082 104656 [ 13082 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 12958 103664 [ 12958 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12925 930600 [ 0 0 12925 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_4_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 13080 104640 [ 0 0 13080 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 12957 103656 [ 0 0 12957 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.13071 - links_utilized_percent_switch_5_link_0: 0.0498414 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.211579 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 13020 937440 [ 0 0 13020 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 4616 36928 [ 0 0 4616 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 13012 104096 [ 13012 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 13033 104264 [ 13033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 13001 936072 [ 0 0 13001 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 13031 104248 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.128854 + links_utilized_percent_switch_5_link_0: 0.0491307 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.208577 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12722 915984 [ 0 0 12722 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 4664 37312 [ 0 0 4664 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 12737 101896 [ 12737 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Invalidate_Control: 93 744 [ 93 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 12736 101888 [ 12736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12725 916200 [ 0 0 12725 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 93 744 [ 0 0 93 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 12734 101872 [ 0 0 12734 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.131064 - links_utilized_percent_switch_6_link_0: 0.0499375 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.212191 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 13031 938232 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4732 37856 [ 0 0 4732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 13061 104488 [ 13061 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 13048 104384 [ 13048 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 13044 939168 [ 0 0 13044 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 13047 104376 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.130398 + links_utilized_percent_switch_6_link_0: 0.0498286 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.210966 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12912 929664 [ 0 0 12912 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 4683 37464 [ 0 0 4683 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 12871 102968 [ 12871 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Invalidate_Control: 105 840 [ 105 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 12925 103400 [ 12925 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12860 925920 [ 0 0 12860 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 105 840 [ 0 0 105 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 12923 103384 [ 0 0 12923 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.130272 - links_utilized_percent_switch_7_link_0: 0.0497081 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.210836 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 4785 38280 [ 0 0 4785 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 12972 103776 [ 12972 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Invalidate_Control: 116 928 [ 116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 12981 103848 [ 12981 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12955 932760 [ 0 0 12955 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 116 928 [ 0 0 116 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 12980 103840 [ 0 0 12980 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.129861 + links_utilized_percent_switch_7_link_0: 0.0494162 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.210305 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 4708 37664 [ 0 0 4708 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 12853 102824 [ 12853 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Invalidate_Control: 88 704 [ 88 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 12806 102448 [ 12806 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12839 924408 [ 0 0 12839 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 88 704 [ 0 0 88 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 12804 102432 [ 0 0 12804 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.143257 - links_utilized_percent_switch_8_link_0: 0.0769755 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.209539 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.143198 + links_utilized_percent_switch_8_link_0: 0.0769425 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.209454 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 104176 833408 [ 104176 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 103353 826824 [ 103353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 104162 833296 [ 0 0 104162 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 103339 826712 [ 0 0 103339 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 37150 297200 [ 0 0 37150 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 104162 833296 [ 104162 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Invalidate_Control: 460 3680 [ 460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 36896 295168 [ 0 0 36896 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Forwarded_Control: 103339 826712 [ 103339 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Invalidate_Control: 420 3360 [ 420 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.40388e-05 - links_utilized_percent_switch_9_link_0: 1.47777e-06 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.65998e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.41445e-05 + links_utilized_percent_switch_9_link_0: 1.4889e-06 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.68002e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 @@ -264,165 +264,165 @@ links_utilized_percent_switch_9: 1.40388e-05 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.190316 - links_utilized_percent_switch_10_link_0: 0.199064 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.200106 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.198769 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.199135 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.200235 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.199366 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.19975 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.198832 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.307902 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 5.91107e-06 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.190223 + links_utilized_percent_switch_10_link_0: 0.197601 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.201615 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.201204 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.20073 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.199807 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.196523 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.199314 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.197665 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.30777 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 5.95559e-06 bw: 160000 base_latency: 1 outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12977 934344 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 4794 38352 [ 0 0 4794 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Forwarded_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13047 939384 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 4825 38600 [ 0 0 4825 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Forwarded_Control: 13041 104328 [ 13041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Invalidate_Control: 113 904 [ 113 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 12963 933336 [ 0 0 12963 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 4756 38048 [ 0 0 4756 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12985 934920 [ 0 0 12985 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 4762 38096 [ 0 0 4762 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Forwarded_Control: 13023 104184 [ 13023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 13069 940968 [ 0 0 13069 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 4715 37720 [ 0 0 4715 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Forwarded_Control: 13059 104472 [ 13059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12797 921384 [ 0 0 12797 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 4642 37136 [ 0 0 4642 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Forwarded_Control: 12801 102408 [ 12801 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13049 939528 [ 0 0 13049 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 4824 38592 [ 0 0 4824 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Forwarded_Control: 13045 104360 [ 13045 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 4741 37928 [ 0 0 4741 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Forwarded_Control: 13054 104432 [ 13054 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 4748 37984 [ 0 0 4748 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Forwarded_Control: 13039 104312 [ 13039 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Invalidate_Control: 94 752 [ 94 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12944 931968 [ 0 0 12944 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 4660 37280 [ 0 0 4660 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Forwarded_Control: 12939 103512 [ 12939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_4_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 13020 937440 [ 0 0 13020 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 4616 36928 [ 0 0 4616 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Forwarded_Control: 13012 104096 [ 13012 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 13031 938232 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4732 37856 [ 0 0 4732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Forwarded_Control: 13061 104488 [ 13061 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 4785 38280 [ 0 0 4785 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Forwarded_Control: 12972 103776 [ 12972 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Invalidate_Control: 116 928 [ 116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 104176 833408 [ 104176 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12722 915984 [ 0 0 12722 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 4664 37312 [ 0 0 4664 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Forwarded_Control: 12737 101896 [ 12737 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Invalidate_Control: 93 744 [ 93 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12912 929664 [ 0 0 12912 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 4683 37464 [ 0 0 4683 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Forwarded_Control: 12871 102968 [ 12871 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Invalidate_Control: 105 840 [ 105 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12790 920880 [ 0 0 12790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 4708 37664 [ 0 0 4708 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Forwarded_Control: 12853 102824 [ 12853 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Invalidate_Control: 88 704 [ 88 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 103353 826824 [ 103353 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Unblock_Control: 104162 833296 [ 0 0 104162 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Unblock_Control: 103339 826712 [ 0 0 103339 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 0 --- - Event Counts - -Load 99023 +Load 98038 Ifetch 0 -Store 53582 +Store 52677 L1_Replacement 0 -Own_GETX 15 -Fwd_GETX 21995 -Fwd_GETS 41350 +Own_GETX 11 +Fwd_GETX 22106 +Fwd_GETS 40419 Fwd_DMA 0 -Inv 102 -Ack 4794 -Data 115 -Exclusive_Data 12863 +Inv 91 +Ack 4642 +Data 101 +Exclusive_Data 12697 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4711 -Use_Timeout 12878 +All_acks 4542 +Use_Timeout 12708 - Transitions - -I Load 8283 +I Load 8269 I Ifetch 0 <-- -I Store 4542 +I Store 4406 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 166 +S Load 152 S Ifetch 0 <-- -S Store 100 +S Store 87 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 15 +S Inv 14 -O Load 114 +O Load 89 O Ifetch 0 <-- -O Store 70 +O Store 49 O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 7 +O Fwd_GETX 3 +O Fwd_GETS 3 O Fwd_DMA 0 <-- -M Load 138 +M Load 108 M Ifetch 0 <-- -M Store 67 +M Store 59 M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 70 +M Fwd_GETX 24 +M Fwd_GETS 52 M Fwd_DMA 0 <-- -M_W Load 14727 +M_W Load 14673 M_W Ifetch 0 <-- -M_W Store 7998 +M_W Store 8031 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1309 -M_W Fwd_GETS 2512 +M_W Fwd_GETX 1325 +M_W Fwd_GETS 2498 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 169 +M_W Use_Timeout 135 -MM Load 11464 +MM Load 11534 MM Ifetch 0 <-- -MM Store 6136 +MM Store 6099 MM L1_Replacement 0 <-- -MM Fwd_GETX 4431 -MM Fwd_GETS 8345 +MM Fwd_GETX 4465 +MM Fwd_GETS 8167 MM Fwd_DMA 0 <-- -MM_W Load 64131 +MM_W Load 63213 MM_W Ifetch 0 <-- -MM_W Store 34669 +MM_W Store 33946 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16168 -MM_W Fwd_GETS 30363 +MM_W Fwd_GETX 16251 +MM_W Fwd_GETS 29661 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12709 +MM_W Use_Timeout 12573 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4704 +IM Ack 4548 IM Data 0 <-- -IM Exclusive_Data 4683 +IM Exclusive_Data 4521 SM Load 0 <-- SM Ifetch 0 <-- @@ -430,29 +430,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 87 -SM Ack 24 +SM Inv 77 +SM Ack 22 SM Data 0 <-- -SM Exclusive_Data 13 +SM Exclusive_Data 10 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 15 -OM Fwd_GETX 55 -OM Fwd_GETS 53 +OM Own_GETX 11 +OM Fwd_GETX 38 +OM Fwd_GETS 38 OM Fwd_DMA 0 <-- -OM Ack 66 -OM All_acks 4711 +OM Ack 72 +OM All_acks 4542 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 115 -IS Exclusive_Data 8167 +IS Data 101 +IS Exclusive_Data 8166 SI Load 0 <-- SI Ifetch 0 <-- @@ -496,113 +496,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 1 --- - Event Counts - -Load 99832 +Load 99904 Ifetch 0 -Store 53534 +Store 53672 L1_Replacement 0 -Own_GETX 15 -Fwd_GETX 22841 -Fwd_GETS 40784 +Own_GETX 11 +Fwd_GETX 22767 +Fwd_GETS 40844 Fwd_DMA 0 -Inv 113 -Ack 4825 -Data 126 -Exclusive_Data 12922 +Inv 102 +Ack 4824 +Data 113 +Exclusive_Data 12936 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4716 -Use_Timeout 12937 +All_acks 4720 +Use_Timeout 12947 - Transitions - -I Load 8348 +I Load 8341 I Ifetch 0 <-- -I Store 4563 +I Store 4582 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 229 +S Load 188 S Ifetch 0 <-- -S Store 102 +S Store 97 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 24 +S Inv 16 -O Load 78 +O Load 103 O Ifetch 0 <-- -O Store 52 +O Store 42 O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 2 +O Fwd_GETX 3 +O Fwd_GETS 7 O Fwd_DMA 0 <-- -M Load 127 +M Load 119 M Ifetch 0 <-- -M Store 53 +M Store 47 M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 54 +M Fwd_GETX 34 +M Fwd_GETS 45 M Fwd_DMA 0 <-- -M_W Load 14558 +M_W Load 15164 M_W Ifetch 0 <-- -M_W Store 8082 +M_W Store 8101 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1302 -M_W Fwd_GETS 2460 +M_W Fwd_GETX 1415 +M_W Fwd_GETS 2544 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 139 +M_W Use_Timeout 126 -MM Load 11606 +MM Load 11562 MM Ifetch 0 <-- -MM Store 6135 +MM Store 6213 MM L1_Replacement 0 <-- -MM Fwd_GETX 4608 -MM Fwd_GETS 8243 +MM Fwd_GETX 4597 +MM Fwd_GETS 8271 MM Fwd_DMA 0 <-- -MM_W Load 64886 +MM_W Load 64427 MM_W Ifetch 0 <-- -MM_W Store 34547 +MM_W Store 34590 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16860 -MM_W Fwd_GETS 29977 +MM_W Fwd_GETX 16687 +MM_W Fwd_GETS 29931 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12798 +MM_W Use_Timeout 12821 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4712 +IM Ack 4727 IM Data 0 <-- -IM Exclusive_Data 4688 +IM Exclusive_Data 4698 SM Load 0 <-- SM Ifetch 0 <-- @@ -610,29 +610,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 89 -SM Ack 30 +SM Inv 86 +SM Ack 23 SM Data 0 <-- -SM Exclusive_Data 13 +SM Exclusive_Data 11 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 15 -OM Fwd_GETX 37 -OM Fwd_GETS 48 +OM Own_GETX 11 +OM Fwd_GETX 31 +OM Fwd_GETS 46 OM Fwd_DMA 0 <-- -OM Ack 83 -OM All_acks 4716 +OM Ack 74 +OM All_acks 4720 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 126 -IS Exclusive_Data 8221 +IS Data 113 +IS Exclusive_Data 8227 SI Load 0 <-- SI Ifetch 0 <-- @@ -676,113 +676,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 2 --- - Event Counts - -Load 98648 +Load 100001 Ifetch 0 -Store 53693 +Store 53360 L1_Replacement 0 Own_GETX 14 -Fwd_GETX 22578 -Fwd_GETS 40716 +Fwd_GETX 22353 +Fwd_GETS 41223 Fwd_DMA 0 -Inv 97 -Ack 4756 -Data 101 -Exclusive_Data 12862 +Inv 98 +Ack 4741 +Data 107 +Exclusive_Data 12920 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4665 -Use_Timeout 12876 +All_acks 4660 +Use_Timeout 12933 - Transitions - -I Load 8314 +I Load 8382 I Ifetch 0 <-- -I Store 4523 +I Store 4515 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 156 +S Load 157 S Ifetch 0 <-- -S Store 88 +S Store 92 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 13 +S Inv 15 -O Load 95 +O Load 104 O Ifetch 0 <-- -O Store 54 +O Store 53 O L1_Replacement 0 <-- -O Fwd_GETX 1 -O Fwd_GETS 5 +O Fwd_GETX 3 +O Fwd_GETS 6 O Fwd_DMA 0 <-- -M Load 117 +M Load 134 M Ifetch 0 <-- -M Store 75 +M Store 74 M L1_Replacement 0 <-- -M Fwd_GETX 25 -M Fwd_GETS 55 +M Fwd_GETX 30 +M Fwd_GETS 56 M Fwd_DMA 0 <-- -M_W Load 14809 +M_W Load 15047 M_W Ifetch 0 <-- -M_W Store 8056 +M_W Store 8113 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1398 -M_W Fwd_GETS 2484 +M_W Fwd_GETX 1357 +M_W Fwd_GETS 2574 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 155 +M_W Use_Timeout 160 -MM Load 11304 +MM Load 11573 MM Ifetch 0 <-- -MM Store 6290 +MM Store 6155 MM L1_Replacement 0 <-- -MM Fwd_GETX 4562 -MM Fwd_GETS 8234 +MM Fwd_GETX 4522 +MM Fwd_GETS 8325 MM Fwd_DMA 0 <-- -MM_W Load 63853 +MM_W Load 64604 MM_W Ifetch 0 <-- -MM_W Store 34607 +MM_W Store 34358 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16552 -MM_W Fwd_GETS 29888 +MM_W Fwd_GETX 16402 +MM_W Fwd_GETS 30204 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12721 +MM_W Use_Timeout 12773 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4666 +IM Ack 4654 IM Data 0 <-- -IM Exclusive_Data 4647 +IM Exclusive_Data 4637 SM Load 0 <-- SM Ifetch 0 <-- @@ -790,29 +790,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 7 +SM Inv 83 +SM Ack 18 SM Data 0 <-- -SM Exclusive_Data 4 +SM Exclusive_Data 9 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- OM Own_GETX 14 -OM Fwd_GETX 40 -OM Fwd_GETS 50 +OM Fwd_GETX 39 +OM Fwd_GETS 58 OM Fwd_DMA 0 <-- -OM Ack 83 -OM All_acks 4665 +OM Ack 69 +OM All_acks 4660 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 101 -IS Exclusive_Data 8211 +IS Data 107 +IS Exclusive_Data 8274 SI Load 0 <-- SI Ifetch 0 <-- @@ -856,113 +856,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 3 --- - Event Counts - -Load 99441 +Load 99547 Ifetch 0 -Store 53405 +Store 53578 L1_Replacement 0 -Own_GETX 6 -Fwd_GETX 22814 -Fwd_GETS 40551 +Own_GETX 18 +Fwd_GETX 22394 +Fwd_GETS 41045 Fwd_DMA 0 -Inv 104 -Ack 4762 -Data 117 -Exclusive_Data 12868 +Inv 94 +Ack 4748 +Data 109 +Exclusive_Data 12884 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4673 -Use_Timeout 12874 +All_acks 4636 +Use_Timeout 12902 - Transitions - -I Load 8319 +I Load 8377 I Ifetch 0 <-- -I Store 4518 +I Store 4474 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 207 +S Load 160 S Ifetch 0 <-- -S Store 92 +S Store 96 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 25 +S Inv 13 -O Load 119 +O Load 137 O Ifetch 0 <-- -O Store 64 +O Store 66 O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 6 +O Fwd_GETX 3 +O Fwd_GETS 5 O Fwd_DMA 0 <-- -M Load 168 +M Load 150 M Ifetch 0 <-- -M Store 54 +M Store 62 M L1_Replacement 0 <-- -M Fwd_GETX 44 -M Fwd_GETS 66 +M Fwd_GETX 36 +M Fwd_GETS 69 M Fwd_DMA 0 <-- -M_W Load 15070 +M_W Load 15193 M_W Ifetch 0 <-- -M_W Store 8037 +M_W Store 8099 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1396 -M_W Fwd_GETS 2516 +M_W Fwd_GETX 1351 +M_W Fwd_GETS 2628 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 164 +M_W Use_Timeout 167 -MM Load 11490 +MM Load 11388 MM Ifetch 0 <-- -MM Store 6222 +MM Store 6298 MM L1_Replacement 0 <-- -MM Fwd_GETX 4591 -MM Fwd_GETS 8173 +MM Fwd_GETX 4511 +MM Fwd_GETS 8286 MM Fwd_DMA 0 <-- -MM_W Load 64068 +MM_W Load 64142 MM_W Ifetch 0 <-- -MM_W Store 34418 +MM_W Store 34483 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16723 -MM_W Fwd_GETS 29713 +MM_W Fwd_GETX 16445 +MM_W Fwd_GETS 29994 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12710 +MM_W Use_Timeout 12735 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4672 +IM Ack 4626 IM Data 0 <-- -IM Exclusive_Data 4654 +IM Exclusive_Data 4603 SM Load 0 <-- SM Ifetch 0 <-- @@ -970,29 +970,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 79 -SM Ack 33 +SM Inv 81 +SM Ack 31 SM Data 0 <-- -SM Exclusive_Data 13 +SM Exclusive_Data 15 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 6 -OM Fwd_GETX 58 -OM Fwd_GETS 77 +OM Own_GETX 18 +OM Fwd_GETX 48 +OM Fwd_GETS 63 OM Fwd_DMA 0 <-- -OM Ack 57 -OM All_acks 4673 +OM Ack 91 +OM All_acks 4636 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 117 -IS Exclusive_Data 8201 +IS Data 109 +IS Exclusive_Data 8266 SI Load 0 <-- SI Ifetch 0 <-- @@ -1036,113 +1036,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 4 --- - Event Counts - -Load 99795 +Load 99119 Ifetch 0 -Store 53955 +Store 53227 L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22437 -Fwd_GETS 41296 +Own_GETX 13 +Fwd_GETX 22967 +Fwd_GETS 40211 Fwd_DMA 0 Inv 103 -Ack 4715 -Data 119 -Exclusive_Data 12950 +Ack 4660 +Data 111 +Exclusive_Data 12833 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4613 -Use_Timeout 12961 +All_acks 4559 +Use_Timeout 12845 - Transitions - -I Load 8468 +I Load 8399 I Ifetch 0 <-- -I Store 4465 +I Store 4426 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 183 +S Load 162 S Ifetch 0 <-- -S Store 100 +S Store 91 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 19 +S Inv 20 -O Load 97 +O Load 44 O Ifetch 0 <-- -O Store 49 +O Store 42 O L1_Replacement 0 <-- -O Fwd_GETX 5 -O Fwd_GETS 4 +O Fwd_GETX 0 <-- +O Fwd_GETS 2 O Fwd_DMA 0 <-- -M Load 132 +M Load 112 M Ifetch 0 <-- -M Store 65 +M Store 68 M L1_Replacement 0 <-- -M Fwd_GETX 37 -M Fwd_GETS 54 +M Fwd_GETX 27 +M Fwd_GETS 42 M Fwd_DMA 0 <-- -M_W Load 15376 +M_W Load 14685 M_W Ifetch 0 <-- -M_W Store 8192 +M_W Store 8150 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1382 -M_W Fwd_GETS 2630 +M_W Fwd_GETX 1379 +M_W Fwd_GETS 2445 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 156 +M_W Use_Timeout 137 -MM Load 11543 +MM Load 11415 MM Ifetch 0 <-- -MM Store 6269 +MM Store 6224 MM L1_Replacement 0 <-- -MM Fwd_GETX 4521 -MM Fwd_GETS 8349 +MM Fwd_GETX 4639 +MM Fwd_GETS 8137 MM Fwd_DMA 0 <-- -MM_W Load 63996 +MM_W Load 64302 MM_W Ifetch 0 <-- -MM_W Store 34815 +MM_W Store 34226 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16454 -MM_W Fwd_GETS 30219 +MM_W Fwd_GETX 16893 +MM_W Fwd_GETS 29536 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12805 +MM_W Use_Timeout 12708 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4614 +IM Ack 4561 IM Data 0 <-- -IM Exclusive_Data 4586 +IM Exclusive_Data 4538 SM Load 0 <-- SM Ifetch 0 <-- @@ -1150,29 +1150,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 29 +SM Inv 83 +SM Ack 13 SM Data 0 <-- -SM Exclusive_Data 16 +SM Exclusive_Data 8 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 38 -OM Fwd_GETS 40 +OM Own_GETX 13 +OM Fwd_GETX 29 +OM Fwd_GETS 49 OM Fwd_DMA 0 <-- -OM Ack 72 -OM All_acks 4613 +OM Ack 86 +OM All_acks 4559 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 119 -IS Exclusive_Data 8348 +IS Data 111 +IS Exclusive_Data 8287 SI Load 0 <-- SI Ifetch 0 <-- @@ -1216,113 +1216,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 5 --- - Event Counts - -Load 99739 +Load 96993 Ifetch 0 -Store 53481 +Store 52753 L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22829 -Fwd_GETS 40648 +Own_GETX 12 +Fwd_GETX 22235 +Fwd_GETS 39902 Fwd_DMA 0 -Inv 102 -Ack 4616 -Data 118 -Exclusive_Data 12902 +Inv 93 +Ack 4664 +Data 99 +Exclusive_Data 12623 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4488 -Use_Timeout 12913 +All_acks 4571 +Use_Timeout 12635 - Transitions - -I Load 8545 +I Load 8165 I Ifetch 0 <-- -I Store 4332 +I Store 4435 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 143 +S Load 169 S Ifetch 0 <-- -S Store 107 +S Store 85 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 11 +S Inv 14 -O Load 59 +O Load 80 O Ifetch 0 <-- -O Store 49 +O Store 51 O L1_Replacement 0 <-- O Fwd_GETX 1 -O Fwd_GETS 1 +O Fwd_GETS 2 O Fwd_DMA 0 <-- -M Load 116 +M Load 113 M Ifetch 0 <-- -M Store 73 +M Store 61 M L1_Replacement 0 <-- -M Fwd_GETX 34 -M Fwd_GETS 50 +M Fwd_GETX 32 +M Fwd_GETS 52 M Fwd_DMA 0 <-- -M_W Load 15492 +M_W Load 14722 M_W Ifetch 0 <-- -M_W Store 8268 +M_W Store 7919 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1474 -M_W Fwd_GETS 2608 +M_W Fwd_GETX 1407 +M_W Fwd_GETS 2459 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 157 +M_W Use_Timeout 145 -MM Load 11554 +MM Load 11363 MM Ifetch 0 <-- -MM Store 6300 +MM Store 6174 MM L1_Replacement 0 <-- -MM Fwd_GETX 4609 -MM Fwd_GETS 8220 +MM Fwd_GETX 4487 +MM Fwd_GETS 8064 MM Fwd_DMA 0 <-- -MM_W Load 63830 +MM_W Load 62381 MM_W Ifetch 0 <-- -MM_W Store 34352 +MM_W Store 34028 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16673 -MM_W Fwd_GETS 29721 +MM_W Fwd_GETX 16269 +MM_W Fwd_GETS 29277 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12756 +MM_W Use_Timeout 12490 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4494 +IM Ack 4586 IM Data 0 <-- -IM Exclusive_Data 4461 +IM Exclusive_Data 4553 SM Load 0 <-- SM Ifetch 0 <-- @@ -1330,29 +1330,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 91 -SM Ack 29 +SM Inv 79 +SM Ack 14 SM Data 0 <-- -SM Exclusive_Data 16 +SM Exclusive_Data 6 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 38 +OM Own_GETX 12 +OM Fwd_GETX 39 OM Fwd_GETS 48 OM Fwd_DMA 0 <-- -OM Ack 93 -OM All_acks 4488 +OM Ack 64 +OM All_acks 4571 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 118 -IS Exclusive_Data 8425 +IS Data 99 +IS Exclusive_Data 8064 SI Load 0 <-- SI Ifetch 0 <-- @@ -1396,113 +1396,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 6 --- - Event Counts - -Load 100001 +Load 98714 Ifetch 0 -Store 53654 +Store 52959 L1_Replacement 0 -Own_GETX 16 -Fwd_GETX 22688 -Fwd_GETS 40941 +Own_GETX 11 +Fwd_GETX 22265 +Fwd_GETS 40575 Fwd_DMA 0 -Inv 98 -Ack 4732 -Data 112 -Exclusive_Data 12919 +Inv 105 +Ack 4683 +Data 120 +Exclusive_Data 12792 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4621 -Use_Timeout 12934 +All_acks 4582 +Use_Timeout 12803 - Transitions - -I Load 8427 +I Load 8342 I Ifetch 0 <-- -I Store 4464 +I Store 4436 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 142 +S Load 244 S Ifetch 0 <-- -S Store 98 +S Store 105 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 14 +S Inv 15 -O Load 101 +O Load 55 O Ifetch 0 <-- -O Store 59 +O Store 42 O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 4 +O Fwd_GETX 0 <-- +O Fwd_GETS 1 O Fwd_DMA 0 <-- -M Load 128 +M Load 104 M Ifetch 0 <-- -M Store 65 +M Store 69 M L1_Replacement 0 <-- -M Fwd_GETX 31 -M Fwd_GETS 61 +M Fwd_GETX 24 +M Fwd_GETS 42 M Fwd_DMA 0 <-- -M_W Load 15324 +M_W Load 14705 M_W Ifetch 0 <-- -M_W Store 8157 +M_W Store 8086 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1433 -M_W Fwd_GETS 2557 +M_W Fwd_GETX 1322 +M_W Fwd_GETS 2502 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 157 +M_W Use_Timeout 135 -MM Load 11583 +MM Load 11345 MM Ifetch 0 <-- -MM Store 6297 +MM Store 6118 MM L1_Replacement 0 <-- -MM Fwd_GETX 4582 -MM Fwd_GETS 8260 +MM Fwd_GETX 4507 +MM Fwd_GETS 8230 MM Fwd_DMA 0 <-- -MM_W Load 64296 +MM_W Load 63919 MM_W Ifetch 0 <-- -MM_W Store 34514 +MM_W Store 34103 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16597 -MM_W Fwd_GETS 29998 +MM_W Fwd_GETX 16381 +MM_W Fwd_GETS 29775 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12777 +MM_W Use_Timeout 12668 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4614 +IM Ack 4577 IM Data 0 <-- -IM Exclusive_Data 4591 +IM Exclusive_Data 4556 SM Load 0 <-- SM Ifetch 0 <-- @@ -1510,29 +1510,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 29 +SM Inv 90 +SM Ack 34 SM Data 0 <-- -SM Exclusive_Data 14 +SM Exclusive_Data 15 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 16 -OM Fwd_GETX 43 -OM Fwd_GETS 61 +OM Own_GETX 11 +OM Fwd_GETX 31 +OM Fwd_GETS 25 OM Fwd_DMA 0 <-- -OM Ack 89 -OM All_acks 4621 +OM Ack 72 +OM All_acks 4582 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 112 -IS Exclusive_Data 8314 +IS Data 120 +IS Exclusive_Data 8221 SI Load 0 <-- SI Ifetch 0 <-- @@ -1576,113 +1576,113 @@ II Writeback_Ack 0 <-- II Writeback_Ack_Data 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 7 --- - Event Counts - -Load 98992 +Load 97921 Ifetch 0 -Store 53546 +Store 52935 L1_Replacement 0 -Own_GETX 16 -Fwd_GETX 22318 -Fwd_GETS 40836 +Own_GETX 14 +Fwd_GETX 22349 +Fwd_GETS 40209 Fwd_DMA 0 -Inv 116 -Ack 4785 -Data 125 -Exclusive_Data 12839 +Inv 88 +Ack 4708 +Data 96 +Exclusive_Data 12694 Writeback_Ack 0 Writeback_Ack_Data 0 Writeback_Nack 0 -All_acks 4665 -Use_Timeout 12854 +All_acks 4627 +Use_Timeout 12708 - Transitions - -I Load 8316 +I Load 8179 I Ifetch 0 <-- -I Store 4506 +I Store 4477 I L1_Replacement 0 <-- I Inv 0 <-- -S Load 205 +S Load 123 S Ifetch 0 <-- -S Store 104 +S Store 88 S L1_Replacement 0 <-- S Fwd_GETS 0 <-- S Fwd_DMA 0 <-- -S Inv 21 +S Inv 8 -O Load 96 +O Load 138 O Ifetch 0 <-- -O Store 55 +O Store 62 O L1_Replacement 0 <-- O Fwd_GETX 4 -O Fwd_GETS 4 +O Fwd_GETS 2 O Fwd_DMA 0 <-- -M Load 145 +M Load 126 M Ifetch 0 <-- -M Store 63 +M Store 68 M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 59 +M Fwd_GETX 25 +M Fwd_GETS 66 M Fwd_DMA 0 <-- -M_W Load 14823 +M_W Load 14685 M_W Ifetch 0 <-- -M_W Store 8036 +M_W Store 7922 M_W L1_Replacement 0 <-- M_W Own_GETX 0 <-- -M_W Fwd_GETX 1327 -M_W Fwd_GETS 2573 +M_W Fwd_GETX 1316 +M_W Fwd_GETS 2538 M_W Fwd_DMA 0 <-- M_W Inv 0 <-- -M_W Use_Timeout 154 +M_W Use_Timeout 159 -MM Load 11394 +MM Load 11522 MM Ifetch 0 <-- -MM Store 6188 +MM Store 6028 MM L1_Replacement 0 <-- -MM Fwd_GETX 4510 -MM Fwd_GETS 8253 +MM Fwd_GETX 4512 +MM Fwd_GETS 8105 MM Fwd_DMA 0 <-- -MM_W Load 64013 +MM_W Load 63148 MM_W Ifetch 0 <-- -MM_W Store 34594 +MM_W Store 34290 MM_W L1_Replacement 0 <-- MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16406 -MM_W Fwd_GETS 29893 +MM_W Fwd_GETX 16444 +MM_W Fwd_GETS 29421 MM_W Fwd_DMA 0 <-- MM_W Inv 0 <-- -MM_W Use_Timeout 12700 +MM_W Use_Timeout 12549 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Inv 0 <-- -IM Ack 4682 +IM Ack 4621 IM Data 0 <-- -IM Exclusive_Data 4640 +IM Exclusive_Data 4605 SM Load 0 <-- SM Ifetch 0 <-- @@ -1690,29 +1690,29 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Fwd_GETS 0 <-- SM Fwd_DMA 0 <-- -SM Inv 95 -SM Ack 18 +SM Inv 80 +SM Ack 16 SM Data 0 <-- -SM Exclusive_Data 9 +SM Exclusive_Data 8 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L1_Replacement 0 <-- -OM Own_GETX 16 -OM Fwd_GETX 39 -OM Fwd_GETS 54 +OM Own_GETX 14 +OM Fwd_GETX 48 +OM Fwd_GETS 77 OM Fwd_DMA 0 <-- -OM Ack 85 -OM All_acks 4665 +OM Ack 71 +OM All_acks 4627 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Inv 0 <-- -IS Data 125 -IS Exclusive_Data 8190 +IS Data 96 +IS Exclusive_Data 8081 SI Load 0 <-- SI Ifetch 0 <-- @@ -1767,8 +1767,8 @@ Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory --- L2Cache 0 --- - Event Counts - -L1_GETS 2730499 -L1_GETX 1517781 +L1_GETS 2706421 +L1_GETX 1509888 L1_PUTO 0 L1_PUTX 0 L1_PUTS_only 0 @@ -1780,20 +1780,20 @@ Own_GETX 0 Inv 0 IntAck 0 ExtAck 0 -All_Acks 2 -Data 2 -Data_Exclusive 0 +All_Acks 1 +Data 1 +Data_Exclusive 1 L1_WBCLEANDATA 0 L1_WBDIRTYDATA 0 Writeback_Ack 0 Writeback_Nack 0 -Unblock 933 -Exclusive_Unblock 103229 +Unblock 856 +Exclusive_Unblock 102483 L2_Replacement 0 - Transitions - -NP L1_GETS 0 <-- -NP L1_GETX 2 +NP L1_GETS 1 +NP L1_GETX 1 NP L1_PUTO 0 <-- NP L1_PUTX 0 <-- NP L1_PUTS 0 <-- @@ -1816,8 +1816,8 @@ ILS L1_PUTS 0 <-- ILS Inv 0 <-- ILS L2_Replacement 0 <-- -ILX L1_GETS 66548 -ILX L1_GETX 36681 +ILX L1_GETS 66011 +ILX L1_GETX 36472 ILX L1_PUTO 0 <-- ILX L1_PUTX 0 <-- ILX L1_PUTS_only 0 <-- @@ -1863,8 +1863,8 @@ ILOS Fwd_DMA 0 <-- ILOS Data 0 <-- ILOS L2_Replacement 0 <-- -ILOSX L1_GETS 464 -ILOSX L1_GETX 469 +ILOSX L1_GETS 432 +ILOSX L1_GETX 424 ILOSX L1_PUTO 0 <-- ILOSX L1_PUTX 0 <-- ILOSX L1_PUTS_only 0 <-- @@ -2231,8 +2231,8 @@ IFLOX Unblock 0 <-- IFLOX Exclusive_Unblock 0 <-- IFLOX L2_Replacement 0 <-- -IFLOXX L1_GETS 2656172 -IFLOXX L1_GETX 1471349 +IFLOXX L1_GETS 2633310 +IFLOXX L1_GETX 1464389 IFLOXX L1_PUTO 0 <-- IFLOXX L1_PUTX 0 <-- IFLOXX L1_PUTS_only 0 <-- @@ -2241,12 +2241,12 @@ IFLOXX Fwd_GETX 0 <-- IFLOXX Fwd_GETS 0 <-- IFLOXX Fwd_DMA 0 <-- IFLOXX Inv 0 <-- -IFLOXX Unblock 469 -IFLOXX Exclusive_Unblock 102758 +IFLOXX Unblock 424 +IFLOXX Exclusive_Unblock 102057 IFLOXX L2_Replacement 0 <-- -IFLOSX L1_GETS 3369 -IFLOSX L1_GETX 4420 +IFLOSX L1_GETS 3100 +IFLOSX L1_GETX 4155 IFLOSX L1_PUTO 0 <-- IFLOSX L1_PUTX 0 <-- IFLOSX L1_PUTS_only 0 <-- @@ -2255,12 +2255,12 @@ IFLOSX Fwd_GETX 0 <-- IFLOSX Fwd_GETS 0 <-- IFLOSX Fwd_DMA 0 <-- IFLOSX Inv 0 <-- -IFLOSX Unblock 464 +IFLOSX Unblock 432 IFLOSX Exclusive_Unblock 0 <-- IFLOSX L2_Replacement 0 <-- -IFLXO L1_GETS 3686 -IFLXO L1_GETX 4665 +IFLXO L1_GETS 3334 +IFLXO L1_GETX 4226 IFLXO L1_PUTO 0 <-- IFLXO L1_PUTX 0 <-- IFLXO L1_PUTS_only 0 <-- @@ -2269,11 +2269,11 @@ IFLXO Fwd_GETX 0 <-- IFLXO Fwd_GETS 0 <-- IFLXO Fwd_DMA 0 <-- IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 469 +IFLXO Exclusive_Unblock 424 IFLXO L2_Replacement 0 <-- -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- +IGS L1_GETS 81 +IGS L1_GETX 107 IGS L1_PUTO 0 <-- IGS L1_PUTX 0 <-- IGS L1_PUTS_only 0 <-- @@ -2284,13 +2284,13 @@ IGS Fwd_DMA 0 <-- IGS Own_GETX 0 <-- IGS Inv 0 <-- IGS Data 0 <-- -IGS Data_Exclusive 0 <-- +IGS Data_Exclusive 1 IGS Unblock 0 <-- -IGS Exclusive_Unblock 0 <-- +IGS Exclusive_Unblock 1 IGS L2_Replacement 0 <-- -IGM L1_GETS 244 -IGM L1_GETX 183 +IGM L1_GETS 144 +IGM L1_GETX 108 IGM L1_PUTO 0 <-- IGM L1_PUTX 0 <-- IGM L1_PUTS_only 0 <-- @@ -2301,7 +2301,7 @@ IGM Fwd_DMA 0 <-- IGM Own_GETX 0 <-- IGM Inv 0 <-- IGM ExtAck 0 <-- -IGM Data 2 +IGM Data 1 IGM Data_Exclusive 0 <-- IGM L2_Replacement 0 <-- @@ -2319,8 +2319,8 @@ IGMLS Data 0 <-- IGMLS Data_Exclusive 0 <-- IGMLS L2_Replacement 0 <-- -IGMO L1_GETS 16 -IGMO L1_GETX 12 +IGMO L1_GETS 8 +IGMO L1_GETX 6 IGMO L1_PUTO 0 <-- IGMO L1_PUTX 0 <-- IGMO L1_PUTS_only 0 <-- @@ -2330,8 +2330,8 @@ IGMO Fwd_GETS 0 <-- IGMO Fwd_DMA 0 <-- IGMO Own_GETX 0 <-- IGMO ExtAck 0 <-- -IGMO All_Acks 2 -IGMO Exclusive_Unblock 2 +IGMO All_Acks 1 +IGMO Exclusive_Unblock 1 IGMO L2_Replacement 0 <-- IGMIO L1_GETS 0 <-- @@ -2560,8 +2560,8 @@ Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: --- Directory 0 --- - Event Counts - -GETX 2 -GETS 0 +GETX 1 +GETS 1 PUTX 0 PUTO 0 PUTO_SHARERS 0 @@ -2577,8 +2577,8 @@ DMA_WRITE 0 Data 0 - Transitions - -I GETX 2 -I GETS 0 <-- +I GETX 1 +I GETS 1 I PUTX 0 <-- I PUTO 0 <-- I Memory_Data 0 <-- @@ -2621,8 +2621,8 @@ IS PUTX 0 <-- IS PUTO 0 <-- IS PUTO_SHARERS 0 <-- IS Unblock 0 <-- -IS Exclusive_Unblock 0 <-- -IS Memory_Data 0 <-- +IS Exclusive_Unblock 1 +IS Memory_Data 1 IS Memory_Ack 0 <-- IS DMA_READ 0 <-- IS DMA_WRITE 0 <-- @@ -2668,8 +2668,8 @@ MM GETS 0 <-- MM PUTX 0 <-- MM PUTO 0 <-- MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 2 -MM Memory_Data 2 +MM Exclusive_Unblock 1 +MM Memory_Data 1 MM Memory_Ack 0 <-- MM DMA_READ 0 <-- MM DMA_WRITE 0 <-- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr index c6717f0fd..2f54bd8e2 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @333700 -system.cpu3: completed 10000 read accesses @335770 -system.cpu4: completed 10000 read accesses @336327 -system.cpu1: completed 10000 read accesses @339698 -system.cpu2: completed 10000 read accesses @344150 -system.cpu6: completed 10000 read accesses @345138 -system.cpu7: completed 10000 read accesses @345167 -system.cpu0: completed 10000 read accesses @349190 -system.cpu6: completed 20000 read accesses @673266 -system.cpu5: completed 20000 read accesses @676289 -system.cpu7: completed 20000 read accesses @679722 -system.cpu3: completed 20000 read accesses @681408 -system.cpu4: completed 20000 read accesses @681933 -system.cpu2: completed 20000 read accesses @683973 -system.cpu0: completed 20000 read accesses @686720 -system.cpu1: completed 20000 read accesses @692941 -system.cpu4: completed 30000 read accesses @1007235 -system.cpu6: completed 30000 read accesses @1011621 -system.cpu7: completed 30000 read accesses @1013787 -system.cpu3: completed 30000 read accesses @1022376 -system.cpu1: completed 30000 read accesses @1026321 -system.cpu0: completed 30000 read accesses @1027922 -system.cpu5: completed 30000 read accesses @1030676 -system.cpu2: completed 30000 read accesses @1030823 -system.cpu6: completed 40000 read accesses @1348685 -system.cpu3: completed 40000 read accesses @1353011 -system.cpu4: completed 40000 read accesses @1356076 -system.cpu7: completed 40000 read accesses @1357286 -system.cpu1: completed 40000 read accesses @1359706 -system.cpu5: completed 40000 read accesses @1367254 -system.cpu2: completed 40000 read accesses @1373741 -system.cpu0: completed 40000 read accesses @1379957 -system.cpu4: completed 50000 read accesses @1688392 -system.cpu7: completed 50000 read accesses @1689568 -system.cpu6: completed 50000 read accesses @1689754 -system.cpu3: completed 50000 read accesses @1696699 -system.cpu1: completed 50000 read accesses @1706109 -system.cpu5: completed 50000 read accesses @1712886 -system.cpu2: completed 50000 read accesses @1716788 -system.cpu0: completed 50000 read accesses @1719320 -system.cpu7: completed 60000 read accesses @2028845 -system.cpu6: completed 60000 read accesses @2029028 -system.cpu3: completed 60000 read accesses @2030491 -system.cpu1: completed 60000 read accesses @2034867 -system.cpu4: completed 60000 read accesses @2042771 -system.cpu5: completed 60000 read accesses @2052491 -system.cpu2: completed 60000 read accesses @2054050 -system.cpu0: completed 60000 read accesses @2059964 -system.cpu1: completed 70000 read accesses @2366182 -system.cpu3: completed 70000 read accesses @2371740 -system.cpu6: completed 70000 read accesses @2378180 -system.cpu7: completed 70000 read accesses @2384422 -system.cpu4: completed 70000 read accesses @2385664 -system.cpu5: completed 70000 read accesses @2386969 -system.cpu0: completed 70000 read accesses @2391802 -system.cpu2: completed 70000 read accesses @2394315 -system.cpu1: completed 80000 read accesses @2697050 -system.cpu3: completed 80000 read accesses @2711777 -system.cpu5: completed 80000 read accesses @2712887 -system.cpu6: completed 80000 read accesses @2716967 -system.cpu7: completed 80000 read accesses @2729293 -system.cpu4: completed 80000 read accesses @2732109 -system.cpu0: completed 80000 read accesses @2735916 -system.cpu2: completed 80000 read accesses @2746698 -system.cpu5: completed 90000 read accesses @3042585 -system.cpu1: completed 90000 read accesses @3050146 -system.cpu4: completed 90000 read accesses @3051611 -system.cpu6: completed 90000 read accesses @3054450 -system.cpu3: completed 90000 read accesses @3060838 -system.cpu7: completed 90000 read accesses @3073385 -system.cpu0: completed 90000 read accesses @3084850 -system.cpu2: completed 90000 read accesses @3085570 -system.cpu6: completed 100000 read accesses @3383480 +system.cpu6: completed 10000 read accesses @325901 +system.cpu4: completed 10000 read accesses @333477 +system.cpu2: completed 10000 read accesses @337264 +system.cpu7: completed 10000 read accesses @338212 +system.cpu0: completed 10000 read accesses @341315 +system.cpu5: completed 10000 read accesses @343794 +system.cpu1: completed 10000 read accesses @347258 +system.cpu3: completed 10000 read accesses @349679 +system.cpu6: completed 20000 read accesses @662679 +system.cpu7: completed 20000 read accesses @663435 +system.cpu4: completed 20000 read accesses @670972 +system.cpu1: completed 20000 read accesses @674886 +system.cpu2: completed 20000 read accesses @675526 +system.cpu0: completed 20000 read accesses @687421 +system.cpu5: completed 20000 read accesses @695852 +system.cpu3: completed 20000 read accesses @698570 +system.cpu6: completed 30000 read accesses @1001408 +system.cpu1: completed 30000 read accesses @1004487 +system.cpu2: completed 30000 read accesses @1007345 +system.cpu4: completed 30000 read accesses @1009967 +system.cpu0: completed 30000 read accesses @1021321 +system.cpu7: completed 30000 read accesses @1025248 +system.cpu3: completed 30000 read accesses @1040400 +system.cpu5: completed 30000 read accesses @1042444 +system.cpu6: completed 40000 read accesses @1335158 +system.cpu1: completed 40000 read accesses @1341837 +system.cpu4: completed 40000 read accesses @1347757 +system.cpu2: completed 40000 read accesses @1348137 +system.cpu3: completed 40000 read accesses @1370930 +system.cpu0: completed 40000 read accesses @1372862 +system.cpu7: completed 40000 read accesses @1374480 +system.cpu5: completed 40000 read accesses @1395059 +system.cpu6: completed 50000 read accesses @1663756 +system.cpu2: completed 50000 read accesses @1676262 +system.cpu1: completed 50000 read accesses @1676376 +system.cpu4: completed 50000 read accesses @1689367 +system.cpu3: completed 50000 read accesses @1707722 +system.cpu7: completed 50000 read accesses @1715376 +system.cpu0: completed 50000 read accesses @1719053 +system.cpu5: completed 50000 read accesses @1756410 +system.cpu2: completed 60000 read accesses @1996507 +system.cpu6: completed 60000 read accesses @2009287 +system.cpu1: completed 60000 read accesses @2021631 +system.cpu4: completed 60000 read accesses @2032125 +system.cpu3: completed 60000 read accesses @2046121 +system.cpu7: completed 60000 read accesses @2054305 +system.cpu0: completed 60000 read accesses @2067865 +system.cpu5: completed 60000 read accesses @2103289 +system.cpu2: completed 70000 read accesses @2336053 +system.cpu6: completed 70000 read accesses @2351727 +system.cpu1: completed 70000 read accesses @2362242 +system.cpu3: completed 70000 read accesses @2365041 +system.cpu4: completed 70000 read accesses @2374894 +system.cpu7: completed 70000 read accesses @2393230 +system.cpu0: completed 70000 read accesses @2409417 +system.cpu5: completed 70000 read accesses @2444673 +system.cpu2: completed 80000 read accesses @2681751 +system.cpu1: completed 80000 read accesses @2695221 +system.cpu6: completed 80000 read accesses @2701603 +system.cpu3: completed 80000 read accesses @2708122 +system.cpu4: completed 80000 read accesses @2715599 +system.cpu7: completed 80000 read accesses @2739434 +system.cpu0: completed 80000 read accesses @2743943 +system.cpu5: completed 80000 read accesses @2780520 +system.cpu2: completed 90000 read accesses @3022424 +system.cpu1: completed 90000 read accesses @3030742 +system.cpu3: completed 90000 read accesses @3042635 +system.cpu6: completed 90000 read accesses @3050919 +system.cpu4: completed 90000 read accesses @3054095 +system.cpu0: completed 90000 read accesses @3084803 +system.cpu7: completed 90000 read accesses @3091274 +system.cpu5: completed 90000 read accesses @3116487 +system.cpu2: completed 100000 read accesses @3358188 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 5c8c91abe..45cec6b56 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:39:50 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:38:22 -M5 executing on cabr0210 -command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory +M5 compiled Jul 1 2010 14:38:10 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:39:45 +M5 executing on phenom +command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3383480 because maximum number of loads reached +Exiting @ tick 3358188 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index e9535f029..f32bc9111 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340176 # Number of bytes of host memory used -host_seconds 30.43 # Real time elapsed on the host -host_tick_rate 111176 # Simulator tick rate (ticks/s) +host_mem_usage 332872 # Number of bytes of host memory used +host_seconds 24.53 # Real time elapsed on the host +host_tick_rate 136908 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003383 # Number of seconds simulated -sim_ticks 3383480 # Number of ticks simulated +sim_seconds 0.003358 # Number of seconds simulated +sim_ticks 3358188 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99022 # number of read accesses completed -system.cpu0.num_writes 53581 # number of write accesses completed +system.cpu0.num_reads 98036 # number of read accesses completed +system.cpu0.num_writes 52677 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99831 # number of read accesses completed -system.cpu1.num_writes 53533 # number of write accesses completed +system.cpu1.num_reads 99903 # number of read accesses completed +system.cpu1.num_writes 53671 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98646 # number of read accesses completed -system.cpu2.num_writes 53693 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 53360 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99440 # number of read accesses completed -system.cpu3.num_writes 53404 # number of write accesses completed +system.cpu3.num_reads 99545 # number of read accesses completed +system.cpu3.num_writes 53578 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99794 # number of read accesses completed -system.cpu4.num_writes 53954 # number of write accesses completed +system.cpu4.num_reads 99118 # number of read accesses completed +system.cpu4.num_writes 53226 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99737 # number of read accesses completed -system.cpu5.num_writes 53481 # number of write accesses completed +system.cpu5.num_reads 96991 # number of read accesses completed +system.cpu5.num_writes 52753 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53654 # number of write accesses completed +system.cpu6.num_reads 98713 # number of read accesses completed +system.cpu6.num_writes 52958 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98991 # number of read accesses completed -system.cpu7.num_writes 53546 # number of write accesses completed +system.cpu7.num_reads 97919 # number of read accesses completed +system.cpu7.num_writes 52935 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index ca0411c69..460712819 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -22,7 +22,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest @@ -37,7 +37,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest @@ -52,7 +52,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest @@ -67,7 +67,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest @@ -82,7 +82,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest @@ -97,7 +97,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest @@ -112,7 +112,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest @@ -127,7 +127,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports7.port[0] [system.funcmem] type=PhysicalMemory @@ -147,11 +147,11 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer block_size_bytes=64 clock=1 debug=system.ruby.debug @@ -164,6 +164,102 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + [system.ruby.debug] type=RubyDebug filter_string=none @@ -202,9 +298,9 @@ weight=1 [system.ruby.network.topology.ext_links0.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -215,31 +311,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -257,9 +340,9 @@ weight=1 [system.ruby.network.topology.ext_links1.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -270,31 +353,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -312,9 +382,9 @@ weight=1 [system.ruby.network.topology.ext_links2.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -325,31 +395,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -367,9 +424,9 @@ weight=1 [system.ruby.network.topology.ext_links3.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -380,31 +437,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -422,9 +466,9 @@ weight=1 [system.ruby.network.topology.ext_links4.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -435,31 +479,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -477,9 +508,9 @@ weight=1 [system.ruby.network.topology.ext_links5.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -490,31 +521,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -532,9 +550,9 @@ weight=1 [system.ruby.network.topology.ext_links6.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -545,31 +563,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -587,9 +592,9 @@ weight=1 [system.ruby.network.topology.ext_links7.ext_node] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory N_tokens=9 buffer_size=0 dynamic_timeout_enabled=true @@ -600,31 +605,18 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index 5246c0e5c..036c1db6a 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:40:04 +Real time: Jul/01/2010 14:40:39 Profiler Stats -------------- -Elapsed_time_in_seconds: 34 -Elapsed_time_in_minutes: 0.566667 -Elapsed_time_in_hours: 0.00944444 -Elapsed_time_in_days: 0.000393519 +Elapsed_time_in_seconds: 26 +Elapsed_time_in_minutes: 0.433333 +Elapsed_time_in_hours: 0.00722222 +Elapsed_time_in_days: 0.000300926 -Virtual_time_in_seconds: 35 -Virtual_time_in_minutes: 0.583333 -Virtual_time_in_hours: 0.00972222 -Virtual_time_in_days: 0.000405093 +Virtual_time_in_seconds: 26.08 +Virtual_time_in_minutes: 0.434667 +Virtual_time_in_hours: 0.00724444 +Virtual_time_in_days: 0.000301852 -Ruby_current_time: 3238178 +Ruby_current_time: 3229931 Ruby_start_time: 0 -Ruby_cycles: 3238178 +Ruby_cycles: 3229931 -mbytes_resident: 31.2969 -mbytes_total: 332.305 -resident_ratio: 0.094193 +mbytes_resident: 32.3867 +mbytes_total: 325.047 +resident_ratio: 0.0996491 -ruby_cycles_executed: [ 3238179 3238179 3238179 3238179 3238179 3238179 3238179 3238179 ] +ruby_cycles_executed: [ 3229932 3229932 3229932 3229932 3229932 3229932 3229932 3229932 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,13 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1212936 average: 1.98562 | standard deviation: 0.119047 | 0 17440 1195496 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1209436 average: 1.99443 | standard deviation: 0.0744408 | 0 6739 1202697 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1024 count: 1212921 average: 40.7149 | standard deviation: 150.899 | 1141490 0 116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68318 1609 231 251 277 280 196 67 26 21 0 1 0 0 5 14 8 1 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 1024 count: 788284 average: 40.6125 | standard deviation: 150.71 | 742060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44290 1039 145 159 184 181 128 48 20 11 0 0 0 0 4 5 4 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 950 count: 424637 average: 40.905 | standard deviation: 151.251 | 399430 0 116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24028 570 86 92 93 99 68 19 6 10 0 1 0 0 1 9 4 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1074 count: 1209420 average: 40.7265 | standard deviation: 150.859 | 1138116 0 121 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69534 1022 106 161 136 90 74 14 17 8 0 0 0 0 0 6 4 1 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 8 max: 949 count: 786341 average: 40.6919 | standard deviation: 150.795 | 740099 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45198 631 68 105 94 61 49 6 10 8 0 0 0 0 0 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 8 max: 1074 count: 423079 average: 40.7906 | standard deviation: 150.976 | 398017 0 121 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24336 391 38 56 42 29 25 8 7 0 0 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,281 +103,281 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 34 +user_time: 26 system_time: 0 -page_reclaims: 9009 +page_reclaims: 8508 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 24 +block_outputs: 72 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.151519 - links_utilized_percent_switch_0_link_0: 0.110184 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.192854 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 17866 142928 [ 0 17866 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 8916 71328 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 17828 142624 [ 0 0 0 17828 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.151652 + links_utilized_percent_switch_0_link_0: 0.110271 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.193034 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 62398 499184 [ 0 62398 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 17840 142720 [ 0 17840 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 8902 640944 [ 0 0 0 0 8902 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 8900 71200 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151526 - links_utilized_percent_switch_1_link_0: 0.110191 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.192862 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 62515 500120 [ 0 62515 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 17860 142880 [ 0 17860 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 8917 71336 [ 0 0 0 0 8917 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Persistent_Control: 17829 142632 [ 0 0 0 17829 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.151663 + links_utilized_percent_switch_1_link_0: 0.110278 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.193049 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 8901 640872 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 8900 71200 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Persistent_Control: 17796 142368 [ 0 0 0 17796 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.151534 - links_utilized_percent_switch_2_link_0: 0.11019 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.192879 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 62516 500128 [ 0 62516 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 17858 142864 [ 0 17858 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 8918 71344 [ 0 0 0 0 8918 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Persistent_Control: 17832 142656 [ 0 0 0 17832 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.151622 + links_utilized_percent_switch_2_link_0: 0.110265 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.192979 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 8896 640512 [ 0 0 0 0 8896 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 8901 71208 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Persistent_Control: 17795 142360 [ 0 0 0 17795 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.151566 - links_utilized_percent_switch_3_link_0: 0.110202 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.192929 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 62513 500104 [ 0 62513 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 14 1008 [ 0 0 0 0 14 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 17864 142912 [ 0 17864 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 8917 642024 [ 0 0 0 0 8917 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.151632 + links_utilized_percent_switch_3_link_0: 0.110268 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.192996 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 17832 142656 [ 0 17832 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 8901 71208 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 17795 142360 [ 0 0 0 17795 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.151524 - links_utilized_percent_switch_4_link_0: 0.110187 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.192862 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 17866 142928 [ 0 17866 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 8914 71312 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.151623 + links_utilized_percent_switch_4_link_0: 0.110263 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.192984 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 17830 142640 [ 0 17830 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 8893 640296 [ 0 0 0 0 8893 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 8903 71224 [ 0 0 0 0 8903 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Persistent_Control: 17796 142368 [ 0 0 0 17796 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.151513 - links_utilized_percent_switch_5_link_0: 0.110184 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.192843 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 62514 500112 [ 0 62514 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 8 64 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 17862 142896 [ 0 17862 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.151636 + links_utilized_percent_switch_5_link_0: 0.110271 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.193001 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 62407 499256 [ 0 62407 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 17822 142576 [ 0 17822 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 8901 640872 [ 0 0 0 0 8901 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_5_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 8897 71176 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.151473 - links_utilized_percent_switch_6_link_0: 0.110172 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.192775 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 62522 500176 [ 0 62522 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 17846 142768 [ 0 17846 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 8909 641448 [ 0 0 0 0 8909 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 8919 71352 [ 0 0 0 0 8919 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Persistent_Control: 17830 142640 [ 0 0 0 17830 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.151646 + links_utilized_percent_switch_6_link_0: 0.110272 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.19302 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 17832 142656 [ 0 17832 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 8900 640800 [ 0 0 0 0 8900 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 8899 71192 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Persistent_Control: 17794 142352 [ 0 0 0 17794 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.151555 - links_utilized_percent_switch_7_link_0: 0.1102 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.192911 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 62511 500088 [ 0 62511 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 8914 641808 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 17868 142944 [ 0 17868 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 8920 642240 [ 0 0 0 0 8920 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Persistent_Control: 17828 142624 [ 0 0 0 17828 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.151601 + links_utilized_percent_switch_7_link_0: 0.110257 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.192945 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 62408 499264 [ 0 62408 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 17822 142576 [ 0 17822 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 8890 640080 [ 0 0 0 0 8890 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 8902 71216 [ 0 0 0 0 8902 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Persistent_Control: 17798 142384 [ 0 0 0 17798 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.110233 - links_utilized_percent_switch_8_link_0: 0.110149 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.110317 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.110314 + links_utilized_percent_switch_8_link_0: 0.110225 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.110402 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 71445 571560 [ 0 71445 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 71275 570200 [ 0 0 0 0 71275 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 71318 570544 [ 0 71318 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 71136 569088 [ 0 0 0 0 71136 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 0.0413315 - links_utilized_percent_switch_9_link_0: 0.0826352 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.77934e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.0413616 + links_utilized_percent_switch_9_link_0: 0.0826953 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.78644e-05 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.407695 - links_utilized_percent_switch_10_link_0: 0.413208 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.413234 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.413228 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.413285 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.413225 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.413211 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.413155 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.413271 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.440595 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 0.330541 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Persistent_Control: 124797 998376 [ 0 0 0 124797 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 62515 500120 [ 0 62515 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Persistent_Control: 124796 998368 [ 0 0 0 124796 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 62516 500128 [ 0 62516 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Persistent_Control: 124793 998344 [ 0 0 0 124793 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 62513 500104 [ 0 62513 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 14 1008 [ 0 0 0 0 14 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 62514 500112 [ 0 62514 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 8 64 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 62522 500176 [ 0 62522 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Persistent_Control: 124795 998360 [ 0 0 0 124795 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 62511 500088 [ 0 62511 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 8914 641808 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Persistent_Control: 124797 998376 [ 0 0 0 124797 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 71445 571560 [ 0 71445 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 71275 570200 [ 0 0 0 0 71275 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +links_utilized_percent_switch_10: 0.407988 + links_utilized_percent_switch_10_link_0: 0.41354 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.413561 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.413513 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.413526 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.413503 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.413538 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.413541 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.413475 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.440901 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 0.330781 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 62398 499184 [ 0 62398 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Persistent_Control: 124566 996528 [ 0 0 0 124566 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Persistent_Control: 124567 996536 [ 0 0 0 124567 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Persistent_Control: 124567 996536 [ 0 0 0 124567 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 62403 499224 [ 0 62403 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 8898 640656 [ 0 0 0 0 8898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 12 96 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Persistent_Control: 124566 996528 [ 0 0 0 124566 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 62407 499256 [ 0 62407 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 62402 499216 [ 0 62402 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 8897 640584 [ 0 0 0 0 8897 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Persistent_Control: 124568 996544 [ 0 0 0 124568 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 62408 499264 [ 0 62408 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 8899 640728 [ 0 0 0 0 8899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 9 72 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Persistent_Control: 124564 996512 [ 0 0 0 124564 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 71318 570544 [ 0 71318 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 71136 569088 [ 0 0 0 0 71136 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 71318 570544 [ 0 0 71318 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Persistent_Control: 142362 1138896 [ 0 0 0 142362 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 + + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 + + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 0 --- - Event Counts - -Load 99985 +Load 99666 Ifetch 0 -Store 54267 +Store 53551 L1_Replacement 0 Data_Shared 0 -Data_Owner 19 -Data_All_Tokens 8902 -Ack 0 -Ack_All_Tokens 10 +Data_Owner 16 +Data_All_Tokens 8891 +Ack 1 +Ack_All_Tokens 11 Transient_GETX 0 -Transient_Local_GETX 22004 +Transient_Local_GETX 21942 Transient_GETS 0 -Transient_Local_GETS 40508 +Transient_Local_GETS 40456 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25124 -Persistent_GETS 46317 -Own_Lock_or_Unlock 71183 -Request_Timeout 9369 -Use_TimeoutStarverX 2 -Use_TimeoutStarverS 5 -Use_TimeoutNoStarvers 8905 +Persistent_GETX 24652 +Persistent_GETS 45581 +Own_Lock_or_Unlock 72129 +Request_Timeout 9283 +Use_TimeoutStarverX 3 +Use_TimeoutStarverS 4 +Use_TimeoutNoStarvers 8895 - Transitions - -NP Load 1 +NP Load 2 NP Ifetch 0 <-- -NP Store 1 +NP Store 0 <-- NP Data_Shared 0 <-- NP Data_Owner 0 <-- NP Data_All_Tokens 0 <-- @@ -390,9 +390,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 9 +I Load 3 I Ifetch 0 <-- -I Store 1 +I Store 4 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -406,18 +406,18 @@ I Transient_GETS_Last_Token 0 <-- I Transient_Local_GETS_Last_Token 0 <-- I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 6 +I Own_Lock_or_Unlock 1 -S Load 6 +S Load 3 S Ifetch 0 <-- -S Store 3 +S Store 1 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 1 +S Transient_Local_GETX 2 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -426,77 +426,77 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 17 +O Load 13 O Ifetch 0 <-- -O Store 10 +O Store 11 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 9 +O Transient_Local_GETX 5 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 +O Own_Lock_or_Unlock 15 -M Load 134 +M Load 149 M Ifetch 0 <-- -M Store 70 +M Store 72 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 4 -M Persistent_GETS 13 -M Own_Lock_or_Unlock 65 +M Persistent_GETX 11 +M Persistent_GETS 14 +M Own_Lock_or_Unlock 72 -MM Load 39402 +MM Load 39155 MM Ifetch 0 <-- -MM Store 21439 +MM Store 21046 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3111 -MM Persistent_GETS 5777 -MM Own_Lock_or_Unlock 8638 +MM Persistent_GETX 3081 +MM Persistent_GETS 5789 +MM Own_Lock_or_Unlock 8681 -M_W Load 10158 +M_W Load 10405 M_W Ifetch 0 <-- -M_W Store 5618 +M_W Store 5678 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1506 +M_W Transient_Local_GETX 1514 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2887 +M_W Transient_Local_GETS 2959 M_W Persistent_GETX 0 <-- M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 21 +M_W Own_Lock_or_Unlock 11 M_W Use_TimeoutStarverX 0 <-- M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 87 +M_W Use_TimeoutNoStarvers 97 -MM_W Load 44523 +MM_W Load 44130 MM_W Ifetch 0 <-- -MM_W Store 23933 +MM_W Store 23628 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 964 +MM_W Transient_Local_GETX 947 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1719 -MM_W Persistent_GETX 2 -MM_W Persistent_GETS 5 -MM_W Own_Lock_or_Unlock 160 -MM_W Use_TimeoutStarverX 2 -MM_W Use_TimeoutStarverS 5 -MM_W Use_TimeoutNoStarvers 8818 +MM_W Transient_Local_GETS 1674 +MM_W Persistent_GETX 3 +MM_W Persistent_GETS 4 +MM_W Own_Lock_or_Unlock 116 +MM_W Use_TimeoutStarverX 3 +MM_W Use_TimeoutStarverS 4 +MM_W Use_TimeoutNoStarvers 8798 IM Load 0 <-- IM Ifetch 0 <-- @@ -504,18 +504,18 @@ IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- IM Data_Owner 0 <-- -IM Data_All_Tokens 3191 +IM Data_All_Tokens 3107 IM Ack 0 <-- IM Transient_GETX 0 <-- IM Transient_Local_GETX 273 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 439 +IM Transient_Local_GETS 409 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5569 -IM Persistent_GETS 10313 -IM Own_Lock_or_Unlock 3193 -IM Request_Timeout 2198 +IM Persistent_GETX 5555 +IM Persistent_GETS 10291 +IM Own_Lock_or_Unlock 3107 +IM Request_Timeout 2214 SM Load 0 <-- SM Ifetch 0 <-- @@ -523,12 +523,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 6 +SM Data_All_Tokens 9 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 +SM Transient_Local_GETX 3 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 +SM Transient_Local_GETS 0 <-- SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -543,11 +543,11 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 10 +OM Ack_All_Tokens 11 OM Transient_GETX 0 <-- OM Transient_Local_GETX 4 OM Transient_GETS 0 <-- -OM Transient_Local_GETS 2 +OM Transient_Local_GETS 1 OM Transient_GETS_Last_Token 0 <-- OM Transient_Local_GETS_Last_Token 0 <-- OM Persistent_GETX 0 <-- @@ -560,23 +560,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 19 -IS Data_All_Tokens 5705 -IS Ack 0 <-- +IS Data_Owner 16 +IS Data_All_Tokens 5775 +IS Ack 1 IS Transient_GETX 0 <-- -IS Transient_Local_GETX 460 +IS Transient_Local_GETX 481 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 816 +IS Transient_Local_GETS 797 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10015 -IS Persistent_GETS 18534 -IS Own_Lock_or_Unlock 5746 -IS Request_Timeout 3986 +IS Persistent_GETX 10383 +IS Persistent_GETS 19203 +IS Own_Lock_or_Unlock 5794 +IS Request_Timeout 4171 -I_L Load 5716 +I_L Load 5788 I_L Ifetch 0 <-- -I_L Store 3183 +I_L Store 3100 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -588,13 +588,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 1 -I_L Persistent_GETS 2 +I_L Persistent_GETX 3 +I_L Persistent_GETS 0 <-- I_L Own_Lock_or_Unlock 0 <-- -S_L Load 19 +S_L Load 18 S_L Ifetch 0 <-- -S_L Store 9 +S_L Store 11 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -608,7 +608,7 @@ S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 4 +S_L Own_Lock_or_Unlock 3 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -619,15 +619,15 @@ IM_L Data_Owner 0 <-- IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6647 +IM_L Transient_Local_GETX 6467 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12472 +IM_L Transient_Local_GETS 12155 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2218 -IM_L Persistent_GETS 4302 -IM_L Own_Lock_or_Unlock 19065 -IM_L Request_Timeout 1174 +IM_L Persistent_GETX 2008 +IM_L Persistent_GETS 3584 +IM_L Own_Lock_or_Unlock 18946 +IM_L Request_Timeout 1024 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -645,7 +645,7 @@ SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 9 +SM_L Own_Lock_or_Unlock 11 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -657,58 +657,58 @@ IS_L Data_Owner 0 <-- IS_L Data_All_Tokens 0 <-- IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12134 +IS_L Transient_Local_GETX 12246 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22172 +IS_L Transient_Local_GETS 22461 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4204 -IS_L Persistent_GETS 7371 -IS_L Own_Lock_or_Unlock 34263 -IS_L Request_Timeout 2011 +IS_L Persistent_GETX 3608 +IS_L Persistent_GETS 6696 +IS_L Own_Lock_or_Unlock 35372 +IS_L Request_Timeout 1874 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 1 --- - Event Counts - -Load 100000 +Load 97849 Ifetch 0 -Store 53572 +Store 52926 L1_Replacement 0 Data_Shared 0 -Data_Owner 16 -Data_All_Tokens 8907 -Ack 1 -Ack_All_Tokens 6 +Data_Owner 14 +Data_All_Tokens 8895 +Ack 0 +Ack_All_Tokens 5 Transient_GETX 0 -Transient_Local_GETX 22102 +Transient_Local_GETX 21897 Transient_GETS 0 -Transient_Local_GETS 40413 +Transient_Local_GETS 40506 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25285 -Persistent_GETS 46227 -Own_Lock_or_Unlock 71112 -Request_Timeout 9838 -Use_TimeoutStarverX 9 -Use_TimeoutStarverS 21 -Use_TimeoutNoStarvers 8883 +Persistent_GETX 24686 +Persistent_GETS 45801 +Own_Lock_or_Unlock 71875 +Request_Timeout 8949 +Use_TimeoutStarverX 3 +Use_TimeoutStarverS 4 +Use_TimeoutNoStarvers 8893 - Transitions - NP Load 0 <-- @@ -726,9 +726,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 9 +I Load 6 I Ifetch 0 <-- -I Store 2 +I Store 3 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -744,9 +744,9 @@ I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- I Own_Lock_or_Unlock 3 -S Load 2 +S Load 1 S Ifetch 0 <-- -S Store 1 +S Store 2 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- @@ -762,95 +762,95 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 13 +O Load 7 O Ifetch 0 <-- -O Store 6 +O Store 5 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 10 +O Transient_Local_GETX 8 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 +O Own_Lock_or_Unlock 10 -M Load 93 +M Load 157 M Ifetch 0 <-- -M Store 64 +M Store 87 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 6 -M Persistent_GETS 11 -M Own_Lock_or_Unlock 57 +M Persistent_GETX 2 +M Persistent_GETS 14 +M Own_Lock_or_Unlock 73 -MM Load 39210 +MM Load 37407 MM Ifetch 0 <-- -MM Store 21060 +MM Store 20168 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3114 -MM Persistent_GETS 5751 -MM Own_Lock_or_Unlock 8567 +MM Persistent_GETX 3149 +MM Persistent_GETS 5728 +MM Own_Lock_or_Unlock 8660 -M_W Load 10349 +M_W Load 10437 M_W Ifetch 0 <-- -M_W Store 5722 +M_W Store 5625 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1545 +M_W Transient_Local_GETX 1592 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2943 +M_W Transient_Local_GETS 2880 M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 3 -M_W Own_Lock_or_Unlock 28 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 81 +M_W Persistent_GETS 0 <-- +M_W Own_Lock_or_Unlock 3 +M_W Use_TimeoutStarverX 0 <-- +M_W Use_TimeoutStarverS 0 <-- +M_W Use_TimeoutNoStarvers 103 -MM_W Load 44502 +MM_W Load 44078 MM_W Ifetch 0 <-- -MM_W Store 23617 +MM_W Store 23874 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 909 +MM_W Transient_Local_GETX 953 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1723 -MM_W Persistent_GETX 8 -MM_W Persistent_GETS 17 -MM_W Own_Lock_or_Unlock 204 -MM_W Use_TimeoutStarverX 8 -MM_W Use_TimeoutStarverS 20 -MM_W Use_TimeoutNoStarvers 8802 +MM_W Transient_Local_GETS 1733 +MM_W Persistent_GETX 3 +MM_W Persistent_GETS 4 +MM_W Own_Lock_or_Unlock 123 +MM_W Use_TimeoutStarverX 3 +MM_W Use_TimeoutStarverS 4 +MM_W Use_TimeoutNoStarvers 8790 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3094 -IM Ack 1 +IM Data_Owner 1 +IM Data_All_Tokens 3157 +IM Ack 0 <-- IM Transient_GETX 0 <-- -IM Transient_Local_GETX 276 +IM Transient_Local_GETX 272 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 403 +IM Transient_Local_GETS 427 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5339 -IM Persistent_GETS 9988 -IM Own_Lock_or_Unlock 3091 +IM Persistent_GETX 5610 +IM Persistent_GETS 10506 +IM Own_Lock_or_Unlock 3021 IM Request_Timeout 2203 SM Load 0 <-- @@ -859,7 +859,7 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 7 +SM Data_All_Tokens 10 SM Ack 0 <-- SM Transient_GETX 0 <-- SM Transient_Local_GETX 4 @@ -879,15 +879,15 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 6 +OM Ack_All_Tokens 5 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 3 +OM Transient_Local_GETX 2 OM Transient_GETS 0 <-- -OM Transient_Local_GETS 1 +OM Transient_Local_GETS 0 <-- OM Transient_GETS_Last_Token 0 <-- OM Transient_Local_GETS_Last_Token 0 <-- OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- +OM Persistent_GETS 1 OM Own_Lock_or_Unlock 0 <-- OM Request_Timeout 0 <-- @@ -896,23 +896,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 16 -IS Data_All_Tokens 5804 +IS Data_Owner 13 +IS Data_All_Tokens 5728 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 494 +IS Transient_Local_GETX 444 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 774 +IS Transient_Local_GETS 758 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10327 -IS Persistent_GETS 18778 -IS Own_Lock_or_Unlock 5808 -IS Request_Timeout 4283 +IS Persistent_GETX 10291 +IS Persistent_GETS 19195 +IS Own_Lock_or_Unlock 5481 +IS Request_Timeout 3967 -I_L Load 5812 +I_L Load 5737 I_L Ifetch 0 <-- -I_L Store 3088 +I_L Store 3149 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -924,13 +924,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 3 -I_L Persistent_GETS 12 +I_L Persistent_GETX 5 +I_L Persistent_GETS 11 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 10 +S_L Load 19 S_L Ifetch 0 <-- -S_L Store 10 +S_L Store 11 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -944,7 +944,7 @@ S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 2 +S_L Own_Lock_or_Unlock 3 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -952,18 +952,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6495 +IM_L Transient_Local_GETX 6621 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12038 +IM_L Transient_Local_GETS 12284 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2303 -IM_L Persistent_GETS 4177 -IM_L Own_Lock_or_Unlock 18413 -IM_L Request_Timeout 1186 +IM_L Persistent_GETX 2040 +IM_L Persistent_GETS 3733 +IM_L Own_Lock_or_Unlock 19265 +IM_L Request_Timeout 979 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -981,7 +981,7 @@ SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 10 +SM_L Own_Lock_or_Unlock 12 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -990,61 +990,61 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 1 +IS_L Data_All_Tokens 0 <-- IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12365 +IS_L Transient_Local_GETX 12000 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22531 +IS_L Transient_Local_GETS 22424 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4185 -IS_L Persistent_GETS 7489 -IS_L Own_Lock_or_Unlock 34916 -IS_L Request_Timeout 2166 +IS_L Persistent_GETX 3586 +IS_L Persistent_GETS 6608 +IS_L Own_Lock_or_Unlock 35221 +IS_L Request_Timeout 1800 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 2 --- - Event Counts - -Load 97643 +Load 100000 Ifetch 0 -Store 52893 +Store 54082 L1_Replacement 0 Data_Shared 0 Data_Owner 17 -Data_All_Tokens 8906 +Data_All_Tokens 8888 Ack 0 -Ack_All_Tokens 5 +Ack_All_Tokens 9 Transient_GETX 0 -Transient_Local_GETX 22043 +Transient_Local_GETX 21915 Transient_GETS 0 -Transient_Local_GETS 40473 +Transient_Local_GETS 40488 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25456 -Persistent_GETS 46651 -Own_Lock_or_Unlock 70517 -Request_Timeout 9275 -Use_TimeoutStarverX 56 -Use_TimeoutStarverS 71 -Use_TimeoutNoStarvers 8784 +Persistent_GETX 24880 +Persistent_GETS 46033 +Own_Lock_or_Unlock 71449 +Request_Timeout 8898 +Use_TimeoutStarverX 10 +Use_TimeoutStarverS 14 +Use_TimeoutNoStarvers 8872 - Transitions - NP Load 1 @@ -1062,9 +1062,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 10 +I Load 7 I Ifetch 0 <-- -I Store 3 +I Store 4 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -1078,9 +1078,9 @@ I Transient_GETS_Last_Token 0 <-- I Transient_Local_GETS_Last_Token 0 <-- I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 4 +I Own_Lock_or_Unlock 3 -S Load 5 +S Load 8 S Ifetch 0 <-- S Store 1 S L1_Replacement 0 <-- @@ -1089,7 +1089,7 @@ S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 2 +S Transient_Local_GETX 3 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -1098,96 +1098,96 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 15 +O Load 11 O Ifetch 0 <-- -O Store 5 +O Store 9 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 11 +O Transient_Local_GETX 8 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 12 +O Own_Lock_or_Unlock 14 -M Load 132 +M Load 188 M Ifetch 0 <-- -M Store 98 +M Store 102 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 8 -M Persistent_GETS 8 -M Own_Lock_or_Unlock 72 +M Persistent_GETX 9 +M Persistent_GETS 13 +M Own_Lock_or_Unlock 83 -MM Load 37025 +MM Load 39705 MM Ifetch 0 <-- -MM Store 20285 +MM Store 21181 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3092 -MM Persistent_GETS 5676 -MM Own_Lock_or_Unlock 8197 +MM Persistent_GETX 3130 +MM Persistent_GETS 5720 +MM Own_Lock_or_Unlock 8637 -M_W Load 10300 +M_W Load 10480 M_W Ifetch 0 <-- -M_W Store 5629 +M_W Store 5620 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1553 +M_W Transient_Local_GETX 1566 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2883 -M_W Persistent_GETX 1 -M_W Persistent_GETS 4 -M_W Own_Lock_or_Unlock 5 +M_W Transient_Local_GETS 2909 +M_W Persistent_GETX 0 <-- +M_W Persistent_GETS 0 <-- +M_W Own_Lock_or_Unlock 1 M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 114 +M_W Use_TimeoutStarverS 0 <-- +M_W Use_TimeoutNoStarvers 124 -MM_W Load 44391 +MM_W Load 43821 MM_W Ifetch 0 <-- -MM_W Store 23713 +MM_W Store 24025 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 954 +MM_W Transient_Local_GETX 914 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1765 -MM_W Persistent_GETX 53 -MM_W Persistent_GETS 65 -MM_W Own_Lock_or_Unlock 81 -MM_W Use_TimeoutStarverX 56 -MM_W Use_TimeoutStarverS 70 -MM_W Use_TimeoutNoStarvers 8670 +MM_W Transient_Local_GETS 1744 +MM_W Persistent_GETX 10 +MM_W Persistent_GETS 14 +MM_W Own_Lock_or_Unlock 23 +MM_W Use_TimeoutStarverX 10 +MM_W Use_TimeoutStarverS 14 +MM_W Use_TimeoutNoStarvers 8748 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- -IM Data_Owner 1 -IM Data_All_Tokens 3154 +IM Data_Owner 0 <-- +IM Data_All_Tokens 3138 IM Ack 0 <-- IM Transient_GETX 0 <-- -IM Transient_Local_GETX 224 +IM Transient_Local_GETX 270 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 423 +IM Transient_Local_GETS 428 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5527 -IM Persistent_GETS 10268 -IM Own_Lock_or_Unlock 3022 -IM Request_Timeout 2254 +IM Persistent_GETX 5591 +IM Persistent_GETS 10381 +IM Own_Lock_or_Unlock 2975 +IM Request_Timeout 2196 SM Load 0 <-- SM Ifetch 0 <-- @@ -1198,7 +1198,7 @@ SM Data_Owner 0 <-- SM Data_All_Tokens 6 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 1 +SM Transient_Local_GETX 4 SM Transient_GETS 0 <-- SM Transient_Local_GETS 0 <-- SM Transient_GETS_Last_Token 0 <-- @@ -1215,14 +1215,14 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 5 +OM Ack_All_Tokens 9 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 5 +OM Transient_Local_GETX 8 OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- +OM Transient_Local_GETS 1 OM Transient_GETS_Last_Token 0 <-- OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 1 +OM Persistent_GETX 0 <-- OM Persistent_GETS 0 <-- OM Own_Lock_or_Unlock 0 <-- OM Request_Timeout 0 <-- @@ -1232,23 +1232,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 16 -IS Data_All_Tokens 5742 +IS Data_Owner 17 +IS Data_All_Tokens 5744 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 500 +IS Transient_Local_GETX 441 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 764 +IS Transient_Local_GETS 766 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10135 -IS Persistent_GETS 18799 -IS Own_Lock_or_Unlock 5489 -IS Request_Timeout 3965 +IS Persistent_GETX 10221 +IS Persistent_GETS 19165 +IS Own_Lock_or_Unlock 5460 +IS Request_Timeout 3916 -I_L Load 5750 +I_L Load 5753 I_L Ifetch 0 <-- -I_L Store 3152 +I_L Store 3130 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -1260,13 +1260,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 123 -I_L Persistent_GETS 171 +I_L Persistent_GETX 31 +I_L Persistent_GETS 63 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 14 +S_L Load 26 S_L Ifetch 0 <-- -S_L Store 6 +S_L Store 9 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -1279,8 +1279,8 @@ S_L Transient_Local_GETS 0 <-- S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 3 +S_L Persistent_GETS 0 <-- +S_L Own_Lock_or_Unlock 4 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -1288,18 +1288,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 2 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6723 +IM_L Transient_Local_GETX 6599 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12190 +IM_L Transient_Local_GETS 12210 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2287 -IM_L Persistent_GETS 4214 -IM_L Own_Lock_or_Unlock 18945 -IM_L Request_Timeout 1051 +IM_L Persistent_GETX 2151 +IM_L Persistent_GETS 3738 +IM_L Own_Lock_or_Unlock 19101 +IM_L Request_Timeout 941 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -1317,7 +1317,7 @@ SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 6 +SM_L Own_Lock_or_Unlock 9 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -1326,66 +1326,66 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 +IS_L Data_All_Tokens 0 <-- IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12070 +IS_L Transient_Local_GETX 12102 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22448 +IS_L Transient_Local_GETS 22430 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4229 -IS_L Persistent_GETS 7442 -IS_L Own_Lock_or_Unlock 34681 -IS_L Request_Timeout 2005 +IS_L Persistent_GETX 3737 +IS_L Persistent_GETS 6939 +IS_L Own_Lock_or_Unlock 35139 +IS_L Request_Timeout 1845 -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 3 --- - Event Counts - -Load 97533 +Load 97548 Ifetch 0 -Store 52364 +Store 52845 L1_Replacement 0 Data_Shared 0 -Data_Owner 13 -Data_All_Tokens 8914 +Data_Owner 15 +Data_All_Tokens 8890 Ack 0 -Ack_All_Tokens 3 +Ack_All_Tokens 9 Transient_GETX 0 -Transient_Local_GETX 22082 +Transient_Local_GETX 21893 Transient_GETS 0 -Transient_Local_GETS 40431 +Transient_Local_GETS 40509 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25737 -Persistent_GETS 47104 -Own_Lock_or_Unlock 69783 -Request_Timeout 9632 -Use_TimeoutStarverX 49 -Use_TimeoutStarverS 101 -Use_TimeoutNoStarvers 8767 +Persistent_GETX 24936 +Persistent_GETS 46314 +Own_Lock_or_Unlock 71112 +Request_Timeout 9055 +Use_TimeoutStarverX 18 +Use_TimeoutStarverS 47 +Use_TimeoutNoStarvers 8834 - Transitions - -NP Load 2 +NP Load 1 NP Ifetch 0 <-- -NP Store 0 <-- +NP Store 1 NP Data_Shared 0 <-- NP Data_Owner 0 <-- NP Data_All_Tokens 0 <-- @@ -1398,9 +1398,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 7 +I Load 8 I Ifetch 0 <-- -I Store 5 +I Store 2 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -1414,18 +1414,18 @@ I Transient_GETS_Last_Token 0 <-- I Transient_Local_GETS_Last_Token 0 <-- I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 5 +I Own_Lock_or_Unlock 4 S Load 7 S Ifetch 0 <-- -S Store 5 +S Store 1 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 2 +S Transient_Local_GETX 4 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -1434,77 +1434,77 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 9 +O Load 21 O Ifetch 0 <-- -O Store 3 +O Store 9 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 10 +O Transient_Local_GETX 6 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 8 +O Own_Lock_or_Unlock 11 -M Load 118 +M Load 149 M Ifetch 0 <-- -M Store 59 +M Store 71 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 12 -M Persistent_GETS 18 -M Own_Lock_or_Unlock 64 +M Persistent_GETX 7 +M Persistent_GETS 17 +M Own_Lock_or_Unlock 70 -MM Load 36793 +MM Load 37142 MM Ifetch 0 <-- -MM Store 19758 +MM Store 20055 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3077 -MM Persistent_GETS 5660 -MM Own_Lock_or_Unlock 8127 +MM Persistent_GETX 3053 +MM Persistent_GETS 5757 +MM Own_Lock_or_Unlock 8418 -M_W Load 10555 +M_W Load 10116 M_W Ifetch 0 <-- -M_W Store 5696 +M_W Store 5630 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1567 +M_W Transient_Local_GETX 1537 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2900 -M_W Persistent_GETX 3 -M_W Persistent_GETS 5 -M_W Own_Lock_or_Unlock 9 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 89 +M_W Transient_Local_GETS 2910 +M_W Persistent_GETX 0 <-- +M_W Persistent_GETS 0 <-- +M_W Own_Lock_or_Unlock 3 +M_W Use_TimeoutStarverX 0 <-- +M_W Use_TimeoutStarverS 0 <-- +M_W Use_TimeoutNoStarvers 95 -MM_W Load 44219 +MM_W Load 44353 MM_W Ifetch 0 <-- -MM_W Store 23722 +MM_W Store 23913 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 940 +MM_W Transient_Local_GETX 966 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1718 -MM_W Persistent_GETX 45 -MM_W Persistent_GETS 91 -MM_W Own_Lock_or_Unlock 175 -MM_W Use_TimeoutStarverX 48 -MM_W Use_TimeoutStarverS 99 -MM_W Use_TimeoutNoStarvers 8678 +MM_W Transient_Local_GETS 1750 +MM_W Persistent_GETX 18 +MM_W Persistent_GETS 46 +MM_W Own_Lock_or_Unlock 99 +MM_W Use_TimeoutStarverX 18 +MM_W Use_TimeoutStarverS 47 +MM_W Use_TimeoutNoStarvers 8739 IM Load 0 <-- IM Ifetch 0 <-- @@ -1512,18 +1512,18 @@ IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- IM Data_Owner 0 <-- -IM Data_All_Tokens 3110 +IM Data_All_Tokens 3157 IM Ack 0 <-- IM Transient_GETX 0 <-- -IM Transient_Local_GETX 239 +IM Transient_Local_GETX 240 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 407 +IM Transient_Local_GETS 417 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5351 -IM Persistent_GETS 10228 -IM Own_Lock_or_Unlock 2723 -IM Request_Timeout 2247 +IM Persistent_GETX 5599 +IM Persistent_GETS 10582 +IM Own_Lock_or_Unlock 2850 +IM Request_Timeout 2215 SM Load 0 <-- SM Ifetch 0 <-- @@ -1531,12 +1531,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 14 +SM Data_All_Tokens 8 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 4 +SM Transient_Local_GETX 5 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 +SM Transient_Local_GETS 0 <-- SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -1551,9 +1551,9 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 3 +OM Ack_All_Tokens 9 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 1 +OM Transient_Local_GETX 5 OM Transient_GETS 0 <-- OM Transient_Local_GETS 0 <-- OM Transient_GETS_Last_Token 0 <-- @@ -1568,23 +1568,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 13 -IS Data_All_Tokens 5784 +IS Data_Owner 15 +IS Data_All_Tokens 5724 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 483 +IS Transient_Local_GETX 467 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 809 +IS Transient_Local_GETS 762 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10327 -IS Persistent_GETS 18763 -IS Own_Lock_or_Unlock 5094 -IS Request_Timeout 4257 +IS Persistent_GETX 10393 +IS Persistent_GETS 18988 +IS Own_Lock_or_Unlock 5198 +IS Request_Timeout 4113 -I_L Load 5794 +I_L Load 5731 I_L Ifetch 0 <-- -I_L Store 3103 +I_L Store 3151 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -1596,13 +1596,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 107 -I_L Persistent_GETS 171 +I_L Persistent_GETX 58 +I_L Persistent_GETS 108 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 29 +S_L Load 20 S_L Ifetch 0 <-- -S_L Store 13 +S_L Store 12 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -1615,8 +1615,8 @@ S_L Transient_Local_GETS 0 <-- S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 7 +S_L Persistent_GETS 1 +S_L Own_Lock_or_Unlock 5 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -1624,18 +1624,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 2 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6465 +IM_L Transient_Local_GETX 6699 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12190 +IM_L Transient_Local_GETS 12233 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2323 -IM_L Persistent_GETS 4335 -IM_L Own_Lock_or_Unlock 18680 -IM_L Request_Timeout 1090 +IM_L Persistent_GETX 2031 +IM_L Persistent_GETS 3864 +IM_L Own_Lock_or_Unlock 19331 +IM_L Request_Timeout 1000 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -1652,8 +1652,8 @@ SM_L Transient_Local_GETS 0 <-- SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 1 -SM_L Own_Lock_or_Unlock 13 +SM_L Persistent_GETS 2 +SM_L Own_Lock_or_Unlock 12 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -1662,66 +1662,66 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 4 +IS_L Data_All_Tokens 1 IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12371 +IS_L Transient_Local_GETX 11964 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22406 +IS_L Transient_Local_GETS 22437 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4492 -IS_L Persistent_GETS 7828 -IS_L Own_Lock_or_Unlock 34878 -IS_L Request_Timeout 2038 +IS_L Persistent_GETX 3777 +IS_L Persistent_GETS 6949 +IS_L Own_Lock_or_Unlock 35111 +IS_L Request_Timeout 1727 -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 4 --- - Event Counts - -Load 98571 +Load 98336 Ifetch 0 -Store 53174 +Store 52558 L1_Replacement 0 Data_Shared 0 -Data_Owner 15 -Data_All_Tokens 8907 -Ack 1 -Ack_All_Tokens 9 +Data_Owner 22 +Data_All_Tokens 8882 +Ack 2 +Ack_All_Tokens 10 Transient_GETX 0 -Transient_Local_GETX 22035 +Transient_Local_GETX 21927 Transient_GETS 0 -Transient_Local_GETS 40477 +Transient_Local_GETS 40476 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25723 -Persistent_GETS 47221 -Own_Lock_or_Unlock 69680 -Request_Timeout 9073 -Use_TimeoutStarverX 45 -Use_TimeoutStarverS 64 -Use_TimeoutNoStarvers 8807 +Persistent_GETX 24899 +Persistent_GETS 46131 +Own_Lock_or_Unlock 71332 +Request_Timeout 8962 +Use_TimeoutStarverX 11 +Use_TimeoutStarverS 17 +Use_TimeoutNoStarvers 8864 - Transitions - -NP Load 0 <-- +NP Load 2 NP Ifetch 0 <-- -NP Store 2 +NP Store 0 <-- NP Data_Shared 0 <-- NP Data_Owner 0 <-- NP Data_All_Tokens 0 <-- @@ -1734,9 +1734,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 5 +I Load 10 I Ifetch 0 <-- -I Store 2 +I Store 4 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -1752,16 +1752,16 @@ I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- I Own_Lock_or_Unlock 2 -S Load 5 +S Load 2 S Ifetch 0 <-- -S Store 1 +S Store 2 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 1 +S Transient_Local_GETX 3 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -1770,96 +1770,96 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 12 +O Load 20 O Ifetch 0 <-- -O Store 9 +O Store 10 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 6 +O Transient_Local_GETX 11 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 +O Own_Lock_or_Unlock 19 -M Load 162 +M Load 166 M Ifetch 0 <-- -M Store 90 +M Store 86 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- M Persistent_GETX 10 -M Persistent_GETS 15 -M Own_Lock_or_Unlock 81 +M Persistent_GETS 16 +M Own_Lock_or_Unlock 83 -MM Load 37823 +MM Load 37712 MM Ifetch 0 <-- -MM Store 20386 +MM Store 19992 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3131 -MM Persistent_GETS 5651 -MM Own_Lock_or_Unlock 8286 +MM Persistent_GETX 3090 +MM Persistent_GETS 5748 +MM Own_Lock_or_Unlock 8387 -M_W Load 10724 +M_W Load 10442 M_W Ifetch 0 <-- -M_W Store 5626 +M_W Store 5639 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1492 +M_W Transient_Local_GETX 1598 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2942 +M_W Transient_Local_GETS 2819 M_W Persistent_GETX 1 -M_W Persistent_GETS 2 -M_W Own_Lock_or_Unlock 5 +M_W Persistent_GETS 0 <-- +M_W Own_Lock_or_Unlock 3 M_W Use_TimeoutStarverX 0 <-- M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 115 +M_W Use_TimeoutNoStarvers 112 -MM_W Load 44076 +MM_W Load 44196 MM_W Ifetch 0 <-- -MM_W Store 23896 +MM_W Store 23699 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 938 +MM_W Transient_Local_GETX 902 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1714 -MM_W Persistent_GETX 42 -MM_W Persistent_GETS 58 -MM_W Own_Lock_or_Unlock 118 -MM_W Use_TimeoutStarverX 45 -MM_W Use_TimeoutStarverS 64 -MM_W Use_TimeoutNoStarvers 8692 +MM_W Transient_Local_GETS 1779 +MM_W Persistent_GETX 9 +MM_W Persistent_GETS 17 +MM_W Own_Lock_or_Unlock 95 +MM_W Use_TimeoutStarverX 11 +MM_W Use_TimeoutStarverS 17 +MM_W Use_TimeoutNoStarvers 8752 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3153 +IM Data_Owner 1 +IM Data_All_Tokens 3126 IM Ack 1 IM Transient_GETX 0 <-- -IM Transient_Local_GETX 249 +IM Transient_Local_GETX 229 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 476 +IM Transient_Local_GETS 407 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5499 -IM Persistent_GETS 10272 -IM Own_Lock_or_Unlock 2790 -IM Request_Timeout 2276 +IM Persistent_GETX 5549 +IM Persistent_GETS 10517 +IM Own_Lock_or_Unlock 2855 +IM Request_Timeout 2152 SM Load 0 <-- SM Ifetch 0 <-- @@ -1867,12 +1867,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 9 +SM Data_All_Tokens 5 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 5 +SM Transient_Local_GETX 9 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- +SM Transient_Local_GETS 1 SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -1887,15 +1887,15 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 9 +OM Ack_All_Tokens 10 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 3 +OM Transient_Local_GETX 7 OM Transient_GETS 0 <-- OM Transient_Local_GETS 0 <-- OM Transient_GETS_Last_Token 0 <-- OM Transient_Local_GETS_Last_Token 0 <-- OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- +OM Persistent_GETS 1 OM Own_Lock_or_Unlock 0 <-- OM Request_Timeout 0 <-- @@ -1904,23 +1904,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 15 -IS Data_All_Tokens 5739 -IS Ack 0 <-- +IS Data_Owner 21 +IS Data_All_Tokens 5750 +IS Ack 1 IS Transient_GETX 0 <-- -IS Transient_Local_GETX 480 +IS Transient_Local_GETX 491 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 773 +IS Transient_Local_GETS 805 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10010 -IS Persistent_GETS 18635 -IS Own_Lock_or_Unlock 5061 -IS Request_Timeout 3939 +IS Persistent_GETX 10484 +IS Persistent_GETS 19149 +IS Own_Lock_or_Unlock 5299 +IS Request_Timeout 4040 -I_L Load 5752 +I_L Load 5761 I_L Ifetch 0 <-- -I_L Store 3149 +I_L Store 3115 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -1932,13 +1932,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 91 -I_L Persistent_GETS 129 +I_L Persistent_GETX 80 +I_L Persistent_GETS 123 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 12 +S_L Load 25 S_L Ifetch 0 <-- -S_L Store 13 +S_L Store 11 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -1952,7 +1952,7 @@ S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 2 +S_L Own_Lock_or_Unlock 5 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -1960,18 +1960,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 4 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6730 +IM_L Transient_Local_GETX 6491 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12189 +IM_L Transient_Local_GETS 12257 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2467 -IM_L Persistent_GETS 4316 -IM_L Own_Lock_or_Unlock 18915 -IM_L Request_Timeout 976 +IM_L Persistent_GETX 1961 +IM_L Persistent_GETS 3726 +IM_L Own_Lock_or_Unlock 19180 +IM_L Request_Timeout 988 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -1988,8 +1988,8 @@ SM_L Transient_Local_GETS 0 <-- SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 1 -SM_L Own_Lock_or_Unlock 13 +SM_L Persistent_GETS 0 <-- +SM_L Own_Lock_or_Unlock 12 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -1998,61 +1998,61 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 +IS_L Data_All_Tokens 1 IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12131 +IS_L Transient_Local_GETX 12186 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22383 +IS_L Transient_Local_GETS 22408 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4472 -IS_L Persistent_GETS 8141 -IS_L Own_Lock_or_Unlock 34394 -IS_L Request_Timeout 1882 +IS_L Persistent_GETX 3715 +IS_L Persistent_GETS 6833 +IS_L Own_Lock_or_Unlock 35392 +IS_L Request_Timeout 1782 -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 5 --- - Event Counts - -Load 98263 +Load 97596 Ifetch 0 -Store 52643 +Store 52680 L1_Replacement 0 Data_Shared 0 -Data_Owner 14 -Data_All_Tokens 8907 +Data_Owner 8 +Data_All_Tokens 8899 Ack 0 -Ack_All_Tokens 8 +Ack_All_Tokens 2 Transient_GETX 0 -Transient_Local_GETX 22057 +Transient_Local_GETX 22013 Transient_GETS 0 -Transient_Local_GETS 40457 +Transient_Local_GETS 40394 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25924 -Persistent_GETS 47474 -Own_Lock_or_Unlock 69226 -Request_Timeout 9210 -Use_TimeoutStarverX 95 -Use_TimeoutStarverS 180 -Use_TimeoutNoStarvers 8640 +Persistent_GETX 25459 +Persistent_GETS 46885 +Own_Lock_or_Unlock 70018 +Request_Timeout 9144 +Use_TimeoutStarverX 41 +Use_TimeoutStarverS 78 +Use_TimeoutNoStarvers 8782 - Transitions - NP Load 1 @@ -2070,9 +2070,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 1 +I Load 5 I Ifetch 0 <-- -I Store 7 +I Store 1 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -2086,18 +2086,18 @@ I Transient_GETS_Last_Token 0 <-- I Transient_Local_GETS_Last_Token 0 <-- I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 +I Own_Lock_or_Unlock 3 -S Load 6 +S Load 0 <-- S Ifetch 0 <-- -S Store 2 +S Store 0 <-- S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 2 +S Transient_Local_GETX 0 <-- S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -2106,9 +2106,9 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 14 +O Load 2 O Ifetch 0 <-- -O Store 8 +O Store 2 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- @@ -2122,9 +2122,9 @@ O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 12 +O Own_Lock_or_Unlock 5 -M Load 146 +M Load 143 M Ifetch 0 <-- M Store 82 M L1_Replacement 0 <-- @@ -2133,50 +2133,50 @@ M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- M Persistent_GETX 10 -M Persistent_GETS 14 -M Own_Lock_or_Unlock 78 +M Persistent_GETS 12 +M Own_Lock_or_Unlock 75 -MM Load 37545 +MM Load 37054 MM Ifetch 0 <-- -MM Store 19800 +MM Store 20002 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 2939 -MM Persistent_GETS 5677 -MM Own_Lock_or_Unlock 8010 +MM Persistent_GETX 3069 +MM Persistent_GETS 5691 +MM Own_Lock_or_Unlock 8228 -M_W Load 10319 +M_W Load 10582 M_W Ifetch 0 <-- -M_W Store 5652 +M_W Store 5741 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1615 +M_W Transient_Local_GETX 1563 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2853 -M_W Persistent_GETX 6 -M_W Persistent_GETS 10 -M_W Own_Lock_or_Unlock 3 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 106 +M_W Transient_Local_GETS 2981 +M_W Persistent_GETX 1 +M_W Persistent_GETS 1 +M_W Own_Lock_or_Unlock 2 +M_W Use_TimeoutStarverX 0 <-- +M_W Use_TimeoutStarverS 1 +M_W Use_TimeoutNoStarvers 104 -MM_W Load 44434 +MM_W Load 43952 MM_W Ifetch 0 <-- -MM_W Store 23955 +MM_W Store 23799 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 922 +MM_W Transient_Local_GETX 896 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1731 -MM_W Persistent_GETX 89 -MM_W Persistent_GETS 167 -MM_W Own_Lock_or_Unlock 63 -MM_W Use_TimeoutStarverX 94 -MM_W Use_TimeoutStarverS 178 -MM_W Use_TimeoutNoStarvers 8534 +MM_W Transient_Local_GETS 1686 +MM_W Persistent_GETX 40 +MM_W Persistent_GETS 76 +MM_W Own_Lock_or_Unlock 48 +MM_W Use_TimeoutStarverX 41 +MM_W Use_TimeoutStarverS 77 +MM_W Use_TimeoutNoStarvers 8678 IM Load 0 <-- IM Ifetch 0 <-- @@ -2184,18 +2184,18 @@ IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- IM Data_Owner 0 <-- -IM Data_All_Tokens 3137 +IM Data_All_Tokens 3043 IM Ack 0 <-- IM Transient_GETX 0 <-- -IM Transient_Local_GETX 242 +IM Transient_Local_GETX 264 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 440 +IM Transient_Local_GETS 412 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5536 -IM Persistent_GETS 10252 -IM Own_Lock_or_Unlock 2638 -IM Request_Timeout 2133 +IM Persistent_GETX 5392 +IM Persistent_GETS 10154 +IM Own_Lock_or_Unlock 2439 +IM Request_Timeout 2167 SM Load 0 <-- SM Ifetch 0 <-- @@ -2203,12 +2203,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 8 +SM Data_All_Tokens 10 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 +SM Transient_Local_GETX 3 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 +SM Transient_Local_GETS 0 <-- SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -2223,9 +2223,9 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 8 +OM Ack_All_Tokens 2 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 6 +OM Transient_Local_GETX 2 OM Transient_GETS 0 <-- OM Transient_Local_GETS 0 <-- OM Transient_GETS_Last_Token 0 <-- @@ -2240,23 +2240,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 14 -IS Data_All_Tokens 5759 +IS Data_Owner 8 +IS Data_All_Tokens 5845 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 469 +IS Transient_Local_GETX 462 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 783 +IS Transient_Local_GETS 808 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10207 -IS Persistent_GETS 18677 -IS Own_Lock_or_Unlock 4838 -IS Request_Timeout 3962 +IS Persistent_GETX 10637 +IS Persistent_GETS 19370 +IS Own_Lock_or_Unlock 4767 +IS Request_Timeout 4200 -I_L Load 5775 +I_L Load 5849 I_L Ifetch 0 <-- -I_L Store 3124 +I_L Store 3039 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -2268,13 +2268,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 124 -I_L Persistent_GETS 249 +I_L Persistent_GETX 104 +I_L Persistent_GETS 214 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 22 +S_L Load 8 S_L Ifetch 0 <-- -S_L Store 12 +S_L Store 13 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -2287,8 +2287,8 @@ S_L Transient_Local_GETS 0 <-- S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 4 +S_L Persistent_GETS 2 +S_L Own_Lock_or_Unlock 0 <-- IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -2296,18 +2296,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6599 +IM_L Transient_Local_GETX 6400 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12205 +IM_L Transient_Local_GETS 11834 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2385 -IM_L Persistent_GETS 4323 -IM_L Own_Lock_or_Unlock 18911 -IM_L Request_Timeout 1095 +IM_L Persistent_GETX 2161 +IM_L Persistent_GETS 3947 +IM_L Own_Lock_or_Unlock 18584 +IM_L Request_Timeout 934 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -2324,8 +2324,8 @@ SM_L Transient_Local_GETS 0 <-- SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 2 -SM_L Own_Lock_or_Unlock 12 +SM_L Persistent_GETS 0 <-- +SM_L Own_Lock_or_Unlock 13 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -2334,66 +2334,66 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 +IS_L Data_All_Tokens 1 IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12190 +IS_L Transient_Local_GETX 12417 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22444 +IS_L Transient_Local_GETS 22673 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4628 -IS_L Persistent_GETS 8099 -IS_L Own_Lock_or_Unlock 34655 -IS_L Request_Timeout 2020 +IS_L Persistent_GETX 4045 +IS_L Persistent_GETS 7418 +IS_L Own_Lock_or_Unlock 35854 +IS_L Request_Timeout 1843 -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 6 --- - Event Counts - -Load 98465 +Load 97890 Ifetch 0 -Store 52806 +Store 52462 L1_Replacement 0 Data_Shared 0 -Data_Owner 12 -Data_All_Tokens 8905 -Ack 0 -Ack_All_Tokens 4 +Data_Owner 14 +Data_All_Tokens 8893 +Ack 2 +Ack_All_Tokens 7 Transient_GETX 0 -Transient_Local_GETX 22067 +Transient_Local_GETX 21982 Transient_GETS 0 -Transient_Local_GETS 40455 +Transient_Local_GETS 40420 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 26105 -Persistent_GETS 47891 -Own_Lock_or_Unlock 68628 -Request_Timeout 9116 -Use_TimeoutStarverX 83 -Use_TimeoutStarverS 130 -Use_TimeoutNoStarvers 8696 +Persistent_GETX 25433 +Persistent_GETS 46779 +Own_Lock_or_Unlock 70150 +Request_Timeout 8995 +Use_TimeoutStarverX 59 +Use_TimeoutStarverS 91 +Use_TimeoutNoStarvers 8750 - Transitions - -NP Load 2 +NP Load 0 <-- NP Ifetch 0 <-- -NP Store 0 <-- +NP Store 2 NP Data_Shared 0 <-- NP Data_Owner 0 <-- NP Data_All_Tokens 0 <-- @@ -2406,9 +2406,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 8 +I Load 5 I Ifetch 0 <-- -I Store 4 +I Store 3 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -2424,16 +2424,16 @@ I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- I Own_Lock_or_Unlock 2 -S Load 4 +S Load 1 S Ifetch 0 <-- -S Store 4 +S Store 3 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 4 +S Transient_Local_GETX 1 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -2442,77 +2442,77 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 17 +O Load 5 O Ifetch 0 <-- -O Store 4 +O Store 7 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- -O Ack 0 <-- +O Ack 1 O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 8 +O Transient_Local_GETX 7 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- O Transient_Local_GETS_Last_Token 0 <-- O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 10 +O Own_Lock_or_Unlock 12 -M Load 180 +M Load 175 M Ifetch 0 <-- -M Store 84 +M Store 82 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 9 -M Persistent_GETS 10 -M Own_Lock_or_Unlock 73 +M Persistent_GETX 5 +M Persistent_GETS 20 +M Own_Lock_or_Unlock 77 -MM Load 37625 +MM Load 37311 MM Ifetch 0 <-- -MM Store 20185 +MM Store 19913 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3113 -MM Persistent_GETS 5564 -MM Own_Lock_or_Unlock 8005 +MM Persistent_GETX 3037 +MM Persistent_GETS 5688 +MM Own_Lock_or_Unlock 8062 -M_W Load 10787 +M_W Load 10708 M_W Ifetch 0 <-- -M_W Store 5661 +M_W Store 5706 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1617 +M_W Transient_Local_GETX 1629 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2872 -M_W Persistent_GETX 2 -M_W Persistent_GETS 6 +M_W Transient_Local_GETS 2878 +M_W Persistent_GETX 4 +M_W Persistent_GETS 2 M_W Own_Lock_or_Unlock 0 <-- M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 103 +M_W Use_TimeoutStarverS 1 +M_W Use_TimeoutNoStarvers 107 -MM_W Load 44046 +MM_W Load 43836 MM_W Ifetch 0 <-- -MM_W Store 23732 +MM_W Store 23674 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 944 +MM_W Transient_Local_GETX 974 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1688 -MM_W Persistent_GETX 81 -MM_W Persistent_GETS 120 -MM_W Own_Lock_or_Unlock 32 -MM_W Use_TimeoutStarverX 83 -MM_W Use_TimeoutStarverS 128 -MM_W Use_TimeoutNoStarvers 8593 +MM_W Transient_Local_GETS 1682 +MM_W Persistent_GETX 55 +MM_W Persistent_GETS 89 +MM_W Own_Lock_or_Unlock 11 +MM_W Use_TimeoutStarverX 59 +MM_W Use_TimeoutStarverS 90 +MM_W Use_TimeoutNoStarvers 8643 IM Load 0 <-- IM Ifetch 0 <-- @@ -2520,18 +2520,18 @@ IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- IM Data_Owner 0 <-- -IM Data_All_Tokens 3136 -IM Ack 0 <-- +IM Data_All_Tokens 3069 +IM Ack 1 IM Transient_GETX 0 <-- -IM Transient_Local_GETX 272 +IM Transient_Local_GETX 245 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 429 +IM Transient_Local_GETS 389 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5413 -IM Persistent_GETS 10166 -IM Own_Lock_or_Unlock 2512 -IM Request_Timeout 2230 +IM Persistent_GETX 5601 +IM Persistent_GETS 10146 +IM Own_Lock_or_Unlock 2518 +IM Request_Timeout 2145 SM Load 0 <-- SM Ifetch 0 <-- @@ -2539,12 +2539,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 2 +SM Data_All_Tokens 10 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 +SM Transient_Local_GETX 10 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- +SM Transient_Local_GETS 1 SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -2559,9 +2559,9 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 4 +OM Ack_All_Tokens 7 OM Transient_GETX 0 <-- -OM Transient_Local_GETX 1 +OM Transient_Local_GETX 3 OM Transient_GETS 0 <-- OM Transient_Local_GETS 0 <-- OM Transient_GETS_Last_Token 0 <-- @@ -2576,23 +2576,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 12 -IS Data_All_Tokens 5763 +IS Data_Owner 14 +IS Data_All_Tokens 5814 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 453 +IS Transient_Local_GETX 492 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 781 +IS Transient_Local_GETS 759 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10124 -IS Persistent_GETS 18788 -IS Own_Lock_or_Unlock 4600 -IS Request_Timeout 4029 +IS Persistent_GETX 10459 +IS Persistent_GETS 19532 +IS Own_Lock_or_Unlock 4832 +IS Request_Timeout 4014 -I_L Load 5769 +I_L Load 5824 I_L Ifetch 0 <-- -I_L Store 3128 +I_L Store 3055 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -2604,13 +2604,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 155 -I_L Persistent_GETS 290 +I_L Persistent_GETX 151 +I_L Persistent_GETS 242 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 27 +S_L Load 25 S_L Ifetch 0 <-- -S_L Store 4 +S_L Store 17 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -2623,8 +2623,8 @@ S_L Transient_Local_GETS 0 <-- S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 6 -S_L Own_Lock_or_Unlock 8 +S_L Persistent_GETS 2 +S_L Own_Lock_or_Unlock 4 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -2632,18 +2632,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 +IM_L Data_All_Tokens 0 <-- IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6488 +IM_L Transient_Local_GETX 6386 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12321 +IM_L Transient_Local_GETS 12013 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2578 -IM_L Persistent_GETS 4664 -IM_L Own_Lock_or_Unlock 18705 -IM_L Request_Timeout 985 +IM_L Persistent_GETX 2174 +IM_L Persistent_GETS 3820 +IM_L Own_Lock_or_Unlock 18801 +IM_L Request_Timeout 978 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -2660,8 +2660,8 @@ SM_L Transient_Local_GETS 0 <-- SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 4 +SM_L Persistent_GETS 3 +SM_L Own_Lock_or_Unlock 17 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -2670,61 +2670,61 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 3 +IS_L Data_All_Tokens 0 <-- IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12274 +IS_L Transient_Local_GETX 12235 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22364 +IS_L Transient_Local_GETS 22698 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4630 -IS_L Persistent_GETS 8277 -IS_L Own_Lock_or_Unlock 34677 -IS_L Request_Timeout 1872 +IS_L Persistent_GETX 3947 +IS_L Persistent_GETS 7235 +IS_L Own_Lock_or_Unlock 35814 +IS_L Request_Timeout 1858 -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- L1Cache 7 --- - Event Counts - -Load 97834 +Load 97464 Ifetch 0 -Store 52922 +Store 51982 L1_Replacement 0 Data_Shared 0 -Data_Owner 12 -Data_All_Tokens 8914 -Ack 0 -Ack_All_Tokens 7 +Data_Owner 21 +Data_All_Tokens 8881 +Ack 1 +Ack_All_Tokens 8 Transient_GETX 0 -Transient_Local_GETX 22087 +Transient_Local_GETX 21914 Transient_GETS 0 -Transient_Local_GETS 40424 +Transient_Local_GETS 40494 Transient_GETS_Last_Token 0 Transient_Local_GETS_Last_Token 0 -Persistent_GETX 26278 -Persistent_GETS 48035 -Own_Lock_or_Unlock 68312 -Request_Timeout 9299 -Use_TimeoutStarverX 114 -Use_TimeoutStarverS 189 -Use_TimeoutNoStarvers 8618 +Persistent_GETX 25492 +Persistent_GETS 47155 +Own_Lock_or_Unlock 69715 +Request_Timeout 9514 +Use_TimeoutStarverX 78 +Use_TimeoutStarverS 164 +Use_TimeoutNoStarvers 8647 - Transitions - NP Load 1 @@ -2742,9 +2742,9 @@ NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- NP Own_Lock_or_Unlock 0 <-- -I Load 6 +I Load 8 I Ifetch 0 <-- -I Store 1 +I Store 5 I L1_Replacement 0 <-- I Data_Shared 0 <-- I Data_Owner 0 <-- @@ -2758,18 +2758,18 @@ I Transient_GETS_Last_Token 0 <-- I Transient_Local_GETS_Last_Token 0 <-- I Persistent_GETX 0 <-- I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 1 +I Own_Lock_or_Unlock 9 -S Load 6 +S Load 3 S Ifetch 0 <-- -S Store 4 +S Store 2 S L1_Replacement 0 <-- S Data_Shared 0 <-- S Data_Owner 0 <-- S Data_All_Tokens 0 <-- S Ack 0 <-- S Transient_GETX 0 <-- -S Transient_Local_GETX 2 +S Transient_Local_GETX 1 S Transient_GETS 0 <-- S Transient_Local_GETS 0 <-- S Transient_GETS_Last_Token 0 <-- @@ -2778,16 +2778,16 @@ S Persistent_GETX 0 <-- S Persistent_GETS 0 <-- S Own_Lock_or_Unlock 0 <-- -O Load 8 +O Load 11 O Ifetch 0 <-- -O Store 7 +O Store 8 O L1_Replacement 0 <-- O Data_Shared 0 <-- O Data_All_Tokens 0 <-- O Ack 0 <-- O Ack_All_Tokens 0 <-- O Transient_GETX 0 <-- -O Transient_Local_GETX 5 +O Transient_Local_GETX 12 O Transient_GETS 0 <-- O Transient_Local_GETS 0 <-- O Transient_GETS_Last_Token 0 <-- @@ -2796,78 +2796,78 @@ O Persistent_GETX 0 <-- O Persistent_GETS 0 <-- O Own_Lock_or_Unlock 11 -M Load 162 +M Load 148 M Ifetch 0 <-- -M Store 84 +M Store 79 M L1_Replacement 0 <-- M Transient_GETX 0 <-- M Transient_Local_GETX 0 <-- M Transient_GETS 0 <-- M Transient_Local_GETS 0 <-- -M Persistent_GETX 4 -M Persistent_GETS 19 -M Own_Lock_or_Unlock 67 +M Persistent_GETX 8 +M Persistent_GETS 13 +M Own_Lock_or_Unlock 65 -MM Load 36988 +MM Load 36904 MM Ifetch 0 <-- -MM Store 20238 +MM Store 19338 MM L1_Replacement 0 <-- MM Transient_GETX 0 <-- MM Transient_Local_GETX 0 <-- MM Transient_GETS 0 <-- MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 2995 -MM Persistent_GETS 5599 -MM Own_Lock_or_Unlock 7907 +MM Persistent_GETX 3047 +MM Persistent_GETS 5579 +MM Own_Lock_or_Unlock 7946 -M_W Load 10805 +M_W Load 10283 M_W Ifetch 0 <-- -M_W Store 5688 +M_W Store 5634 M_W L1_Replacement 0 <-- M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1572 +M_W Transient_Local_GETX 1545 M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2937 -M_W Persistent_GETX 7 -M_W Persistent_GETS 6 +M_W Transient_Local_GETS 2924 +M_W Persistent_GETX 4 +M_W Persistent_GETS 13 M_W Own_Lock_or_Unlock 0 <-- M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 107 +M_W Use_TimeoutStarverS 0 <-- +M_W Use_TimeoutNoStarvers 100 -MM_W Load 44028 +MM_W Load 44338 MM_W Ifetch 0 <-- -MM_W Store 23788 +MM_W Store 23776 MM_W L1_Replacement 0 <-- MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 967 +MM_W Transient_Local_GETX 908 MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1650 -MM_W Persistent_GETX 107 -MM_W Persistent_GETS 173 +MM_W Transient_Local_GETS 1759 +MM_W Persistent_GETX 73 +MM_W Persistent_GETS 147 MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 113 -MM_W Use_TimeoutStarverS 188 -MM_W Use_TimeoutNoStarvers 8511 +MM_W Use_TimeoutStarverX 77 +MM_W Use_TimeoutStarverS 164 +MM_W Use_TimeoutNoStarvers 8547 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L1_Replacement 0 <-- IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3101 -IM Ack 0 <-- +IM Data_Owner 1 +IM Data_All_Tokens 3142 +IM Ack 1 IM Transient_GETX 0 <-- -IM Transient_Local_GETX 259 +IM Transient_Local_GETX 232 IM Transient_GETS 0 <-- -IM Transient_Local_GETS 412 +IM Transient_Local_GETS 444 IM Transient_GETS_Last_Token 0 <-- IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5450 -IM Persistent_GETS 10069 -IM Own_Lock_or_Unlock 2398 -IM Request_Timeout 2209 +IM Persistent_GETX 5658 +IM Persistent_GETS 10537 +IM Own_Lock_or_Unlock 2485 +IM Request_Timeout 2317 SM Load 0 <-- SM Ifetch 0 <-- @@ -2875,12 +2875,12 @@ SM Store 0 <-- SM L1_Replacement 0 <-- SM Data_Shared 0 <-- SM Data_Owner 0 <-- -SM Data_All_Tokens 12 +SM Data_All_Tokens 2 SM Ack 0 <-- SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 +SM Transient_Local_GETX 11 SM Transient_GETS 0 <-- -SM Transient_Local_GETS 3 +SM Transient_Local_GETS 1 SM Transient_GETS_Last_Token 0 <-- SM Transient_Local_GETS_Last_Token 0 <-- SM Persistent_GETX 0 <-- @@ -2895,15 +2895,15 @@ OM L1_Replacement 0 <-- OM Data_Shared 0 <-- OM Data_All_Tokens 0 <-- OM Ack 0 <-- -OM Ack_All_Tokens 7 +OM Ack_All_Tokens 8 OM Transient_GETX 0 <-- OM Transient_Local_GETX 4 OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- +OM Transient_Local_GETS 1 OM Transient_GETS_Last_Token 0 <-- OM Transient_Local_GETS_Last_Token 0 <-- OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- +OM Persistent_GETS 1 OM Own_Lock_or_Unlock 0 <-- OM Request_Timeout 0 <-- @@ -2912,23 +2912,23 @@ IS Ifetch 0 <-- IS Store 0 <-- IS L1_Replacement 0 <-- IS Data_Shared 0 <-- -IS Data_Owner 12 -IS Data_All_Tokens 5791 +IS Data_Owner 20 +IS Data_All_Tokens 5732 IS Ack 0 <-- IS Transient_GETX 0 <-- -IS Transient_Local_GETX 471 +IS Transient_Local_GETX 463 IS Transient_GETS 0 <-- -IS Transient_Local_GETS 784 +IS Transient_Local_GETS 759 IS Transient_GETS_Last_Token 0 <-- IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10205 -IS Persistent_GETS 18777 -IS Own_Lock_or_Unlock 4518 -IS Request_Timeout 4152 +IS Persistent_GETX 10253 +IS Persistent_GETS 19299 +IS Own_Lock_or_Unlock 4569 +IS Request_Timeout 4269 -I_L Load 5803 +I_L Load 5747 I_L Ifetch 0 <-- -I_L Store 3097 +I_L Store 3129 I_L L1_Replacement 0 <-- I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- @@ -2940,13 +2940,13 @@ I_L Transient_GETS 0 <-- I_L Transient_Local_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 156 -I_L Persistent_GETS 291 +I_L Persistent_GETX 140 +I_L Persistent_GETS 344 I_L Own_Lock_or_Unlock 0 <-- -S_L Load 27 +S_L Load 21 S_L Ifetch 0 <-- -S_L Store 14 +S_L Store 10 S_L L1_Replacement 0 <-- S_L Data_Shared 0 <-- S_L Data_Owner 0 <-- @@ -2959,8 +2959,8 @@ S_L Transient_Local_GETS 0 <-- S_L Transient_GETS_Last_Token 0 <-- S_L Transient_Local_GETS_Last_Token 0 <-- S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 5 -S_L Own_Lock_or_Unlock 6 +S_L Persistent_GETS 3 +S_L Own_Lock_or_Unlock 3 IM_L Load 0 <-- IM_L Ifetch 0 <-- @@ -2968,18 +2968,18 @@ IM_L Store 0 <-- IM_L L1_Replacement 0 <-- IM_L Data_Shared 0 <-- IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 4 +IM_L Data_All_Tokens 2 IM_L Ack 0 <-- IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6464 +IM_L Transient_Local_GETX 6660 IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12152 +IM_L Transient_Local_GETS 12193 IM_L Transient_GETS_Last_Token 0 <-- IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2631 -IM_L Persistent_GETS 4457 -IM_L Own_Lock_or_Unlock 18612 -IM_L Request_Timeout 1035 +IM_L Persistent_GETX 2248 +IM_L Persistent_GETS 3909 +IM_L Own_Lock_or_Unlock 19321 +IM_L Request_Timeout 1049 SM_L Load 0 <-- SM_L Ifetch 0 <-- @@ -2996,8 +2996,8 @@ SM_L Transient_Local_GETS 0 <-- SM_L Transient_GETS_Last_Token 0 <-- SM_L Transient_Local_GETS_Last_Token 0 <-- SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 2 -SM_L Own_Lock_or_Unlock 14 +SM_L Persistent_GETS 0 <-- +SM_L Own_Lock_or_Unlock 11 SM_L Request_Timeout 0 <-- IS_L Load 0 <-- @@ -3006,18 +3006,18 @@ IS_L Store 0 <-- IS_L L1_Replacement 0 <-- IS_L Data_Shared 0 <-- IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 6 +IS_L Data_All_Tokens 3 IS_L Ack 0 <-- IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12337 +IS_L Transient_Local_GETX 12078 IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22486 +IS_L Transient_Local_GETS 22413 IS_L Transient_GETS_Last_Token 0 <-- IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4723 -IS_L Persistent_GETS 8637 -IS_L Own_Lock_or_Unlock 34778 -IS_L Request_Timeout 1903 +IS_L Persistent_GETX 4061 +IS_L Persistent_GETS 7310 +IS_L Own_Lock_or_Unlock 35295 +IS_L Request_Timeout 1879 Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 @@ -3030,10 +3030,10 @@ Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory --- L2Cache 0 --- - Event Counts - -L1_GETS 46234 +L1_GETS 46249 L1_GETS_Last_Token 0 -L1_GETX 25211 -L1_INV 71275 +L1_GETX 25069 +L1_INV 71135 Transient_GETX 0 Transient_GETS 0 Transient_GETS_Last_Token 0 @@ -3047,14 +3047,14 @@ Data_Owner 0 Data_All_Tokens 0 Ack 0 Ack_All_Tokens 0 -Persistent_GETX 29383 -Persistent_GETS 53856 -Own_Lock_or_Unlock 59385 +Persistent_GETX 28628 +Persistent_GETS 52955 +Own_Lock_or_Unlock 60779 - Transitions - -NP L1_GETS 63 -NP L1_GETX 127 -NP L1_INV 80 +NP L1_GETS 60 +NP L1_GETX 143 +NP L1_INV 78 NP Transient_GETX 0 <-- NP Transient_GETS 0 <-- NP Writeback_Tokens 0 <-- @@ -3067,7 +3067,7 @@ NP Data_All_Tokens 0 <-- NP Ack 0 <-- NP Persistent_GETX 0 <-- NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 59385 +NP Own_Lock_or_Unlock 60779 I L1_GETS 0 <-- I L1_GETS_Last_Token 0 <-- @@ -3138,9 +3138,9 @@ M Persistent_GETX 0 <-- M Persistent_GETS 0 <-- M Own_Lock_or_Unlock 0 <-- -I_L L1_GETS 46171 -I_L L1_GETX 25084 -I_L L1_INV 71195 +I_L L1_GETS 46189 +I_L L1_GETX 24926 +I_L L1_INV 71057 I_L Transient_GETX 0 <-- I_L Transient_GETS 0 <-- I_L Transient_GETS_Last_Token 0 <-- @@ -3153,8 +3153,8 @@ I_L Data_Shared 0 <-- I_L Data_Owner 0 <-- I_L Data_All_Tokens 0 <-- I_L Ack 0 <-- -I_L Persistent_GETX 29383 -I_L Persistent_GETS 53856 +I_L Persistent_GETX 28628 +I_L Persistent_GETS 52955 I_L Own_Lock_or_Unlock 0 <-- S_L L1_GETS 0 <-- @@ -3199,10 +3199,10 @@ Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: --- Directory 0 --- - Event Counts - -GETX 25384 -GETS 46466 -Lockdown 83239 -Unlockdown 59385 +GETX 25266 +GETS 46457 +Lockdown 81583 +Unlockdown 60779 Own_Lock_or_Unlock 0 Data_Owner 0 Data_All_Tokens 0 @@ -3218,8 +3218,8 @@ DMA_WRITE 0 DMA_WRITE_All_Tokens 0 - Transitions - -O GETX 2 -O GETS 0 <-- +O GETX 1 +O GETS 1 O Lockdown 0 <-- O Own_Lock_or_Unlock 0 <-- O Data_Owner 0 <-- @@ -3230,9 +3230,9 @@ O DMA_READ 0 <-- O DMA_WRITE 0 <-- O DMA_WRITE_All_Tokens 0 <-- -NO GETX 184 -NO GETS 63 -NO Lockdown 59387 +NO GETX 200 +NO GETS 59 +NO Lockdown 60781 NO Own_Lock_or_Unlock 0 <-- NO Data_Owner 0 <-- NO Data_All_Tokens 0 <-- @@ -3242,10 +3242,10 @@ NO Tokens 0 <-- NO DMA_READ 0 <-- NO DMA_WRITE 0 <-- -L GETX 25025 -L GETS 46171 -L Lockdown 23852 -L Unlockdown 59385 +L GETX 24868 +L GETS 46189 +L Lockdown 20802 +L Unlockdown 60779 L Own_Lock_or_Unlock 0 <-- L Data_Owner 0 <-- L Data_All_Tokens 0 <-- @@ -3310,8 +3310,8 @@ DR_L_W Memory_Data 0 <-- DR_L_W DMA_READ 0 <-- DR_L_W DMA_WRITE 0 <-- -NO_W GETX 173 -NO_W GETS 232 +NO_W GETX 197 +NO_W GETS 208 NO_W Lockdown 0 <-- NO_W Unlockdown 0 <-- NO_W Own_Lock_or_Unlock 0 <-- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index 3c80f8d99..d78beb62f 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -1,74 +1,74 @@ -system.cpu1: completed 10000 read accesses @320533 -system.cpu0: completed 10000 read accesses @324255 -system.cpu5: completed 10000 read accesses @329816 -system.cpu4: completed 10000 read accesses @330370 -system.cpu2: completed 10000 read accesses @330850 -system.cpu3: completed 10000 read accesses @330898 -system.cpu6: completed 10000 read accesses @330981 -system.cpu7: completed 10000 read accesses @332669 -system.cpu1: completed 20000 read accesses @645951 -system.cpu6: completed 20000 read accesses @654684 -system.cpu0: completed 20000 read accesses @655122 -system.cpu5: completed 20000 read accesses @655139 -system.cpu4: completed 20000 read accesses @658112 -system.cpu7: completed 20000 read accesses @659630 -system.cpu3: completed 20000 read accesses @662399 -system.cpu2: completed 20000 read accesses @662745 -system.cpu1: completed 30000 read accesses @971498 -system.cpu0: completed 30000 read accesses @979665 -system.cpu6: completed 30000 read accesses @980753 -system.cpu4: completed 30000 read accesses @986046 -system.cpu5: completed 30000 read accesses @986992 -system.cpu7: completed 30000 read accesses @990004 -system.cpu2: completed 30000 read accesses @992746 -system.cpu3: completed 30000 read accesses @994289 -system.cpu1: completed 40000 read accesses @1295713 -system.cpu0: completed 40000 read accesses @1304844 -system.cpu6: completed 40000 read accesses @1311609 -system.cpu4: completed 40000 read accesses @1313210 -system.cpu5: completed 40000 read accesses @1315669 -system.cpu7: completed 40000 read accesses @1321203 -system.cpu3: completed 40000 read accesses @1325768 -system.cpu2: completed 40000 read accesses @1327431 -system.cpu1: completed 50000 read accesses @1620139 -system.cpu0: completed 50000 read accesses @1624207 -system.cpu6: completed 50000 read accesses @1642053 -system.cpu5: completed 50000 read accesses @1643779 -system.cpu4: completed 50000 read accesses @1647677 -system.cpu7: completed 50000 read accesses @1653016 -system.cpu3: completed 50000 read accesses @1659224 -system.cpu2: completed 50000 read accesses @1659858 -system.cpu1: completed 60000 read accesses @1944324 -system.cpu0: completed 60000 read accesses @1947039 -system.cpu5: completed 60000 read accesses @1971722 -system.cpu6: completed 60000 read accesses @1971958 -system.cpu4: completed 60000 read accesses @1978467 -system.cpu3: completed 60000 read accesses @1984371 -system.cpu7: completed 60000 read accesses @1986116 -system.cpu2: completed 60000 read accesses @1990627 -system.cpu1: completed 70000 read accesses @2268077 -system.cpu0: completed 70000 read accesses @2271308 -system.cpu6: completed 70000 read accesses @2299743 -system.cpu5: completed 70000 read accesses @2302988 -system.cpu4: completed 70000 read accesses @2306754 -system.cpu3: completed 70000 read accesses @2313390 -system.cpu7: completed 70000 read accesses @2318502 -system.cpu2: completed 70000 read accesses @2323657 -system.cpu1: completed 80000 read accesses @2590310 -system.cpu0: completed 80000 read accesses @2594700 -system.cpu5: completed 80000 read accesses @2629321 -system.cpu6: completed 80000 read accesses @2631814 -system.cpu4: completed 80000 read accesses @2636634 -system.cpu7: completed 80000 read accesses @2643921 -system.cpu2: completed 80000 read accesses @2656705 -system.cpu3: completed 80000 read accesses @2656992 -system.cpu0: completed 90000 read accesses @2911654 -system.cpu1: completed 90000 read accesses @2922192 -system.cpu5: completed 90000 read accesses @2956637 -system.cpu4: completed 90000 read accesses @2959893 -system.cpu6: completed 90000 read accesses @2961119 -system.cpu7: completed 90000 read accesses @2975550 -system.cpu2: completed 90000 read accesses @2985342 -system.cpu3: completed 90000 read accesses @2990681 -system.cpu1: completed 100000 read accesses @3238178 +system.cpu2: completed 10000 read accesses @322194 +system.cpu0: completed 10000 read accesses @322719 +system.cpu5: completed 10000 read accesses @330050 +system.cpu7: completed 10000 read accesses @330574 +system.cpu6: completed 10000 read accesses @330892 +system.cpu4: completed 10000 read accesses @331172 +system.cpu1: completed 10000 read accesses @333911 +system.cpu3: completed 10000 read accesses @335019 +system.cpu0: completed 20000 read accesses @641579 +system.cpu2: completed 20000 read accesses @642932 +system.cpu6: completed 20000 read accesses @660969 +system.cpu4: completed 20000 read accesses @661309 +system.cpu5: completed 20000 read accesses @662083 +system.cpu7: completed 20000 read accesses @664047 +system.cpu1: completed 20000 read accesses @664884 +system.cpu3: completed 20000 read accesses @668081 +system.cpu0: completed 30000 read accesses @964302 +system.cpu2: completed 30000 read accesses @967590 +system.cpu4: completed 30000 read accesses @990023 +system.cpu7: completed 30000 read accesses @990043 +system.cpu6: completed 30000 read accesses @991961 +system.cpu5: completed 30000 read accesses @993160 +system.cpu1: completed 30000 read accesses @996431 +system.cpu3: completed 30000 read accesses @1001054 +system.cpu2: completed 40000 read accesses @1287629 +system.cpu0: completed 40000 read accesses @1291802 +system.cpu4: completed 40000 read accesses @1317065 +system.cpu7: completed 40000 read accesses @1322312 +system.cpu6: completed 40000 read accesses @1324580 +system.cpu5: completed 40000 read accesses @1326928 +system.cpu1: completed 40000 read accesses @1328485 +system.cpu3: completed 40000 read accesses @1330568 +system.cpu2: completed 50000 read accesses @1610807 +system.cpu0: completed 50000 read accesses @1611621 +system.cpu4: completed 50000 read accesses @1645302 +system.cpu7: completed 50000 read accesses @1650899 +system.cpu6: completed 50000 read accesses @1654396 +system.cpu5: completed 50000 read accesses @1657056 +system.cpu1: completed 50000 read accesses @1661586 +system.cpu3: completed 50000 read accesses @1662920 +system.cpu0: completed 60000 read accesses @1928533 +system.cpu2: completed 60000 read accesses @1935763 +system.cpu4: completed 60000 read accesses @1973168 +system.cpu7: completed 60000 read accesses @1985073 +system.cpu6: completed 60000 read accesses @1987312 +system.cpu1: completed 60000 read accesses @1992182 +system.cpu5: completed 60000 read accesses @1992692 +system.cpu3: completed 60000 read accesses @1994120 +system.cpu0: completed 70000 read accesses @2251425 +system.cpu2: completed 70000 read accesses @2258967 +system.cpu4: completed 70000 read accesses @2302588 +system.cpu6: completed 70000 read accesses @2314337 +system.cpu7: completed 70000 read accesses @2315937 +system.cpu5: completed 70000 read accesses @2322183 +system.cpu1: completed 70000 read accesses @2323330 +system.cpu3: completed 70000 read accesses @2326357 +system.cpu0: completed 80000 read accesses @2576249 +system.cpu2: completed 80000 read accesses @2582991 +system.cpu4: completed 80000 read accesses @2630111 +system.cpu6: completed 80000 read accesses @2644662 +system.cpu7: completed 80000 read accesses @2648201 +system.cpu1: completed 80000 read accesses @2650725 +system.cpu5: completed 80000 read accesses @2653106 +system.cpu3: completed 80000 read accesses @2653877 +system.cpu2: completed 90000 read accesses @2907948 +system.cpu0: completed 90000 read accesses @2917526 +system.cpu4: completed 90000 read accesses @2951732 +system.cpu6: completed 90000 read accesses @2969846 +system.cpu1: completed 90000 read accesses @2970686 +system.cpu3: completed 90000 read accesses @2978760 +system.cpu5: completed 90000 read accesses @2981622 +system.cpu7: completed 90000 read accesses @2987871 +system.cpu2: completed 100000 read accesses @3229931 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 90c08d2af..12db6638e 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:58:42 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:39:30 -M5 executing on cabr0210 -command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token +M5 compiled Jul 1 2010 14:39:47 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:40:13 +M5 executing on phenom +command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3238178 because maximum number of loads reached +Exiting @ tick 3229931 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 1e622c69a..aaeb05b60 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340284 # Number of bytes of host memory used -host_seconds 34.80 # Real time elapsed on the host -host_tick_rate 93055 # Simulator tick rate (ticks/s) +host_mem_usage 332852 # Number of bytes of host memory used +host_seconds 26.21 # Real time elapsed on the host +host_tick_rate 123225 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003238 # Number of seconds simulated -sim_ticks 3238178 # Number of ticks simulated +sim_seconds 0.003230 # Number of seconds simulated +sim_ticks 3229931 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99983 # number of read accesses completed -system.cpu0.num_writes 54267 # number of write accesses completed +system.cpu0.num_reads 99664 # number of read accesses completed +system.cpu0.num_writes 53551 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53571 # number of write accesses completed +system.cpu1.num_reads 97847 # number of read accesses completed +system.cpu1.num_writes 52926 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 97642 # number of read accesses completed -system.cpu2.num_writes 52892 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 54081 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 97531 # number of read accesses completed -system.cpu3.num_writes 52364 # number of write accesses completed +system.cpu3.num_reads 97548 # number of read accesses completed +system.cpu3.num_writes 52843 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98570 # number of read accesses completed -system.cpu4.num_writes 53173 # number of write accesses completed +system.cpu4.num_reads 98335 # number of read accesses completed +system.cpu4.num_writes 52557 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98261 # number of read accesses completed -system.cpu5.num_writes 52643 # number of write accesses completed +system.cpu5.num_reads 97595 # number of read accesses completed +system.cpu5.num_writes 52679 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98464 # number of read accesses completed -system.cpu6.num_writes 52805 # number of write accesses completed +system.cpu6.num_reads 97889 # number of read accesses completed +system.cpu6.num_writes 52461 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97833 # number of read accesses completed -system.cpu7.num_writes 52922 # number of write accesses completed +system.cpu7.num_reads 97463 # number of read accesses completed +system.cpu7.num_writes 51981 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 1b27f77ff..8cace1d25 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -22,7 +22,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports0.port[0] [system.cpu1] type=MemTest @@ -37,7 +37,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports1.port[0] [system.cpu2] type=MemTest @@ -52,7 +52,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports2.port[0] [system.cpu3] type=MemTest @@ -67,7 +67,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports3.port[0] [system.cpu4] type=MemTest @@ -82,7 +82,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports4.port[0] [system.cpu5] type=MemTest @@ -97,7 +97,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports5.port[0] [system.cpu6] type=MemTest @@ -112,7 +112,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports6.port[0] [system.cpu7] type=MemTest @@ -127,7 +127,7 @@ percent_uncacheable=0 progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.ruby.cpu_ruby_ports7.port[0] [system.funcmem] type=PhysicalMemory @@ -147,11 +147,11 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer block_size_bytes=64 clock=1 debug=system.ruby.debug @@ -164,6 +164,102 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer +[system.ruby.cpu_ruby_ports0] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.ruby.cpu_ruby_ports1] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.ruby.cpu_ruby_ports2] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.ruby.cpu_ruby_ports3] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.ruby.cpu_ruby_ports4] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.ruby.cpu_ruby_ports5] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.ruby.cpu_ruby_ports6] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.ruby.cpu_ruby_ports7] +type=RubySequencer +dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +deadlock_threshold=500000 +icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + [system.ruby.debug] type=RubyDebug filter_string=none @@ -202,52 +298,39 @@ weight=1 [system.ruby.network.topology.ext_links0.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports0 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test +size=256 -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links1] type=ExtLink @@ -260,52 +343,39 @@ weight=1 [system.ruby.network.topology.ext_links1.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports1 transitions_per_cycle=32 version=1 -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test +size=256 -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links2] type=ExtLink @@ -318,52 +388,39 @@ weight=1 [system.ruby.network.topology.ext_links2.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports2 transitions_per_cycle=32 version=2 -[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test +size=256 -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links3] type=ExtLink @@ -376,52 +433,39 @@ weight=1 [system.ruby.network.topology.ext_links3.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports3 transitions_per_cycle=32 version=3 -[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test +size=256 -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links4] type=ExtLink @@ -434,52 +478,39 @@ weight=1 [system.ruby.network.topology.ext_links4.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports4 transitions_per_cycle=32 version=4 -[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test +size=256 -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links5] type=ExtLink @@ -492,52 +523,39 @@ weight=1 [system.ruby.network.topology.ext_links5.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports5 transitions_per_cycle=32 version=5 -[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test +size=256 -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links6] type=ExtLink @@ -550,52 +568,39 @@ weight=1 [system.ruby.network.topology.ext_links6.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports6 transitions_per_cycle=32 version=6 -[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test +size=256 -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links7] type=ExtLink @@ -608,52 +613,39 @@ weight=1 [system.ruby.network.topology.ext_links7.ext_node] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory +L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory +L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory buffer_size=0 cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer +sequencer=system.ruby.cpu_ruby_ports7 transitions_per_cycle=32 version=7 -[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory] +[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory] type=RubyCache assoc=2 -latency=15 +latency=3 replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test +size=256 -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] +[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory] type=RubyCache assoc=2 latency=3 replacement_policy=PSEUDO_LRU size=256 -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] +[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory] type=RubyCache assoc=2 -latency=3 +latency=15 replacement_policy=PSEUDO_LRU -size=256 +size=512 [system.ruby.network.topology.ext_links8] type=ExtLink diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 347642d0a..5f070ae7c 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:41:16 +Real time: Jul/01/2010 14:39:27 Profiler Stats -------------- -Elapsed_time_in_seconds: 42 -Elapsed_time_in_minutes: 0.7 -Elapsed_time_in_hours: 0.0116667 -Elapsed_time_in_days: 0.000486111 +Elapsed_time_in_seconds: 32 +Elapsed_time_in_minutes: 0.533333 +Elapsed_time_in_hours: 0.00888889 +Elapsed_time_in_days: 0.00037037 -Virtual_time_in_seconds: 41.62 -Virtual_time_in_minutes: 0.693667 -Virtual_time_in_hours: 0.0115611 -Virtual_time_in_days: 0.000481713 +Virtual_time_in_seconds: 32.37 +Virtual_time_in_minutes: 0.5395 +Virtual_time_in_hours: 0.00899167 +Virtual_time_in_days: 0.000374653 -Ruby_current_time: 4339943 +Ruby_current_time: 4329426 Ruby_start_time: 0 -Ruby_cycles: 4339943 +Ruby_cycles: 4329426 -mbytes_resident: 31.0664 -mbytes_total: 331.992 -resident_ratio: 0.0935875 +mbytes_resident: 32.1484 +mbytes_total: 324.824 +resident_ratio: 0.0989838 -ruby_cycles_executed: [ 4339944 4339944 4339944 4339944 4339944 4339944 4339944 4339944 ] +ruby_cycles_executed: [ 4329427 4329427 4329427 4329427 4329427 4329427 4329427 4329427 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,13 +66,13 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1220000 average: 1.95591 | standard deviation: 0.205285 | 0 53784 1166216 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1217344 average: 1.9553 | standard deviation: 0.206639 | 0 54411 1162933 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 3607 count: 1219984 average: 54.9119 | standard deviation: 182.333 | 1064696 314 18737 8292 796 30614 532 5225 780 21798 1270 3844 11788 1197 5096 303 6413 275 5252 3545 375 4450 257 2872 2476 991 1837 556 2218 197 1865 604 1071 1361 228 1048 137 1046 570 388 599 212 546 244 393 212 323 210 211 245 53 220 76 196 114 49 122 38 113 45 62 37 35 59 19 37 14 22 34 5 16 10 13 8 11 4 10 3 6 9 1 4 1 2 3 2 1 4 6 0 0 4 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 3607 count: 792479 average: 51.7896 | standard deviation: 176.738 | 697175 1 11915 5038 177 19519 38 3208 50 13951 594 2378 7373 537 3179 11 4092 52 3231 2247 136 2884 69 1753 1510 586 1132 311 1374 79 1212 349 631 823 98 659 55 644 326 227 369 127 356 145 261 103 206 116 136 148 29 125 41 120 76 32 78 18 76 27 35 22 21 42 12 26 10 12 19 1 9 7 5 4 6 2 4 1 2 4 0 2 1 1 1 0 1 3 6 0 0 3 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 16 max: 3187 count: 427505 average: 60.6998 | standard deviation: 192.141 | 367521 0 0 313 6757 65 402 2852 317 302 297 10798 219 275 1248 769 238 492 7574 273 204 472 1357 109 352 4063 435 225 185 1732 53 239 2238 83 155 68 1856 165 56 1242 93 146 1291 275 136 52 936 183 83 883 266 139 145 560 172 73 479 365 36 82 427 226 56 199 408 32 55 483 84 46 80 309 63 19 348 54 52 192 102 59 13 217 74 11 119 71 54 45 75 57 18 91 105 12 31 63 60 15 28 69 15 9 79 16 18 17 57 19 5 33 9 8 26 18 13 7 25 12 5 13 13 14 8 7 14 0 4 13 3 4 3 8 1 3 9 1 2 13 1 3 3 4 3 0 5 3 3 1 1 4 0 2 5 1 1 1 3 1 3 2 0 1 2 0 0 0 1 0 0 2 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 16 max: 3117 count: 1217328 average: 54.8996 | standard deviation: 182.188 | 1062418 0 0 311 18298 68 401 7732 474 308 323 30614 240 267 3005 2219 254 546 21462 551 195 1076 3640 111 396 11292 946 204 417 4667 93 208 6265 158 167 149 5043 185 55 3548 197 160 3692 659 182 47 2461 384 73 2408 748 216 294 1630 503 61 1246 1085 74 108 1229 537 85 506 1072 74 67 1257 122 82 185 870 98 26 843 159 80 534 245 112 7 590 200 21 313 206 125 111 226 155 23 171 247 40 51 152 144 37 75 190 33 32 188 49 39 41 123 41 13 103 32 28 68 47 46 9 57 46 11 41 38 34 26 20 39 9 25 34 10 7 8 23 12 5 26 8 6 14 6 9 7 12 4 1 10 6 5 9 7 5 2 3 7 1 3 0 1 2 0 1 2 4 1 0 0 0 3 3 1 2 1 1 2 1 0 0 2 2 0 2 0 0 1 0 2 0 1 0 3 0 0 0 0 0 1 ] +miss_latency_2: [binsize: 16 max: 3017 count: 791763 average: 51.8282 | standard deviation: 176.682 | 696361 0 0 0 11763 0 0 4961 185 0 0 19895 35 0 1832 1425 8 44 13756 258 0 612 2313 2 16 7243 565 1 222 2975 5 5 3981 65 4 68 3212 39 2 2253 126 5 2376 378 46 1 1611 231 4 1523 465 103 153 1069 306 7 765 675 19 24 744 354 16 307 669 41 9 797 68 26 109 544 47 4 556 103 43 329 153 53 0 373 124 8 188 131 71 63 134 100 11 104 164 21 26 99 87 14 35 120 19 14 123 26 15 24 77 25 5 71 21 12 38 28 25 4 39 31 5 25 24 25 19 9 27 5 18 21 5 4 4 15 3 5 20 3 3 11 5 6 2 7 1 0 5 2 4 7 5 3 2 2 3 1 2 0 0 1 0 0 2 2 1 0 0 0 1 2 0 1 0 0 2 1 0 0 0 2 0 2 0 0 1 0 0 0 0 0 2 ] +miss_latency_3: [binsize: 16 max: 3117 count: 425565 average: 60.6139 | standard deviation: 191.881 | 366057 0 0 311 6535 68 401 2771 289 308 323 10719 205 267 1173 794 246 502 7706 293 195 464 1327 109 380 4049 381 203 195 1692 88 203 2284 93 163 81 1831 146 53 1295 71 155 1316 281 136 46 850 153 69 885 283 113 141 561 197 54 481 410 55 84 485 183 69 199 403 33 58 460 54 56 76 326 51 22 287 56 37 205 92 59 7 217 76 13 125 75 54 48 92 55 12 67 83 19 25 53 57 23 40 70 14 18 65 23 24 17 46 16 8 32 11 16 30 19 21 5 18 15 6 16 14 9 7 11 12 4 7 13 5 3 4 8 9 0 6 5 3 3 1 3 5 5 3 1 5 4 1 2 2 2 0 1 4 0 1 0 1 1 0 1 0 2 0 0 0 0 2 1 1 1 1 1 0 0 0 0 2 0 0 0 0 0 0 0 2 0 1 0 1 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -102,240 +102,240 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 41 +user_time: 32 system_time: 0 -page_reclaims: 8947 +page_reclaims: 8443 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 48 +block_outputs: 88 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.251482 - links_utilized_percent_switch_0_link_0: 0.123013 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.379951 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 19379 1395288 [ 0 0 0 0 19379 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 116856 934848 [ 0 0 0 0 116856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 135827 1086616 [ 0 0 0 135827 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 19464 155712 [ 0 0 19464 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 19380 1395360 [ 0 0 0 0 19380 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 116447 931576 [ 0 0 0 0 116447 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 19462 155696 [ 0 0 0 0 0 19462 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.251323 + links_utilized_percent_switch_0_link_0: 0.12279 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.379855 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 19278 1388016 [ 0 0 0 0 19278 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 116236 929888 [ 0 0 0 0 116236 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Forwarded_Control: 135551 1084408 [ 0 0 0 135551 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 19361 154888 [ 0 0 19361 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 19330 1391760 [ 0 0 0 0 19330 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 116221 929768 [ 0 0 0 0 116221 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 19359 154872 [ 0 0 0 0 0 19359 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.251327 - links_utilized_percent_switch_1_link_0: 0.122954 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.3797 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 19361 1393992 [ 0 0 0 0 19361 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 116804 934432 [ 0 0 0 0 116804 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 135837 1086696 [ 0 0 0 135837 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 19454 155632 [ 0 0 19454 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 19354 1393488 [ 0 0 0 0 19354 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 116483 931864 [ 0 0 0 0 116483 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 19452 155616 [ 0 0 0 0 0 19452 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.251069 + links_utilized_percent_switch_1_link_0: 0.122725 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.379413 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 19261 1386792 [ 0 0 0 0 19261 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 116147 929176 [ 0 0 0 0 116147 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 135566 1084528 [ 0 0 0 135566 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 19346 154768 [ 0 0 19346 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 19284 1388448 [ 0 0 0 0 19284 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 116282 930256 [ 0 0 0 0 116282 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 19344 154752 [ 0 0 0 0 0 19344 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.250111 - links_utilized_percent_switch_2_link_0: 0.122199 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.378023 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 19177 1380744 [ 0 0 0 0 19177 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 115650 925200 [ 0 0 0 0 115650 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 136028 1088224 [ 0 0 0 136028 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 19263 154104 [ 0 0 19263 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 19196 1382112 [ 0 0 0 0 19196 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 116832 934656 [ 0 0 0 0 116832 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 19261 154088 [ 0 0 0 0 0 19261 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.250795 + links_utilized_percent_switch_2_link_0: 0.122802 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.378788 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 19292 1389024 [ 0 0 0 0 19292 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 116138 929104 [ 0 0 0 0 116138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 135563 1084504 [ 0 0 0 135563 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 19349 154792 [ 0 0 19349 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 19216 1383552 [ 0 0 0 0 19216 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 116347 930776 [ 0 0 0 0 116347 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 19347 154776 [ 0 0 0 0 0 19347 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.25008 - links_utilized_percent_switch_3_link_0: 0.122428 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.377733 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 19237 1385064 [ 0 0 0 0 19237 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 115954 927632 [ 0 0 0 0 115954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 135976 1087808 [ 0 0 0 135976 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 19315 154520 [ 0 0 19315 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 19158 1379376 [ 0 0 0 0 19158 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 116818 934544 [ 0 0 0 0 116818 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 19313 154504 [ 0 0 0 0 0 19313 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.251498 + links_utilized_percent_switch_3_link_0: 0.123014 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.379982 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 19333 1391976 [ 0 0 0 0 19333 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 116572 932576 [ 0 0 0 0 116572 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 135495 1083960 [ 0 0 0 135495 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 19416 155328 [ 0 0 19416 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 19337 1392264 [ 0 0 0 0 19337 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 116158 929264 [ 0 0 0 0 116158 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 19414 155312 [ 0 0 0 0 0 19414 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.251163 - links_utilized_percent_switch_4_link_0: 0.122805 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.379521 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Response_Data: 19329 1391688 [ 0 0 0 0 19329 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 116534 932272 [ 0 0 0 0 116534 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 135880 1087040 [ 0 0 0 135880 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 19411 155288 [ 0 0 19411 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 19340 1392480 [ 0 0 0 0 19340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 116540 932320 [ 0 0 0 0 116540 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 19409 155272 [ 0 0 0 0 0 19409 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.249848 + links_utilized_percent_switch_4_link_0: 0.12226 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.377437 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 19149 1378728 [ 0 0 0 0 19149 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 115426 923408 [ 0 0 0 0 115426 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 135685 1085480 [ 0 0 0 135685 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 19227 153816 [ 0 0 19227 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 19085 1374120 [ 0 0 0 0 19085 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 116600 932800 [ 0 0 0 0 116600 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 19225 153800 [ 0 0 0 0 0 19225 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.251317 - links_utilized_percent_switch_5_link_0: 0.122856 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.379778 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Response_Data: 19339 1392408 [ 0 0 0 0 19339 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 116636 933088 [ 0 0 0 0 116636 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 135863 1086904 [ 0 0 0 135863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 19427 155416 [ 0 0 19427 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 19366 1394352 [ 0 0 0 0 19366 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 116497 931976 [ 0 0 0 0 116497 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 19425 155400 [ 0 0 0 0 0 19425 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.249997 + links_utilized_percent_switch_5_link_0: 0.122273 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.377721 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 19150 1378800 [ 0 0 0 0 19150 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 115467 923736 [ 0 0 0 0 115467 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 135679 1085432 [ 0 0 0 135679 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 19233 153864 [ 0 0 19233 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 19115 1376280 [ 0 0 0 0 19115 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 116564 932512 [ 0 0 0 0 116564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 19231 153848 [ 0 0 0 0 0 19231 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.250843 - links_utilized_percent_switch_6_link_0: 0.122534 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.379151 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Response_Data: 19266 1387152 [ 0 0 0 0 19266 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 116086 928688 [ 0 0 0 0 116086 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 135953 1087624 [ 0 0 0 135953 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 19338 154704 [ 0 0 19338 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 19309 1390248 [ 0 0 0 0 19309 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 116644 933152 [ 0 0 0 0 116644 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 19336 154688 [ 0 0 0 0 0 19336 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.252646 + links_utilized_percent_switch_6_link_0: 0.12355 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.381742 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 19460 1401120 [ 0 0 0 0 19460 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 117425 939400 [ 0 0 0 0 117425 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 135355 1082840 [ 0 0 0 135355 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 19556 156448 [ 0 0 19556 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 19510 1404720 [ 0 0 0 0 19510 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 115845 926760 [ 0 0 0 0 115845 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 19554 156432 [ 0 0 0 0 0 19554 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.252566 - links_utilized_percent_switch_7_link_0: 0.123671 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.381461 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Response_Data: 19539 1406808 [ 0 0 0 0 19539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 117871 942968 [ 0 0 0 0 117871 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 135659 1085272 [ 0 0 0 135659 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 19631 157048 [ 0 0 19631 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 19523 1405656 [ 0 0 0 0 19523 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 116136 929088 [ 0 0 0 0 116136 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 19630 157040 [ 0 0 0 0 0 19630 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.251885 + links_utilized_percent_switch_7_link_0: 0.123116 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.380653 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 19363 1394136 [ 0 0 0 0 19363 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 116675 933400 [ 0 0 0 0 116675 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 135476 1083808 [ 0 0 0 135476 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 19436 155488 [ 0 0 19436 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 19407 1397304 [ 0 0 0 0 19407 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 116069 928552 [ 0 0 0 0 116069 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 19434 155472 [ 0 0 0 0 0 19434 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.134192 - links_utilized_percent_switch_8_link_0: 0.0894571 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.178927 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.13419 + links_utilized_percent_switch_8_link_0: 0.0894553 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.178924 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 155303 1242424 [ 0 0 155303 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 155288 1242304 [ 0 0 0 0 0 155288 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 154924 1239392 [ 0 0 154924 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 154908 1239264 [ 0 0 0 0 0 154908 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 155289 1242312 [ 0 0 0 155289 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Forwarded_Control: 154910 1239280 [ 0 0 0 154910 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 0.47641 - links_utilized_percent_switch_9_link_0: 0.49205 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.491815 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.488798 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.48971 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.491222 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.491441 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.490137 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.494685 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.357828 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Response_Data: 19379 1395288 [ 0 0 0 0 19379 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 116856 934848 [ 0 0 0 0 116856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Forwarded_Control: 135827 1086616 [ 0 0 0 135827 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 19361 1393992 [ 0 0 0 0 19361 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 116804 934432 [ 0 0 0 0 116804 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Forwarded_Control: 135837 1086696 [ 0 0 0 135837 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 19177 1380744 [ 0 0 0 0 19177 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 115650 925200 [ 0 0 0 0 115650 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Forwarded_Control: 136028 1088224 [ 0 0 0 136028 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 19237 1385064 [ 0 0 0 0 19237 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 115954 927632 [ 0 0 0 0 115954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Forwarded_Control: 135976 1087808 [ 0 0 0 135976 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 19329 1391688 [ 0 0 0 0 19329 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 116534 932272 [ 0 0 0 0 116534 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Forwarded_Control: 135880 1087040 [ 0 0 0 135880 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 19340 1392480 [ 0 0 0 0 19340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 116642 933136 [ 0 0 0 0 116642 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Forwarded_Control: 135863 1086904 [ 0 0 0 135863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 19266 1387152 [ 0 0 0 0 19266 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 116086 928688 [ 0 0 0 0 116086 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Forwarded_Control: 135953 1087624 [ 0 0 0 135953 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 19539 1406808 [ 0 0 0 0 19539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 117871 942968 [ 0 0 0 0 117871 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Forwarded_Control: 135659 1085272 [ 0 0 0 135659 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 155303 1242424 [ 0 0 155303 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 155288 1242304 [ 0 0 0 0 0 155288 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 61.7242% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 38.2758% - - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19464 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19464 average: 1 | standard deviation: 0 | 0 19464 ] +links_utilized_percent_switch_9: 0.476438 + links_utilized_percent_switch_9_link_0: 0.491161 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.490899 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.491207 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.492056 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.489039 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.48909 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.494199 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.492465 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 0.357821 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Response_Data: 19278 1388016 [ 0 0 0 0 19278 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 116236 929888 [ 0 0 0 0 116236 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Forwarded_Control: 135551 1084408 [ 0 0 0 135551 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 19261 1386792 [ 0 0 0 0 19261 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 116147 929176 [ 0 0 0 0 116147 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Forwarded_Control: 135566 1084528 [ 0 0 0 135566 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 19292 1389024 [ 0 0 0 0 19292 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 116138 929104 [ 0 0 0 0 116138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Forwarded_Control: 135563 1084504 [ 0 0 0 135563 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 19333 1391976 [ 0 0 0 0 19333 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 116572 932576 [ 0 0 0 0 116572 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Forwarded_Control: 135495 1083960 [ 0 0 0 135495 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 19149 1378728 [ 0 0 0 0 19149 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 115426 923408 [ 0 0 0 0 115426 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Forwarded_Control: 135685 1085480 [ 0 0 0 135685 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 19150 1378800 [ 0 0 0 0 19150 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 115467 923736 [ 0 0 0 0 115467 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Forwarded_Control: 135679 1085432 [ 0 0 0 135679 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 19460 1401120 [ 0 0 0 0 19460 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 117425 939400 [ 0 0 0 0 117425 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Forwarded_Control: 135355 1082840 [ 0 0 0 135355 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 19363 1394136 [ 0 0 0 0 19363 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 116675 933400 [ 0 0 0 0 116675 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Forwarded_Control: 135476 1083808 [ 0 0 0 135476 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 154924 1239392 [ 0 0 154924 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 154908 1239264 [ 0 0 0 0 0 154908 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_total_hw_prefetches: 0 + + system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_misses: 19361 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_demand_misses: 19361 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_total_hw_prefetches: 0 + + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_type_LD: 61.4121% + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_type_ST: 38.5879% + + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19361 100% + system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19361 average: 1 | standard deviation: 0 | 0 19361 ] Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 19464 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 19361 + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 19361 system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 61.7242% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 38.2758% + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 61.4121% + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 38.5879% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19464 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19464 average: 1 | standard deviation: 0 | 0 19464 ] + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19361 100% + system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19361 average: 1 | standard deviation: 0 | 0 19361 ] --- L1Cache 0 --- - Event Counts - -Load 99315 +Load 99344 Ifetch 0 -Store 53538 +Store 53020 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52535 -Other_GETS 83292 -Ack 116277 -Shared_Ack 579 -Data 284 -Shared_Data 730 -Exclusive_Data 18365 +Other_GETX 52037 +Other_GETS 83514 +Ack 115719 +Shared_Ack 517 +Data 275 +Shared_Data 698 +Exclusive_Data 18305 Writeback_Ack 0 Writeback_Nack 0 -All_acks 730 -All_acks_no_sharers 18732 +All_acks 698 +All_acks_no_sharers 18661 - Transitions - -I Load 12014 +I Load 11890 I Ifetch 0 <-- -I Store 6365 +I Store 6416 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -343,123 +343,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1350 +S Load 1247 S Ifetch 0 <-- -S Store 707 +S Store 677 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 23 -S Other_GETS 26 +S Other_GETX 21 +S Other_GETS 22 -O Load 765 +O Load 699 O Ifetch 0 <-- O Store 378 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 4 +O Other_GETX 1 +O Other_GETS 2 -M Load 19541 +M Load 19926 M Ifetch 0 <-- -M Store 10690 +M Store 10584 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 380 +M Other_GETX 227 +M Other_GETS 379 -MM Load 65645 +MM Load 65582 MM Ifetch 0 <-- -MM Store 35398 +MM Store 34965 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6950 -MM Other_GETS 11190 +MM Other_GETX 6807 +MM Other_GETS 11248 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 16962 -IM Other_GETS 26097 -IM Ack 21942 -IM Data 196 -IM Exclusive_Data 7083 +IM Other_GETX 17706 +IM Other_GETS 27589 +IM Ack 21983 +IM Data 203 +IM Exclusive_Data 7115 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 619 -SM Other_GETS 540 -SM Ack 244 -SM Data 88 +SM Other_GETX 605 +SM Other_GETS 542 +SM Ack 227 +SM Data 72 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 295 -OM Other_GETS 347 -OM Ack 581 +OM Other_GETX 297 +OM Other_GETS 369 +OM Ack 567 OM All_acks 0 <-- -OM All_acks_no_sharers 83 +OM All_acks_no_sharers 81 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 912 -ISM All_acks_no_sharers 284 +ISM Ack 752 +ISM All_acks_no_sharers 275 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 34227 -M_W All_acks_no_sharers 11282 +M_W Ack 33721 +M_W All_acks_no_sharers 11190 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21105 -MM_W All_acks_no_sharers 7083 +MM_W Ack 21378 +MM_W All_acks_no_sharers 7115 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 27472 -IS Other_GETS 44708 -IS Ack 35359 -IS Shared_Ack 275 +IS Other_GETX 26373 +IS Other_GETS 43363 +IS Ack 35284 +IS Shared_Ack 271 IS Data 0 <-- -IS Shared_Data 730 -IS Exclusive_Data 11282 +IS Shared_Data 698 +IS Exclusive_Data 11190 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1907 -SS Shared_Ack 304 -SS All_acks 730 +SS Ack 1807 +SS Shared_Ack 246 +SS All_acks 698 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -490,66 +490,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_misses: 19346 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_demand_misses: 19346 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_LD: 60.7587% - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_ST: 39.2413% + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_type_LD: 61.4442% + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_type_ST: 38.5558% - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19454 100% - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19454 average: 1 | standard deviation: 0 | 0 19454 ] + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19346 100% + system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19346 average: 1 | standard deviation: 0 | 0 19346 ] Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 19454 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 19346 + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 19346 system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_LD: 60.7587% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_ST: 39.2413% + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_LD: 61.4442% + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_ST: 38.5558% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19454 100% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19454 average: 1 | standard deviation: 0 | 0 19454 ] + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19346 100% + system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19346 average: 1 | standard deviation: 0 | 0 19346 ] --- L1Cache 1 --- - Event Counts - -Load 99091 +Load 98746 Ifetch 0 -Store 53648 +Store 53385 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52351 -Other_GETS 83486 -Ack 116231 -Shared_Ack 573 -Data 284 -Shared_Data 719 -Exclusive_Data 18358 +Other_GETX 52050 +Other_GETS 83516 +Ack 115650 +Shared_Ack 497 +Data 304 +Shared_Data 680 +Exclusive_Data 18277 Writeback_Ack 0 Writeback_Nack 0 -All_acks 719 -All_acks_no_sharers 18733 +All_acks 680 +All_acks_no_sharers 18664 - Transitions - -I Load 11820 +I Load 11887 I Ifetch 0 <-- -I Store 6576 +I Store 6432 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -557,123 +557,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1335 +S Load 1220 S Ifetch 0 <-- -S Store 697 +S Store 661 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 22 -S Other_GETS 20 +S Other_GETX 19 +S Other_GETS 15 -O Load 610 +O Load 681 O Ifetch 0 <-- -O Store 361 +O Store 366 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 3 +O Other_GETX 2 +O Other_GETS 1 -M Load 19135 +M Load 20150 M Ifetch 0 <-- -M Store 10524 +M Store 10628 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 214 -M Other_GETS 361 +M Other_GETX 210 +M Other_GETS 368 -MM Load 66191 +MM Load 64808 MM Ifetch 0 <-- -MM Store 35490 +MM Store 35298 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6927 -MM Other_GETS 11231 +MM Other_GETX 6880 +MM Other_GETS 11206 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17561 -IM Other_GETS 27274 -IM Ack 22346 -IM Data 200 -IM Exclusive_Data 7259 +IM Other_GETX 17173 +IM Other_GETS 26846 +IM Ack 21762 +IM Data 215 +IM Exclusive_Data 7071 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 613 -SM Other_GETS 531 -SM Ack 230 -SM Data 84 +SM Other_GETX 572 +SM Other_GETS 527 +SM Ack 242 +SM Data 89 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 270 -OM Other_GETS 348 -OM Ack 637 +OM Other_GETX 283 +OM Other_GETS 334 +OM Ack 581 OM All_acks 0 <-- -OM All_acks_no_sharers 91 +OM All_acks_no_sharers 83 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 920 -ISM All_acks_no_sharers 284 +ISM Ack 963 +ISM All_acks_no_sharers 304 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33416 -M_W All_acks_no_sharers 11099 +M_W Ack 33742 +M_W All_acks_no_sharers 11206 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21763 -MM_W All_acks_no_sharers 7259 +MM_W Ack 21283 +MM_W All_acks_no_sharers 7071 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 26744 -IS Other_GETS 43718 -IS Ack 35027 -IS Shared_Ack 279 +IS Other_GETX 26911 +IS Other_GETS 44219 +IS Ack 35249 +IS Shared_Ack 242 IS Data 0 <-- -IS Shared_Data 719 -IS Exclusive_Data 11099 +IS Shared_Data 680 +IS Exclusive_Data 11206 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1892 -SS Shared_Ack 294 -SS All_acks 719 +SS Ack 1828 +SS Shared_Ack 255 +SS All_acks 680 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -704,66 +704,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_misses: 19349 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_demand_misses: 19349 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_LD: 61.5325% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_ST: 38.4675% + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_type_LD: 61.3417% + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_type_ST: 38.6583% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19263 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19263 average: 1 | standard deviation: 0 | 0 19263 ] + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19349 100% + system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19349 average: 1 | standard deviation: 0 | 0 19349 ] Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_demand_misses: 19263 + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_misses: 19349 + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_demand_misses: 19349 system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_LD: 61.5325% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_ST: 38.4675% + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_LD: 61.3417% + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_ST: 38.6583% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19263 100% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19263 average: 1 | standard deviation: 0 | 0 19263 ] + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19349 100% + system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19349 average: 1 | standard deviation: 0 | 0 19349 ] --- L1Cache 2 --- - Event Counts - -Load 98496 +Load 98624 Ifetch 0 -Store 52751 +Store 53315 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52575 -Other_GETS 83453 -Ack 115139 -Shared_Ack 511 -Data 296 -Shared_Data 707 -Exclusive_Data 18174 +Other_GETX 52030 +Other_GETS 83533 +Ack 115623 +Shared_Ack 515 +Data 272 +Shared_Data 719 +Exclusive_Data 18301 Writeback_Ack 0 Writeback_Nack 0 -All_acks 707 -All_acks_no_sharers 18554 +All_acks 719 +All_acks_no_sharers 18628 - Transitions - -I Load 11853 +I Load 11869 I Ifetch 0 <-- -I Store 6345 +I Store 6439 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -771,123 +771,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1284 +S Load 1254 S Ifetch 0 <-- -S Store 693 +S Store 699 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 14 -S Other_GETS 24 +S Other_GETX 20 +S Other_GETS 18 -O Load 671 +O Load 672 O Ifetch 0 <-- -O Store 372 +O Store 342 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 2 +O Other_GETX 2 +O Other_GETS 1 -M Load 19735 +M Load 19515 M Ifetch 0 <-- -M Store 10526 +M Store 10604 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 246 -M Other_GETS 372 +M Other_GETX 202 +M Other_GETS 344 -MM Load 64953 +MM Load 65314 MM Ifetch 0 <-- -MM Store 34815 +MM Store 35231 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6748 -MM Other_GETS 11188 +MM Other_GETX 6815 +MM Other_GETS 11267 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17422 -IM Other_GETS 26671 -IM Ack 21637 -IM Data 202 -IM Exclusive_Data 7030 +IM Other_GETX 17023 +IM Other_GETS 26686 +IM Ack 22228 +IM Data 199 +IM Exclusive_Data 7151 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 599 -SM Other_GETS 537 -SM Ack 292 -SM Data 94 +SM Other_GETX 626 +SM Other_GETS 536 +SM Ack 221 +SM Data 73 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 288 -OM Other_GETS 352 -OM Ack 588 +OM Other_GETX 286 +OM Other_GETS 299 +OM Ack 385 OM All_acks 0 <-- -OM All_acks_no_sharers 84 +OM All_acks_no_sharers 55 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 871 -ISM All_acks_no_sharers 296 +ISM Ack 823 +ISM All_acks_no_sharers 272 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33302 -M_W All_acks_no_sharers 11144 +M_W Ack 33805 +M_W All_acks_no_sharers 11150 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21156 -MM_W All_acks_no_sharers 7030 +MM_W Ack 21267 +MM_W All_acks_no_sharers 7151 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 27258 -IS Other_GETS 44307 -IS Ack 35532 -IS Shared_Ack 290 +IS Other_GETX 27056 +IS Other_GETS 44382 +IS Ack 35091 +IS Shared_Ack 273 IS Data 0 <-- -IS Shared_Data 707 -IS Exclusive_Data 11144 +IS Shared_Data 719 +IS Exclusive_Data 11150 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1761 -SS Shared_Ack 221 -SS All_acks 707 +SS Ack 1803 +SS Shared_Ack 242 +SS All_acks 719 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -918,66 +918,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_misses: 19416 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_demand_misses: 19416 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_LD: 61.4134% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_ST: 38.5866% + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_type_LD: 61.9077% + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_type_ST: 38.0923% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19315 100% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19315 average: 1 | standard deviation: 0 | 0 19315 ] + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19416 100% + system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19416 average: 1 | standard deviation: 0 | 0 19416 ] Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_demand_misses: 19315 + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_misses: 19416 + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_demand_misses: 19416 system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_LD: 61.4134% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_ST: 38.5866% + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_LD: 61.9077% + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_ST: 38.0923% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19315 100% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19315 average: 1 | standard deviation: 0 | 0 19315 ] + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19416 100% + system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19416 average: 1 | standard deviation: 0 | 0 19416 ] --- L1Cache 3 --- - Event Counts - -Load 98500 +Load 99275 Ifetch 0 -Store 53165 +Store 53327 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52533 -Other_GETS 83443 -Ack 115416 -Shared_Ack 538 -Data 260 -Shared_Data 726 -Exclusive_Data 18251 +Other_GETX 52112 +Other_GETS 83383 +Ack 116023 +Shared_Ack 549 +Data 281 +Shared_Data 715 +Exclusive_Data 18337 Writeback_Ack 0 Writeback_Nack 0 -All_acks 726 -All_acks_no_sharers 18587 +All_acks 715 +All_acks_no_sharers 18700 - Transitions - -I Load 11862 +I Load 12020 I Ifetch 0 <-- -I Store 6402 +I Store 6330 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -985,123 +985,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1302 +S Load 1337 S Ifetch 0 <-- -S Store 707 +S Store 692 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 19 -S Other_GETS 14 +S Other_GETX 22 +S Other_GETS 24 -O Load 637 +O Load 652 O Ifetch 0 <-- -O Store 344 +O Store 374 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 0 <-- +O Other_GETX 1 O Other_GETS 1 -M Load 19387 +M Load 19894 M Ifetch 0 <-- -M Store 10581 +M Store 10721 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 210 -M Other_GETS 344 +M Other_GETX 208 +M Other_GETS 375 -MM Load 65312 +MM Load 65372 MM Ifetch 0 <-- -MM Store 35131 +MM Store 35210 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 7026 -MM Other_GETS 11007 +MM Other_GETX 6827 +MM Other_GETS 11290 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17035 -IM Other_GETS 26879 -IM Ack 22135 -IM Data 176 -IM Exclusive_Data 7116 +IM Other_GETX 16735 +IM Other_GETS 26100 +IM Ack 21436 +IM Data 174 +IM Exclusive_Data 7033 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 623 -SM Other_GETS 550 -SM Ack 260 -SM Data 84 +SM Other_GETX 585 +SM Other_GETS 551 +SM Ack 310 +SM Data 107 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 268 -OM Other_GETS 302 -OM Ack 532 +OM Other_GETX 292 +OM Other_GETS 343 +OM Ack 574 OM All_acks 0 <-- -OM All_acks_no_sharers 76 +OM All_acks_no_sharers 82 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 773 -ISM All_acks_no_sharers 260 +ISM Ack 887 +ISM All_acks_no_sharers 281 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33558 -M_W All_acks_no_sharers 11135 +M_W Ack 34315 +M_W All_acks_no_sharers 11304 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21088 -MM_W All_acks_no_sharers 7116 +MM_W Ack 21251 +MM_W All_acks_no_sharers 7033 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 27352 -IS Other_GETS 44346 -IS Ack 35080 -IS Shared_Ack 265 +IS Other_GETX 27442 +IS Other_GETS 44699 +IS Ack 35339 +IS Shared_Ack 289 IS Data 0 <-- -IS Shared_Data 726 -IS Exclusive_Data 11135 +IS Shared_Data 715 +IS Exclusive_Data 11304 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1990 -SS Shared_Ack 273 -SS All_acks 726 +SS Ack 1911 +SS Shared_Ack 260 +SS All_acks 715 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -1132,66 +1132,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_misses: 19227 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_demand_misses: 19227 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_LD: 62.0061% - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_ST: 37.9939% + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_type_LD: 61.6269% + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_type_ST: 38.3731% - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19411 100% - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19411 average: 1 | standard deviation: 0 | 0 19411 ] + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19227 100% + system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19227 average: 1 | standard deviation: 0 | 0 19227 ] Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_demand_misses: 19411 + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_misses: 19227 + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_demand_misses: 19227 system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_LD: 62.0061% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_ST: 37.9939% + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_LD: 61.6269% + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_ST: 38.3731% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19411 100% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19411 average: 1 | standard deviation: 0 | 0 19411 ] + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19227 100% + system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19227 average: 1 | standard deviation: 0 | 0 19227 ] --- L1Cache 4 --- - Event Counts - -Load 99038 +Load 98085 Ifetch 0 -Store 53408 +Store 52520 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52611 -Other_GETS 83269 -Ack 115968 -Shared_Ack 566 -Data 266 -Shared_Data 702 -Exclusive_Data 18361 +Other_GETX 52130 +Other_GETS 83555 +Ack 114858 +Shared_Ack 568 +Data 293 +Shared_Data 735 +Exclusive_Data 18121 Writeback_Ack 0 Writeback_Nack 0 -All_acks 702 -All_acks_no_sharers 18707 +All_acks 735 +All_acks_no_sharers 18490 - Transitions - -I Load 12036 +I Load 11849 I Ifetch 0 <-- -I Store 6312 +I Store 6303 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -1199,123 +1199,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1172 +S Load 1289 S Ifetch 0 <-- -S Store 685 +S Store 724 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 17 -S Other_GETS 16 +S Other_GETX 11 +S Other_GETS 20 -O Load 670 +O Load 650 O Ifetch 0 <-- -O Store 378 +O Store 351 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 1 +O Other_GETX 0 <-- +O Other_GETS 0 <-- -M Load 20047 +M Load 19521 M Ifetch 0 <-- -M Store 10741 +M Store 10542 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 380 +M Other_GETX 219 +M Other_GETS 351 -MM Load 65113 +MM Load 64776 MM Ifetch 0 <-- -MM Store 35292 +MM Store 34600 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6885 -MM Other_GETS 11230 +MM Other_GETX 6837 +MM Other_GETS 11083 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17299 -IM Other_GETS 26539 -IM Ack 21568 -IM Data 187 -IM Exclusive_Data 7028 +IM Other_GETX 17328 +IM Other_GETS 27038 +IM Ack 21720 +IM Data 204 +IM Exclusive_Data 7009 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 606 -SM Other_GETS 507 -SM Ack 251 -SM Data 79 +SM Other_GETX 635 +SM Other_GETS 551 +SM Ack 280 +SM Data 89 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 298 -OM Other_GETS 332 -OM Ack 560 +OM Other_GETX 275 +OM Other_GETS 320 +OM Ack 532 OM All_acks 0 <-- -OM All_acks_no_sharers 80 +OM All_acks_no_sharers 76 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 805 -ISM All_acks_no_sharers 266 +ISM Ack 903 +ISM All_acks_no_sharers 293 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33929 -M_W All_acks_no_sharers 11333 +M_W Ack 33570 +M_W All_acks_no_sharers 11112 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21140 -MM_W All_acks_no_sharers 7028 +MM_W Ack 20909 +MM_W All_acks_no_sharers 7009 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 27292 -IS Other_GETS 44264 -IS Ack 35919 -IS Shared_Ack 277 +IS Other_GETX 26825 +IS Other_GETS 44192 +IS Ack 35093 +IS Shared_Ack 270 IS Data 0 <-- -IS Shared_Data 702 -IS Exclusive_Data 11333 +IS Shared_Data 735 +IS Exclusive_Data 11112 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1796 -SS Shared_Ack 289 -SS All_acks 702 +SS Ack 1851 +SS Shared_Ack 298 +SS All_acks 735 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -1346,66 +1346,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_misses: 19233 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_demand_misses: 19233 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_LD: 61.3219% - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_ST: 38.6781% + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_type_LD: 61.2905% + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_type_ST: 38.7095% - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19427 100% - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19427 average: 1 | standard deviation: 0 | 0 19427 ] + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19233 100% + system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19233 average: 1 | standard deviation: 0 | 0 19233 ] Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_demand_misses: 19427 + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_misses: 19233 + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_demand_misses: 19233 system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_LD: 61.3219% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_ST: 38.6781% + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_LD: 61.2905% + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_ST: 38.7095% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19427 100% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19427 average: 1 | standard deviation: 0 | 0 19427 ] + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19233 100% + system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19233 average: 1 | standard deviation: 0 | 0 19233 ] --- L1Cache 5 --- - Event Counts - -Load 99160 +Load 98307 Ifetch 0 -Store 53567 +Store 52894 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52471 -Other_GETS 83392 -Ack 116095 -Shared_Ack 541 -Data 284 -Shared_Data 711 -Exclusive_Data 18344 +Other_GETX 52064 +Other_GETS 83615 +Ack 114896 +Shared_Ack 571 +Data 297 +Shared_Data 704 +Exclusive_Data 18149 Writeback_Ack 0 Writeback_Nack 0 -All_acks 711 -All_acks_no_sharers 18714 +All_acks 704 +All_acks_no_sharers 18527 - Transitions - -I Load 11913 +I Load 11788 I Ifetch 0 <-- -I Store 6459 +I Store 6422 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -1413,65 +1413,65 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1245 +S Load 1309 S Ifetch 0 <-- -S Store 692 +S Store 680 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 19 -S Other_GETS 19 +S Other_GETX 24 +S Other_GETS 13 -O Load 710 +O Load 594 O Ifetch 0 <-- -O Store 363 +O Store 343 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 2 +O Other_GETX 0 <-- O Other_GETS 3 -M Load 19676 +M Load 19300 M Ifetch 0 <-- -M Store 10615 +M Store 10530 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 221 -M Other_GETS 365 +M Other_GETX 210 +M Other_GETS 343 -MM Load 65616 +MM Load 65316 MM Ifetch 0 <-- -MM Store 35438 +MM Store 34919 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6917 -MM Other_GETS 11211 +MM Other_GETX 6792 +MM Other_GETS 11182 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17699 -IM Other_GETS 27330 -IM Ack 22142 -IM Data 204 -IM Exclusive_Data 7143 +IM Other_GETX 17452 +IM Other_GETS 27344 +IM Ack 21879 +IM Data 217 +IM Exclusive_Data 7066 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 612 -SM Other_GETS 543 -SM Ack 216 +SM Other_GETX 600 +SM Other_GETS 459 +SM Ack 226 SM Data 80 OM Load 0 <-- @@ -1479,35 +1479,35 @@ OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 277 -OM Other_GETS 370 -OM Ack 602 +OM Other_GETX 262 +OM Other_GETS 323 +OM Ack 567 OM All_acks 0 <-- -OM All_acks_no_sharers 86 +OM All_acks_no_sharers 81 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 875 -ISM All_acks_no_sharers 284 +ISM Ack 939 +ISM All_acks_no_sharers 297 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33646 -M_W All_acks_no_sharers 11201 +M_W Ack 32853 +M_W All_acks_no_sharers 11083 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21329 -MM_W All_acks_no_sharers 7143 +MM_W Ack 21134 +MM_W All_acks_no_sharers 7066 IS Load 0 <-- IS Ifetch 0 <-- @@ -1515,21 +1515,21 @@ IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- IS Other_GETX 26724 -IS Other_GETS 43551 -IS Ack 35510 -IS Shared_Ack 315 +IS Other_GETS 43948 +IS Ack 35479 +IS Shared_Ack 299 IS Data 0 <-- -IS Shared_Data 711 -IS Exclusive_Data 11201 +IS Shared_Data 704 +IS Exclusive_Data 11083 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1775 -SS Shared_Ack 226 -SS All_acks 711 +SS Ack 1819 +SS Shared_Ack 272 +SS All_acks 704 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -1560,66 +1560,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_misses: 19556 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_demand_misses: 19556 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_LD: 61.2525% - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_ST: 38.7475% + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_type_LD: 61.9043% + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_type_ST: 38.0957% - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19338 100% - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19338 average: 1 | standard deviation: 0 | 0 19338 ] + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19556 100% + system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19556 average: 1 | standard deviation: 0 | 0 19556 ] Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_demand_misses: 19338 + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_misses: 19556 + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_demand_misses: 19556 system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_LD: 61.2525% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_ST: 38.7475% + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_LD: 61.9043% + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_ST: 38.0957% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19338 100% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19338 average: 1 | standard deviation: 0 | 0 19338 ] + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19556 100% + system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19556 average: 1 | standard deviation: 0 | 0 19556 ] --- L1Cache 6 --- - Event Counts - -Load 98889 +Load 100001 Ifetch 0 -Store 53165 +Store 53622 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52493 -Other_GETS 83460 -Ack 115539 -Shared_Ack 547 -Data 284 -Shared_Data 679 -Exclusive_Data 18303 +Other_GETX 52058 +Other_GETS 83297 +Ack 116891 +Shared_Ack 534 +Data 300 +Shared_Data 669 +Exclusive_Data 18491 Writeback_Ack 0 Writeback_Nack 0 -All_acks 679 -All_acks_no_sharers 18657 +All_acks 669 +All_acks_no_sharers 18886 - Transitions - -I Load 11845 +I Load 12106 I Ifetch 0 <-- -I Store 6480 +I Store 6420 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -1627,123 +1627,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1308 +S Load 1090 S Ifetch 0 <-- -S Store 654 +S Store 653 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 25 -S Other_GETS 14 +S Other_GETX 16 +S Other_GETS 11 -O Load 685 +O Load 632 O Ifetch 0 <-- -O Store 359 +O Store 377 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- -O Other_GETX 2 +O Other_GETX 0 <-- O Other_GETS 3 -M Load 19489 +M Load 20362 M Ifetch 0 <-- -M Store 10570 +M Store 10812 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 234 -M Other_GETS 361 +M Other_GETX 246 +M Other_GETS 377 -MM Load 65562 +MM Load 65811 MM Ifetch 0 <-- -MM Store 35102 +MM Store 35360 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6856 -MM Other_GETS 11206 +MM Other_GETX 7016 +MM Other_GETS 11246 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17237 -IM Other_GETS 26688 -IM Ack 21916 -IM Data 202 -IM Exclusive_Data 7138 +IM Other_GETX 16702 +IM Other_GETS 26259 +IM Ack 21931 +IM Data 211 +IM Exclusive_Data 7055 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 572 -SM Other_GETS 482 -SM Ack 248 -SM Data 82 +SM Other_GETX 564 +SM Other_GETS 502 +SM Ack 236 +SM Data 89 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 289 -OM Other_GETS 358 -OM Ack 490 +OM Other_GETX 282 +OM Other_GETS 340 +OM Ack 665 OM All_acks 0 <-- -OM All_acks_no_sharers 70 +OM All_acks_no_sharers 95 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 862 -ISM All_acks_no_sharers 284 +ISM Ack 947 +ISM All_acks_no_sharers 300 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33944 -M_W All_acks_no_sharers 11165 +M_W Ack 33907 +M_W All_acks_no_sharers 11436 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21506 -MM_W All_acks_no_sharers 7138 +MM_W Ack 21016 +MM_W All_acks_no_sharers 7055 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 27278 -IS Other_GETS 44348 -IS Ack 34795 -IS Shared_Ack 261 +IS Other_GETX 27232 +IS Other_GETS 44559 +IS Ack 36431 +IS Shared_Ack 278 IS Data 0 <-- -IS Shared_Data 679 -IS Exclusive_Data 11165 +IS Shared_Data 669 +IS Exclusive_Data 11436 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1778 -SS Shared_Ack 286 -SS All_acks 679 +SS Ack 1758 +SS Shared_Ack 256 +SS All_acks 669 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -1774,66 +1774,66 @@ II Other_GETS 0 <-- II Writeback_Ack 0 <-- II Writeback_Nack 0 <-- -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_demand_misses: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_misses: 19436 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_demand_misses: 19436 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_sw_prefetches: 0 + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_LD: 60.9852% - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_ST: 39.0148% + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_type_LD: 61.7514% + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_type_ST: 38.2486% - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19631 100% - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19631 average: 1 | standard deviation: 0 | 0 19631 ] + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_access_mode_type_SupervisorMode: 19436 100% + system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory_request_size: [binsize: 1 max: 1 count: 19436 average: 1 | standard deviation: 0 | 0 19436 ] Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_demand_misses: 19631 + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_misses: 19436 + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_demand_misses: 19436 system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_prefetches: 0 system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_sw_prefetches: 0 system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_LD: 60.9852% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_ST: 39.0148% + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_LD: 61.7514% + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_ST: 38.2486% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19631 100% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19631 average: 1 | standard deviation: 0 | 0 19631 ] + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19436 100% + system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19436 average: 1 | standard deviation: 0 | 0 19436 ] --- L1Cache 7 --- - Event Counts - -Load 100001 +Load 99390 Ifetch 0 -Store 54267 +Store 53487 L2_Replacement 0 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 -Other_GETX 52326 -Other_GETS 83333 -Ack 117318 -Shared_Ack 553 -Data 310 -Shared_Data 736 -Exclusive_Data 18493 +Other_GETX 52075 +Other_GETS 83401 +Ack 116123 +Shared_Ack 552 +Data 278 +Shared_Data 688 +Exclusive_Data 18397 Writeback_Ack 0 Writeback_Nack 0 -All_acks 736 -All_acks_no_sharers 18894 +All_acks 688 +All_acks_no_sharers 18746 - Transitions - -I Load 11972 +I Load 12002 I Ifetch 0 <-- -I Store 6579 +I Store 6376 I L2_Replacement 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- @@ -1841,123 +1841,123 @@ I L2_to_L1I 0 <-- I Other_GETX 0 <-- I Other_GETS 0 <-- -S Load 1355 +S Load 1285 S Ifetch 0 <-- -S Store 716 +S Store 672 S L2_Replacement 0 <-- S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- -S Other_GETX 20 -S Other_GETS 14 +S Other_GETX 16 +S Other_GETS 26 -O Load 691 +O Load 736 O Ifetch 0 <-- -O Store 364 +O Store 386 O L2_Replacement 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- O Other_GETX 2 -O Other_GETS 3 +O Other_GETS 2 -M Load 19829 +M Load 19905 M Ifetch 0 <-- -M Store 10657 +M Store 10715 M L2_Replacement 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 366 +M Other_GETX 210 +M Other_GETS 388 -MM Load 66154 +MM Load 65462 MM Ifetch 0 <-- -MM Store 35951 +MM Store 35338 MM L2_Replacement 0 <-- MM L1_to_L2 0 <-- MM L2_to_L1D 0 <-- MM L2_to_L1I 0 <-- -MM Other_GETX 6984 -MM Other_GETS 11331 +MM Other_GETX 6877 +MM Other_GETS 11271 IM Load 0 <-- IM Ifetch 0 <-- IM Store 0 <-- IM L2_Replacement 0 <-- IM L1_to_L2 0 <-- -IM Other_GETX 17532 -IM Other_GETS 27148 -IM Ack 22400 -IM Data 215 -IM Exclusive_Data 7258 +IM Other_GETX 17167 +IM Other_GETS 26381 +IM Ack 21891 +IM Data 204 +IM Exclusive_Data 7084 SM Load 0 <-- SM Ifetch 0 <-- SM Store 0 <-- SM L2_Replacement 0 <-- SM L1_to_L2 0 <-- -SM Other_GETX 621 -SM Other_GETS 571 -SM Ack 271 -SM Data 95 +SM Other_GETX 598 +SM Other_GETS 486 +SM Ack 234 +SM Data 74 OM Load 0 <-- OM Ifetch 0 <-- OM Store 0 <-- OM L2_Replacement 0 <-- OM L1_to_L2 0 <-- -OM Other_GETX 273 -OM Other_GETS 352 -OM Ack 637 +OM Other_GETX 315 +OM Other_GETS 342 +OM Ack 497 OM All_acks 0 <-- -OM All_acks_no_sharers 91 +OM All_acks_no_sharers 71 ISM Load 0 <-- ISM Ifetch 0 <-- ISM Store 0 <-- ISM L2_Replacement 0 <-- ISM L1_to_L2 0 <-- -ISM Ack 950 -ISM All_acks_no_sharers 310 +ISM Ack 785 +ISM All_acks_no_sharers 278 M_W Load 0 <-- M_W Ifetch 0 <-- M_W Store 0 <-- M_W L2_Replacement 0 <-- M_W L1_to_L2 0 <-- -M_W Ack 33772 -M_W All_acks_no_sharers 11235 +M_W Ack 33978 +M_W All_acks_no_sharers 11313 MM_W Load 0 <-- MM_W Ifetch 0 <-- MM_W Store 0 <-- MM_W L2_Replacement 0 <-- MM_W L1_to_L2 0 <-- -MM_W Ack 21787 -MM_W All_acks_no_sharers 7258 +MM_W Ack 21262 +MM_W All_acks_no_sharers 7084 IS Load 0 <-- IS Ifetch 0 <-- IS Store 0 <-- IS L2_Replacement 0 <-- IS L1_to_L2 0 <-- -IS Other_GETX 26682 -IS Other_GETS 43548 -IS Ack 35649 +IS Other_GETX 26890 +IS Other_GETS 44505 +IS Ack 35618 IS Shared_Ack 274 IS Data 0 <-- -IS Shared_Data 736 -IS Exclusive_Data 11235 +IS Shared_Data 688 +IS Exclusive_Data 11313 SS Load 0 <-- SS Ifetch 0 <-- SS Store 0 <-- SS L2_Replacement 0 <-- SS L1_to_L2 0 <-- -SS Ack 1852 -SS Shared_Ack 279 -SS All_acks 736 +SS Ack 1858 +SS Shared_Ack 278 +SS All_acks 688 SS All_acks_no_sharers 0 <-- OI Load 0 <-- @@ -2010,10 +2010,10 @@ Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: --- Directory 0 --- - Event Counts - -GETX 2262622 -GETS 3542851 +GETX 2249313 +GETS 3541903 PUT 0 -Unblock 155288 +Unblock 154908 Writeback_Clean 0 Writeback_Dirty 0 Writeback_Exclusive_Clean 0 @@ -2030,8 +2030,8 @@ All_acks_and_data 0 All_acks_and_data_no_sharers 0 - Transitions - -NO GETX 59984 -NO GETS 95304 +NO GETX 59507 +NO GETS 95401 NO PUT 0 <-- NO DMA_READ 0 <-- NO DMA_WRITE 0 <-- @@ -2042,16 +2042,16 @@ O PUT 0 <-- O DMA_READ 0 <-- O DMA_WRITE 0 <-- -E GETX 2 -E GETS 0 <-- +E GETX 1 +E GETS 1 E PUT 0 <-- E DMA_READ 0 <-- E DMA_WRITE 0 <-- -NO_B GETX 2202461 -NO_B GETS 3447311 +NO_B GETX 2189606 +NO_B GETS 3446289 NO_B PUT 0 <-- -NO_B Unblock 155288 +NO_B Unblock 154908 NO_B DMA_READ 0 <-- NO_B DMA_WRITE 0 <-- @@ -2062,8 +2062,8 @@ O_B Unblock 0 <-- O_B DMA_READ 0 <-- O_B DMA_WRITE 0 <-- -NO_B_W GETX 175 -NO_B_W GETS 236 +NO_B_W GETX 199 +NO_B_W GETS 212 NO_B_W PUT 0 <-- NO_B_W Unblock 0 <-- NO_B_W DMA_READ 0 <-- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 21ce47f84..4ad631c35 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,74 @@ -system.cpu0: completed 10000 read accesses @427647 -system.cpu1: completed 10000 read accesses @431729 -system.cpu6: completed 10000 read accesses @433789 -system.cpu7: completed 10000 read accesses @439540 -system.cpu2: completed 10000 read accesses @440839 -system.cpu5: completed 10000 read accesses @442985 -system.cpu4: completed 10000 read accesses @444200 -system.cpu3: completed 10000 read accesses @449590 -system.cpu0: completed 20000 read accesses @865314 -system.cpu6: completed 20000 read accesses @868247 -system.cpu1: completed 20000 read accesses @868279 -system.cpu4: completed 20000 read accesses @868705 -system.cpu7: completed 20000 read accesses @876211 -system.cpu3: completed 20000 read accesses @884081 -system.cpu2: completed 20000 read accesses @890953 -system.cpu5: completed 20000 read accesses @896667 -system.cpu7: completed 30000 read accesses @1294509 -system.cpu0: completed 30000 read accesses @1300229 -system.cpu4: completed 30000 read accesses @1308389 -system.cpu6: completed 30000 read accesses @1309605 -system.cpu1: completed 30000 read accesses @1314626 -system.cpu2: completed 30000 read accesses @1319614 -system.cpu3: completed 30000 read accesses @1333112 -system.cpu5: completed 30000 read accesses @1342297 -system.cpu0: completed 40000 read accesses @1732725 -system.cpu7: completed 40000 read accesses @1734274 -system.cpu6: completed 40000 read accesses @1739223 -system.cpu4: completed 40000 read accesses @1750291 -system.cpu2: completed 40000 read accesses @1757823 -system.cpu1: completed 40000 read accesses @1760314 -system.cpu3: completed 40000 read accesses @1761490 -system.cpu5: completed 40000 read accesses @1777684 -system.cpu7: completed 50000 read accesses @2168908 -system.cpu0: completed 50000 read accesses @2178119 -system.cpu3: completed 50000 read accesses @2188628 -system.cpu1: completed 50000 read accesses @2189157 -system.cpu6: completed 50000 read accesses @2193920 -system.cpu2: completed 50000 read accesses @2194930 -system.cpu4: completed 50000 read accesses @2196927 -system.cpu5: completed 50000 read accesses @2215126 -system.cpu7: completed 60000 read accesses @2604948 -system.cpu0: completed 60000 read accesses @2616657 -system.cpu4: completed 60000 read accesses @2617534 -system.cpu1: completed 60000 read accesses @2632147 -system.cpu6: completed 60000 read accesses @2638426 -system.cpu3: completed 60000 read accesses @2639965 -system.cpu2: completed 60000 read accesses @2642221 -system.cpu5: completed 60000 read accesses @2647795 -system.cpu7: completed 70000 read accesses @3047214 -system.cpu0: completed 70000 read accesses @3049033 -system.cpu4: completed 70000 read accesses @3063601 -system.cpu1: completed 70000 read accesses @3069586 -system.cpu2: completed 70000 read accesses @3071644 -system.cpu3: completed 70000 read accesses @3075127 -system.cpu6: completed 70000 read accesses @3078550 -system.cpu5: completed 70000 read accesses @3088269 -system.cpu7: completed 80000 read accesses @3486517 -system.cpu0: completed 80000 read accesses @3492714 -system.cpu4: completed 80000 read accesses @3505717 -system.cpu2: completed 80000 read accesses @3505856 -system.cpu3: completed 80000 read accesses @3506369 -system.cpu1: completed 80000 read accesses @3507148 -system.cpu6: completed 80000 read accesses @3520617 -system.cpu5: completed 80000 read accesses @3524191 -system.cpu7: completed 90000 read accesses @3917341 -system.cpu0: completed 90000 read accesses @3926523 -system.cpu4: completed 90000 read accesses @3938478 -system.cpu1: completed 90000 read accesses @3940606 -system.cpu5: completed 90000 read accesses @3950826 -system.cpu3: completed 90000 read accesses @3954179 -system.cpu6: completed 90000 read accesses @3956200 -system.cpu2: completed 90000 read accesses @3961428 -system.cpu7: completed 100000 read accesses @4339943 +system.cpu5: completed 10000 read accesses @427588 +system.cpu7: completed 10000 read accesses @431412 +system.cpu2: completed 10000 read accesses @431662 +system.cpu0: completed 10000 read accesses @436404 +system.cpu6: completed 10000 read accesses @437826 +system.cpu3: completed 10000 read accesses @441295 +system.cpu4: completed 10000 read accesses @446537 +system.cpu1: completed 10000 read accesses @454121 +system.cpu6: completed 20000 read accesses @860243 +system.cpu5: completed 20000 read accesses @863931 +system.cpu0: completed 20000 read accesses @870865 +system.cpu7: completed 20000 read accesses @874151 +system.cpu2: completed 20000 read accesses @878670 +system.cpu1: completed 20000 read accesses @880979 +system.cpu3: completed 20000 read accesses @881568 +system.cpu4: completed 20000 read accesses @885967 +system.cpu6: completed 30000 read accesses @1296805 +system.cpu7: completed 30000 read accesses @1298533 +system.cpu0: completed 30000 read accesses @1301793 +system.cpu5: completed 30000 read accesses @1305764 +system.cpu3: completed 30000 read accesses @1313209 +system.cpu1: completed 30000 read accesses @1317956 +system.cpu4: completed 30000 read accesses @1322397 +system.cpu2: completed 30000 read accesses @1327680 +system.cpu7: completed 40000 read accesses @1724327 +system.cpu6: completed 40000 read accesses @1741883 +system.cpu3: completed 40000 read accesses @1743341 +system.cpu0: completed 40000 read accesses @1746338 +system.cpu5: completed 40000 read accesses @1749918 +system.cpu4: completed 40000 read accesses @1756944 +system.cpu1: completed 40000 read accesses @1758785 +system.cpu2: completed 40000 read accesses @1766923 +system.cpu7: completed 50000 read accesses @2153101 +system.cpu3: completed 50000 read accesses @2174455 +system.cpu6: completed 50000 read accesses @2175676 +system.cpu0: completed 50000 read accesses @2176642 +system.cpu1: completed 50000 read accesses @2195626 +system.cpu5: completed 50000 read accesses @2196192 +system.cpu4: completed 50000 read accesses @2206329 +system.cpu2: completed 50000 read accesses @2212172 +system.cpu7: completed 60000 read accesses @2597994 +system.cpu3: completed 60000 read accesses @2607264 +system.cpu6: completed 60000 read accesses @2608871 +system.cpu0: completed 60000 read accesses @2617931 +system.cpu1: completed 60000 read accesses @2626417 +system.cpu5: completed 60000 read accesses @2627919 +system.cpu2: completed 60000 read accesses @2649345 +system.cpu4: completed 60000 read accesses @2649516 +system.cpu7: completed 70000 read accesses @3041950 +system.cpu6: completed 70000 read accesses @3046421 +system.cpu3: completed 70000 read accesses @3055853 +system.cpu0: completed 70000 read accesses @3057789 +system.cpu1: completed 70000 read accesses @3060703 +system.cpu5: completed 70000 read accesses @3069601 +system.cpu4: completed 70000 read accesses @3076345 +system.cpu2: completed 70000 read accesses @3079487 +system.cpu7: completed 80000 read accesses @3472996 +system.cpu6: completed 80000 read accesses @3475066 +system.cpu3: completed 80000 read accesses @3481511 +system.cpu0: completed 80000 read accesses @3498566 +system.cpu1: completed 80000 read accesses @3506662 +system.cpu2: completed 80000 read accesses @3515589 +system.cpu5: completed 80000 read accesses @3522207 +system.cpu4: completed 80000 read accesses @3524696 +system.cpu6: completed 90000 read accesses @3905962 +system.cpu7: completed 90000 read accesses @3913222 +system.cpu3: completed 90000 read accesses @3920060 +system.cpu0: completed 90000 read accesses @3930216 +system.cpu2: completed 90000 read accesses @3948853 +system.cpu1: completed 90000 read accesses @3953559 +system.cpu5: completed 90000 read accesses @3960654 +system.cpu4: completed 90000 read accesses @3965634 +system.cpu6: completed 100000 read accesses @4329426 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 3061eb9aa..419882138 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2010 14:59:19 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:40:34 -M5 executing on cabr0210 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer +M5 compiled Jul 1 2010 14:37:50 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:38:54 +M5 executing on phenom +command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4339943 because maximum number of loads reached +Exiting @ tick 4329426 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index d9440348d..3f6218f25 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 339964 # Number of bytes of host memory used -host_seconds 41.43 # Real time elapsed on the host -host_tick_rate 104755 # Simulator tick rate (ticks/s) +host_mem_usage 332624 # Number of bytes of host memory used +host_seconds 32.19 # Real time elapsed on the host +host_tick_rate 134514 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.004340 # Number of seconds simulated -sim_ticks 4339943 # Number of ticks simulated +sim_seconds 0.004329 # Number of seconds simulated +sim_ticks 4329426 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99313 # number of read accesses completed -system.cpu0.num_writes 53538 # number of write accesses completed +system.cpu0.num_reads 99342 # number of read accesses completed +system.cpu0.num_writes 53020 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99089 # number of read accesses completed -system.cpu1.num_writes 53648 # number of write accesses completed +system.cpu1.num_reads 98745 # number of read accesses completed +system.cpu1.num_writes 53384 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98494 # number of read accesses completed -system.cpu2.num_writes 52751 # number of write accesses completed +system.cpu2.num_reads 98624 # number of read accesses completed +system.cpu2.num_writes 53313 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98499 # number of read accesses completed -system.cpu3.num_writes 53164 # number of write accesses completed +system.cpu3.num_reads 99274 # number of read accesses completed +system.cpu3.num_writes 53327 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99037 # number of read accesses completed -system.cpu4.num_writes 53407 # number of write accesses completed +system.cpu4.num_reads 98083 # number of read accesses completed +system.cpu4.num_writes 52520 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99159 # number of read accesses completed -system.cpu5.num_writes 53566 # number of write accesses completed +system.cpu5.num_reads 98306 # number of read accesses completed +system.cpu5.num_writes 52893 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98888 # number of read accesses completed -system.cpu6.num_writes 53164 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53622 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 54267 # number of write accesses completed +system.cpu7.num_reads 99389 # number of read accesses completed +system.cpu7.num_writes 53486 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr index b09f497b8..76b354de5 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu3: completed 10000 read accesses @26226880 -system.cpu6: completed 10000 read accesses @26416342 -system.cpu2: completed 10000 read accesses @26427251 -system.cpu5: completed 10000 read accesses @26798889 -system.cpu0: completed 10000 read accesses @26886521 +system.cpu4: completed 10000 read accesses @26226880 +system.cpu0: completed 10000 read accesses @26416342 +system.cpu3: completed 10000 read accesses @26427251 +system.cpu2: completed 10000 read accesses @26798889 +system.cpu5: completed 10000 read accesses @26886521 system.cpu7: completed 10000 read accesses @27109446 -system.cpu1: completed 10000 read accesses @27197408 -system.cpu4: completed 10000 read accesses @27318359 -system.cpu3: completed 20000 read accesses @53279230 -system.cpu6: completed 20000 read accesses @53417084 -system.cpu2: completed 20000 read accesses @53757092 -system.cpu0: completed 20000 read accesses @53888320 -system.cpu5: completed 20000 read accesses @53947132 -system.cpu4: completed 20000 read accesses @54390092 -system.cpu1: completed 20000 read accesses @54397720 +system.cpu6: completed 10000 read accesses @27197408 +system.cpu1: completed 10000 read accesses @27318359 +system.cpu4: completed 20000 read accesses @53279230 +system.cpu0: completed 20000 read accesses @53417084 +system.cpu3: completed 20000 read accesses @53757092 +system.cpu5: completed 20000 read accesses @53888320 +system.cpu2: completed 20000 read accesses @53947132 +system.cpu1: completed 20000 read accesses @54390092 +system.cpu6: completed 20000 read accesses @54397720 system.cpu7: completed 20000 read accesses @54632966 -system.cpu6: completed 30000 read accesses @80144176 -system.cpu3: completed 30000 read accesses @80518264 -system.cpu0: completed 30000 read accesses @80638600 -system.cpu5: completed 30000 read accesses @80869702 -system.cpu1: completed 30000 read accesses @81289158 -system.cpu2: completed 30000 read accesses @81358716 +system.cpu0: completed 30000 read accesses @80144176 +system.cpu4: completed 30000 read accesses @80518264 +system.cpu5: completed 30000 read accesses @80638600 +system.cpu2: completed 30000 read accesses @80869702 +system.cpu6: completed 30000 read accesses @81289158 +system.cpu3: completed 30000 read accesses @81358716 system.cpu7: completed 30000 read accesses @81981296 -system.cpu4: completed 30000 read accesses @82043104 -system.cpu6: completed 40000 read accesses @107087547 -system.cpu0: completed 40000 read accesses @107662142 -system.cpu3: completed 40000 read accesses @107722516 -system.cpu5: completed 40000 read accesses @107884124 -system.cpu1: completed 40000 read accesses @107981413 +system.cpu1: completed 30000 read accesses @82043104 +system.cpu0: completed 40000 read accesses @107087547 +system.cpu5: completed 40000 read accesses @107662142 +system.cpu4: completed 40000 read accesses @107722516 +system.cpu2: completed 40000 read accesses @107884124 +system.cpu6: completed 40000 read accesses @107981413 system.cpu7: completed 40000 read accesses @108415286 -system.cpu2: completed 40000 read accesses @108655120 -system.cpu4: completed 40000 read accesses @109427858 -system.cpu6: completed 50000 read accesses @133583246 -system.cpu0: completed 50000 read accesses @133832383 -system.cpu5: completed 50000 read accesses @134755386 -system.cpu1: completed 50000 read accesses @134792594 +system.cpu3: completed 40000 read accesses @108655120 +system.cpu1: completed 40000 read accesses @109427858 +system.cpu0: completed 50000 read accesses @133583246 +system.cpu5: completed 50000 read accesses @133832383 +system.cpu2: completed 50000 read accesses @134755386 +system.cpu6: completed 50000 read accesses @134792594 system.cpu7: completed 50000 read accesses @134914312 -system.cpu3: completed 50000 read accesses @134993978 -system.cpu2: completed 50000 read accesses @135362549 -system.cpu4: completed 50000 read accesses @135394370 -system.cpu0: completed 60000 read accesses @160410176 -system.cpu6: completed 60000 read accesses @160667590 +system.cpu4: completed 50000 read accesses @134993978 +system.cpu3: completed 50000 read accesses @135362549 +system.cpu1: completed 50000 read accesses @135394370 +system.cpu5: completed 60000 read accesses @160410176 +system.cpu0: completed 60000 read accesses @160667590 system.cpu7: completed 60000 read accesses @161466346 -system.cpu1: completed 60000 read accesses @161592434 -system.cpu5: completed 60000 read accesses @161656374 -system.cpu4: completed 60000 read accesses @161882626 -system.cpu2: completed 60000 read accesses @162062631 -system.cpu3: completed 60000 read accesses @162154299 -system.cpu6: completed 70000 read accesses @187592265 -system.cpu1: completed 70000 read accesses @188138542 +system.cpu6: completed 60000 read accesses @161592434 +system.cpu2: completed 60000 read accesses @161656374 +system.cpu1: completed 60000 read accesses @161882626 +system.cpu3: completed 60000 read accesses @162062631 +system.cpu4: completed 60000 read accesses @162154299 +system.cpu0: completed 70000 read accesses @187592265 +system.cpu6: completed 70000 read accesses @188138542 system.cpu7: completed 70000 read accesses @188373105 -system.cpu0: completed 70000 read accesses @188690782 -system.cpu3: completed 70000 read accesses @189309687 -system.cpu2: completed 70000 read accesses @189360790 -system.cpu4: completed 70000 read accesses @189391126 -system.cpu5: completed 70000 read accesses @189902895 -system.cpu6: completed 80000 read accesses @214739574 -system.cpu1: completed 80000 read accesses @215665444 -system.cpu0: completed 80000 read accesses @216021457 +system.cpu5: completed 70000 read accesses @188690782 +system.cpu4: completed 70000 read accesses @189309687 +system.cpu3: completed 70000 read accesses @189360790 +system.cpu1: completed 70000 read accesses @189391126 +system.cpu2: completed 70000 read accesses @189902895 +system.cpu0: completed 80000 read accesses @214739574 +system.cpu6: completed 80000 read accesses @215665444 +system.cpu5: completed 80000 read accesses @216021457 system.cpu7: completed 80000 read accesses @216394344 -system.cpu3: completed 80000 read accesses @216537382 -system.cpu4: completed 80000 read accesses @216775798 -system.cpu2: completed 80000 read accesses @216868662 -system.cpu5: completed 80000 read accesses @217401619 -system.cpu6: completed 90000 read accesses @241415090 -system.cpu1: completed 90000 read accesses @242558992 -system.cpu0: completed 90000 read accesses @242897388 +system.cpu4: completed 80000 read accesses @216537382 +system.cpu1: completed 80000 read accesses @216775798 +system.cpu3: completed 80000 read accesses @216868662 +system.cpu2: completed 80000 read accesses @217401619 +system.cpu0: completed 90000 read accesses @241415090 +system.cpu6: completed 90000 read accesses @242558992 +system.cpu5: completed 90000 read accesses @242897388 system.cpu7: completed 90000 read accesses @243372191 -system.cpu3: completed 90000 read accesses @243630762 -system.cpu5: completed 90000 read accesses @243633950 -system.cpu4: completed 90000 read accesses @243710816 -system.cpu2: completed 90000 read accesses @243974160 -system.cpu6: completed 100000 read accesses @268915439 +system.cpu4: completed 90000 read accesses @243630762 +system.cpu2: completed 90000 read accesses @243633950 +system.cpu1: completed 90000 read accesses @243710816 +system.cpu3: completed 90000 read accesses @243974160 +system.cpu0: completed 100000 read accesses @268915439 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index ae0afe01d..d2f584939 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:22:18 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest +M5 compiled Jul 1 2010 14:37:40 +M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate +M5 started Jul 1 2010 14:37:50 +M5 executing on phenom +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 268915439 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 7eeff6062..b7210d154 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,529 +1,529 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 316880 # Number of bytes of host memory used -host_seconds 287.16 # Real time elapsed on the host -host_tick_rate 936456 # Simulator tick rate (ticks/s) +host_mem_usage 318132 # Number of bytes of host memory used +host_seconds 165.43 # Real time elapsed on the host +host_tick_rate 1625594 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7473 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37586 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23387 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. -system.cpu0.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.403583 # Average number of references to valid blocks. +system.cpu0.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 69369 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8396 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60973 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy -system.cpu0.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy -system.cpu0.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context -system.cpu0.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context -system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy +system.cpu0.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy +system.cpu0.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context +system.cpu0.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context +system.cpu0.l1c.overall_accesses 69369 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8674 # number of overall hits -system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60767 # number of overall misses +system.cpu0.l1c.overall_hits 8396 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2453091767 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60973 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60973 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.replacements 28158 # number of replacements -system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 28139 # number of replacements +system.cpu0.l1c.sampled_refs 28470 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 343.673683 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11490 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11054 # number of writebacks +system.cpu0.l1c.writebacks 11130 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99578 # number of read accesses completed -system.cpu0.num_writes 53795 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54239 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37225 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 973 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. -system.cpu1.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.411354 # Average number of references to valid blocks. +system.cpu1.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68853 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8435 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60418 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy -system.cpu1.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy -system.cpu1.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context -system.cpu1.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context -system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy +system.cpu1.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy +system.cpu1.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context +system.cpu1.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context +system.cpu1.l1c.overall_accesses 68853 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8551 # number of overall hits -system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60450 # number of overall misses +system.cpu1.l1c.overall_hits 8435 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2449625152 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60418 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60418 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.replacements 27563 # number of replacements -system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27721 # number of replacements +system.cpu1.l1c.sampled_refs 28078 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 344.718702 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11550 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10923 # number of writebacks +system.cpu1.l1c.writebacks 10846 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99680 # number of read accesses completed -system.cpu1.num_writes 54175 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency +system.cpu1.num_reads 99301 # number of read accesses completed +system.cpu1.num_writes 53586 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7472 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37075 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23395 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. -system.cpu2.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.410620 # Average number of references to valid blocks. +system.cpu2.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68832 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8362 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60470 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy -system.cpu2.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy -system.cpu2.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context -system.cpu2.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context -system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy +system.cpu2.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy +system.cpu2.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context +system.cpu2.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context +system.cpu2.l1c.overall_accesses 68832 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8437 # number of overall hits -system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60562 # number of overall misses +system.cpu2.l1c.overall_hits 8362 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2452523238 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60470 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60470 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.replacements 27725 # number of replacements -system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27632 # number of replacements +system.cpu2.l1c.sampled_refs 27965 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 343.014216 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11483 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10868 # number of writebacks +system.cpu2.l1c.writebacks 10950 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99153 # number of read accesses completed -system.cpu2.num_writes 52976 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency +system.cpu2.num_reads 99024 # number of read accesses completed +system.cpu2.num_writes 53903 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7547 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37391 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 890 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23171 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. -system.cpu3.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.410349 # Average number of references to valid blocks. +system.cpu3.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68999 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8437 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60562 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy -system.cpu3.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy -system.cpu3.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context -system.cpu3.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context -system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy +system.cpu3.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy +system.cpu3.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context +system.cpu3.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context +system.cpu3.l1c.overall_accesses 68999 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8535 # number of overall hits -system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60533 # number of overall misses +system.cpu3.l1c.overall_hits 8437 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2458156635 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60562 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60562 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.replacements 27562 # number of replacements -system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27725 # number of replacements +system.cpu3.l1c.sampled_refs 28081 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 346.450009 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11523 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10850 # number of writebacks +system.cpu3.l1c.writebacks 10868 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99282 # number of read accesses completed -system.cpu3.num_writes 53764 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency +system.cpu3.num_reads 99153 # number of read accesses completed +system.cpu3.num_writes 52976 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7629 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37136 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 906 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23397 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. -system.cpu4.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.418843 # Average number of references to valid blocks. +system.cpu4.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69068 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8535 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60533 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy -system.cpu4.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy -system.cpu4.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context -system.cpu4.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context -system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy +system.cpu4.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy +system.cpu4.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context +system.cpu4.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context +system.cpu4.l1c.overall_accesses 69068 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8435 # number of overall hits -system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60418 # number of overall misses +system.cpu4.l1c.overall_hits 8535 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2459294321 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60533 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60533 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.replacements 27721 # number of replacements -system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27562 # number of replacements +system.cpu4.l1c.sampled_refs 27915 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 345.337496 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11692 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10846 # number of writebacks +system.cpu4.l1c.writebacks 10850 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99301 # number of read accesses completed -system.cpu4.num_writes 53586 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency +system.cpu4.num_reads 99282 # number of read accesses completed +system.cpu4.num_writes 53764 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7762 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37405 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 912 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23362 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. -system.cpu5.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.412252 # Average number of references to valid blocks. +system.cpu5.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69441 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8674 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60767 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy -system.cpu5.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy -system.cpu5.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context -system.cpu5.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context -system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy +system.cpu5.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy +system.cpu5.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context +system.cpu5.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context +system.cpu5.l1c.overall_accesses 69441 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8362 # number of overall hits -system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60470 # number of overall misses +system.cpu5.l1c.overall_hits 8674 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2449640896 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60767 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60767 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.replacements 27632 # number of replacements -system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 28158 # number of replacements +system.cpu5.l1c.sampled_refs 28502 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 346.020042 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11750 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10950 # number of writebacks +system.cpu5.l1c.writebacks 11054 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99024 # number of read accesses completed -system.cpu5.num_writes 53903 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency +system.cpu5.num_reads 99578 # number of read accesses completed +system.cpu5.num_writes 53795 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7617 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37080 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 934 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23370 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. -system.cpu6.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.415709 # Average number of references to valid blocks. +system.cpu6.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 69001 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8551 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60450 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy -system.cpu6.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy -system.cpu6.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context -system.cpu6.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context -system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy +system.cpu6.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy +system.cpu6.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context +system.cpu6.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context +system.cpu6.l1c.overall_accesses 69001 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8396 # number of overall hits -system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60973 # number of overall misses +system.cpu6.l1c.overall_hits 8551 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2447852326 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60450 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60450 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.replacements 28139 # number of replacements -system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27563 # number of replacements +system.cpu6.l1c.sampled_refs 27921 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 342.745179 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11607 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11130 # number of writebacks +system.cpu6.l1c.writebacks 10923 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 54239 # number of write accesses completed +system.cpu6.num_reads 99680 # number of read accesses completed +system.cpu6.num_writes 54175 # number of write accesses completed system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency |