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authorKevin Lim <ktlim@umich.edu>2006-10-31 14:37:19 -0500
committerKevin Lim <ktlim@umich.edu>2006-10-31 14:37:19 -0500
commit5825a6c9d82b813d983b688da5f1ce18c90f774f (patch)
treea5be1a1c3968ff57d387523f95e46bcb2797c121 /tests
parent7f39644609e19ada9e94c9bbb09c3e625fa6e8ed (diff)
parentbfd5eb2b08dad700d085a637d5e16a61dcc530d7 (diff)
downloadgem5-5825a6c9d82b813d983b688da5f1ce18c90f774f.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix configs/example/fs.py: configs/example/se.py: src/mem/tport.hh: Hand merge. --HG-- extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/o3-timing-mp.py1
-rw-r--r--tests/configs/o3-timing.py1
-rw-r--r--tests/configs/simple-atomic-mp.py1
-rw-r--r--tests/configs/simple-atomic.py1
-rw-r--r--tests/configs/simple-timing-mp.py1
-rw-r--r--tests/configs/simple-timing.py2
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py1
-rw-r--r--tests/configs/tsunami-simple-atomic.py1
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py1
-rw-r--r--tests/configs/tsunami-simple-timing.py1
10 files changed, 0 insertions, 11 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 68631b3d2..331e2c569 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -71,7 +71,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
- cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 0dd7be506..a66cd436e 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -40,7 +40,6 @@ class MyCache(BaseCache):
cpu = DerivO3CPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index eaa6ec66e..f9e4e2767 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
- cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index d35ac4ae0..a8a876994 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,6 +34,5 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
root = Root(system = system)
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 8f9ab0dde..0d99d8714 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
- cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 60190b47c..d7d505a5a 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,8 +39,6 @@ class MyCache(BaseCache):
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
-cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 1e6c10243..4adb32868 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
- c.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 623d285e4..653df9bb0 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -35,6 +35,5 @@ cpu = AtomicSimpleCPU(cpu_id=0)
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
-cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 516495d18..bfd478969 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
- c.mem = system.physmem
root = Root(clock = '2GHz', system = system)
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 2edf5ac32..59401c040 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -35,6 +35,5 @@ cpu = TimingSimpleCPU(cpu_id=0)
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
-cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)