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authorRon Dreslinski <rdreslin@umich.edu>2006-08-21 13:20:35 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-08-21 13:20:35 -0400
commit689eb39d4862df05dacb5030494000230dcfb5a7 (patch)
treee89869aba948c740a27629d12ea609b7235d7d1f /tests
parent21b21c63b02456276ebf3b49d61dc42156a20b8e (diff)
parent825a7aadd24493e4cdf9590434134a31a8548cbe (diff)
downloadgem5-689eb39d4862df05dacb5030494000230dcfb5a7.tar.xz
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem src/python/m5/objects/BaseCPU.py: Merge duplicate change --HG-- extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/simple-timing.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 9a5b20e88..7bb76db0e 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -40,7 +40,7 @@ cpu = TimingSimpleCPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
cpu.mem = cpu.dcache
-
+cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())