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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:39 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:39 -0400
commite8b7df072b17bfd86b294fc47cf29d3d013f646a (patch)
tree59013427454f915059addd33967b774f7edfeaa0 /tests
parentd71b95d84d5aac6926f6cd4c7faca20f2c43d8dc (diff)
downloadgem5-e8b7df072b17bfd86b294fc47cf29d3d013f646a.tar.xz
inorder: make InOrder CPU FS compilable/visible
make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile
Diffstat (limited to 'tests')
-rw-r--r--tests/SConscript3
-rw-r--r--tests/configs/tsunami-inorder.py103
2 files changed, 105 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript
index 00ceebdec..2316d9092 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -270,7 +270,8 @@ if env['FULL_SYSTEM']:
'tsunami-simple-atomic-dual',
'tsunami-simple-timing-dual',
'twosys-tsunami-simple-atomic',
- 'tsunami-o3', 'tsunami-o3-dual']
+ 'tsunami-o3', 'tsunami-o3-dual',
+ 'tsunami-inorder']
if env['TARGET_ISA'] == 'sparc':
configs += ['t1000-simple-atomic',
't1000-simple-timing']
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
new file mode 100644
index 000000000..fd62e252a
--- /dev/null
+++ b/tests/configs/tsunami-inorder.py
@@ -0,0 +1,103 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='8GB')
+ forward_snoops = False
+ is_top_level = True
+
+#cpu
+cpu = InOrderCPU(cpu_id=0)
+cpu.stageWidth = 4
+cpu.fetchBuffSize = 1
+
+#the system
+system = FSConfig.makeLinuxAlphaSystem('timing')
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+