SE/FS: Make SE vs. FS mode a runtime parameter.

33 files changed, 33 insertions, 33 deletions

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 1bab83609..2a87cb663 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 2517e7670..6d0f8aa86 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -117,7 +117,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 66e49a63e..c1358eecd 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b14f0e5b1..2f8829db0 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 67aaebd21..9436cf88a 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -86,7 +86,7 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 07851ae9f..b967a5080 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,4 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 395fd24a3..9701b1012 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0fe23d1ee..f3b8e700f 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index eeff17069..62c7c7bd4 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index a1b2f4676..cbfda22a2 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 69c583abd..adab96fcb 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index bab5a193d..f466bc480 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index edfd940ad..5baa3c91a 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 83f85641a..f1de86411 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 7fe0d409b..81646f825 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 90f2539e6..8d1840571 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index a7e598b0a..0fffe1aa2 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -112,7 +112,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 705f13ef3..fe0311801 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index e722ef334..db0c0b9c0 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -85,5 +85,5 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 191230164..eb7415b8d 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e1..63d5291b9 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -95,7 +95,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f1ebb1939..c82ef0a26 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 319dd3b55..2324c196b 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -91,7 +91,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cc0d1d207..19b40fe48 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system=False, system = system)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index ae2c59110..217135bf0 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index a08261533..dc30633b3 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index c63637f73..1680be166 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -95,6 +95,6 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index a6bb4b122..accf350b3 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 758dbef09..9a29f5c65 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -93,5 +93,5 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index a2335d763..897b1c946 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index ad466a5c0..6b78b71f4 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -93,7 +93,7 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
 
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 7dc0ded5c..e3a764e16 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 658508fa0..d32e5dd87 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
 drive_sys.iobridge.slave = drive_sys.iobus.port
 drive_sys.iobridge.master = drive_sys.membus.port
 
-root = makeDualRoot(test_sys, drive_sys, "ethertrace")
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999