config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings.  This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
   caches children of the sequencer rather than the controller; these
   config ciles are rewritten to assign the L1 caches to the
   controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
   causes the sequencers to be children of system.ruby, generating
   warnings because they are already parented to their respective
   controllers.  Changing this attribute to _cpu_ruby_ports fixes this
   because the leading underscore means this is now treated as a plain
   Python attribute rather than a child assignment. As a result, the
   configuration hierarchy changes such that, e.g.,
   system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
   internal link node rather than direct children of the topology.
   The topology classes are rewritten to assign the routers to the
   topology object first.

4 files changed, 10 insertions, 10 deletions

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index eb7a280f4..8e66c7334 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -87,9 +87,9 @@ system = System(cpu = cpus,
 
 system.ruby = Ruby.create_system(options, system)
 
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
 
-for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
+for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      # Tie the cpu test and functional ports to the ruby cpu ports and
      # physmem, respectively
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 3ff4efed1..9c3207a90 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -79,7 +79,7 @@ system = System(tester = tester, physmem = PhysicalMemory())
 
 system.ruby = Ruby.create_system(options, system)
 
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
 #
 # The tester is most effective when randomization is turned on and
@@ -87,7 +87,7 @@ assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
 #
 system.ruby.randomization = True
 
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index e5e60573b..56b7ae1eb 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -79,14 +79,14 @@ system = System(cpu = cpus, physmem = PhysicalMemory())
 
 system.ruby = Ruby.create_system(options, system)
 
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
 for (i, cpu) in enumerate(system.cpu):
     #
     # Tie the cpu ports to the ruby cpu ports
     #
-    cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
-    cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
 
 # -----------------------
 # run simulation
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 6e51a0d67..c07881d24 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -76,14 +76,14 @@ system = System(cpu = cpu, physmem = PhysicalMemory())
 
 system.ruby = Ruby.create_system(options, system)
 
-assert(len(system.ruby.cpu_ruby_ports) == 1)
+assert(len(system.ruby._cpu_ruby_ports) == 1)
 
 #
 # Tie the cpu cache ports to the ruby cpu ports and
 # physmem, respectively
 #
-cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
-cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
+cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
+cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
 
 # -----------------------
 # run simulation