Regression: Use addTwoLevelCacheHierarchy in configs

This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.

The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.

The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.

11 files changed, 118 insertions, 155 deletions

diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index c3e705705..f75c5776d 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -90,28 +90,25 @@ cpu = DerivO3CPU(cpu_id=0)
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
-system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
 
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
+#create the iocache
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
 
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4),
-                            PageTableWalkerCache(),
-                            PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8),
+                              PageTableWalkerCache(),
+                              PageTableWalkerCache())
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 61a2c0772..b628992ec 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -92,28 +92,25 @@ cpu = AtomicSimpleCPU(cpu_id=0)
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
-system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
 
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
+#create the iocache
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
 
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4),
-                            PageTableWalkerCache(),
-                            PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8),
+                              PageTableWalkerCache(),
+                              PageTableWalkerCache())
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 896899e30..8a44300e5 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -93,27 +93,23 @@ system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4),
-                            PageTableWalkerCache(),
-                            PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8),
+                              PageTableWalkerCache(),
+                              PageTableWalkerCache())
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index 56990eb54..961a4a698 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -85,26 +85,23 @@ cpu = DerivO3CPU(cpu_id=0)
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+#connect up the checker
+cpu.addCheckerCpu()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the checker
-cpu.addCheckerCpu()
-#connect up the cpu and l1s
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
+# create the interrupt controller
 cpu.createInterruptController()
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 3159bb104..24e5ca82b 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -76,25 +76,21 @@ cpu = DerivO3CPU(cpu_id=0)
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index b6a77e38e..55c5d2409 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -73,26 +73,23 @@ class IOCache(BaseCache):
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
 system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
-system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
 
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
+#create the iocache
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
 
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 5ed97fdef..b5db3e10b 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -76,25 +76,21 @@ cpu = TimingSimpleCPU(cpu_id=0)
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 65912b30e..b32a1ff17 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -80,23 +80,21 @@ cpu.fetchBuffSize = 1
 system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
+# create the interrupt controller
+cpu.createInterruptController()
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 4af63431d..75ff66218 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -77,25 +77,21 @@ cpu = DerivO3CPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index da8985080..7d8743493 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -74,26 +74,23 @@ class IOCache(BaseCache):
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
-system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
 
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
+#create the iocache
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
 
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index d4ac5d0cf..b6378eb61 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -77,25 +77,21 @@ cpu = TimingSimpleCPU(cpu_id=0)
 system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                            L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+                              L1(size = '32kB', assoc = 4),
+                              L2(size = '4MB', assoc = 8))
 # create the interrupt controller
 cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
 cpu.clock = '2GHz'
 
 root = Root(full_system=True, system=system)