diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 17:02:16 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 17:02:16 -0800 |
| commit | d824af340ec98a9d7ac34a3c358666191df1f83f (patch) | |
| tree | 4e5a3b050c54b0a76e4487a3490c4c3ecb176215 /tests | |
| parent | 7b585114704532133c3aed01847fa534167018b3 (diff) | |
| download | gem5-d824af340ec98a9d7ac34a3c358666191df1f83f.tar.xz | |
X86: Update stats now that the micropc isn't always reset on faults.
Diffstat (limited to 'tests')
35 files changed, 309 insertions, 303 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index fb96ff412..93e326b16 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 7b8dadcc0..81b1be1e0 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:03:28 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:19:42 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 962951801000 because target called exit() +Exiting @ tick 962935342000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 4f9664bbc..fcdb37b5a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1613706 # Simulator instruction rate (inst/s) -host_mem_usage 195008 # Number of bytes of host memory used -host_seconds 1003.53 # Real time elapsed on the host -host_tick_rate 959566027 # Simulator tick rate (ticks/s) +host_inst_rate 717061 # Simulator instruction rate (inst/s) +host_mem_usage 197184 # Number of bytes of host memory used +host_seconds 2258.34 # Real time elapsed on the host +host_tick_rate 426391006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 0.962952 # Number of seconds simulated -sim_ticks 962951801000 # Number of ticks simulated +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 0.962935 # Number of seconds simulated +sim_ticks 962935342000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925903603 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 1925870685 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 7d5cc5629..4630d922d 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 5b0e0d9ff..7f0c2942c 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:23:58 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:22:06 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554132875000 because target called exit() +Exiting @ tick 2554098117000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 76b073830..89a1a5647 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159099 # Simulator instruction rate (inst/s) -host_mem_usage 201888 # Number of bytes of host memory used -host_seconds 1397.12 # Real time elapsed on the host -host_tick_rate 1828142910 # Simulator tick rate (ticks/s) +host_inst_rate 511923 # Simulator instruction rate (inst/s) +host_mem_usage 204640 # Number of bytes of host memory used +host_seconds 3163.30 # Real time elapsed on the host +host_tick_rate 807415286 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619398860 # Number of instructions simulated -sim_seconds 2.554133 # Number of seconds simulated -sim_ticks 2554132875000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses) +sim_insts 1619365942 # Number of instructions simulated +sim_seconds 2.554098 # Number of seconds simulated +sim_ticks 2554098117000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # m system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 506099 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606644555 # number of overall hits +system.cpu.dcache.overall_hits 606642715 # number of overall hits system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses system.cpu.dcache.overall_misses 506099 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use -system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.609383 # Cycle average of tags in use +system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1593417000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1925870644 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1925869923 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2671109.463245 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1925870644 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1925869923 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 721 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1925870644 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925902841 # number of overall hits +system.cpu.icache.overall_hits 1925869923 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use -system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 658.724449 # Cycle average of tags in use +system.cpu.icache.total_refs 1925869923 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16428.000401 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108265750 # number of cpu cycles simulated -system.cpu.num_insts 1619398860 # Number of instructions executed -system.cpu.num_refs 607161871 # Number of memory references +system.cpu.numCycles 5108196234 # number of cpu cycles simulated +system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.num_refs 607160031 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index 7f2a4c792..40541f366 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 195b58e3f..c22c368b8 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:20:12 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:05:48 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 165731691000 because target called exit() +Exiting @ tick 165726426000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index ee5db6e3c..a4a7be0d1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1935457 # Simulator instruction rate (inst/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 139.35 # Real time elapsed on the host -host_tick_rate 1189355805 # Simulator tick rate (ticks/s) +host_inst_rate 687504 # Simulator instruction rate (inst/s) +host_mem_usage 331712 # Number of bytes of host memory used +host_seconds 392.27 # Real time elapsed on the host +host_tick_rate 422480782 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.165732 # Number of seconds simulated -sim_ticks 165731691000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.165726 # Number of seconds simulated +sim_ticks 165726426000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 331463383 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 331452853 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 106b52826..2447a5715 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index a552023cf..5e04da3a3 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 13 2008 21:51:42 -M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 -M5 commit date Sun Nov 09 21:57:15 2008 -0800 -M5 started Nov 13 2008 21:51:43 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 20:14:49 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 495387670000 because target called exit() +Exiting @ tick 495377140000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 94a44a507..2fa37b8f7 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1084581 # Simulator instruction rate (inst/s) -host_mem_usage 336400 # Number of bytes of host memory used -host_seconds 248.67 # Real time elapsed on the host -host_tick_rate 1992187591 # Simulator tick rate (ticks/s) +host_inst_rate 422356 # Simulator instruction rate (inst/s) +host_mem_usage 339176 # Number of bytes of host memory used +host_seconds 638.53 # Real time elapsed on the host +host_tick_rate 775808629 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269697303 # Number of instructions simulated -sim_seconds 0.495388 # Number of seconds simulated -sim_ticks 495387670000 # Number of ticks simulated +sim_insts 269686773 # Number of instructions simulated +sim_seconds 0.495377 # Number of seconds simulated +sim_ticks 495377140000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits +system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 331462528 # number of overall hits +system.cpu.icache.overall_hits 331451998 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use -system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use +system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 990775340 # number of cpu cycles simulated -system.cpu.num_insts 269697303 # Number of instructions executed +system.cpu.numCycles 990754280 # number of cpu cycles simulated +system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 124054655 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index 21fdad99e..dd5474f9a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -12,6 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 110848279..08a12f2a0 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 16 2009 20:04:39 -M5 revision Unknown:Unknown -M5 commit date Unknown -M5 started Jan 16 2009 21:36:48 -M5 executing on zizzer +M5 compiled Feb 1 2009 00:35:14 +M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase +M5 started Feb 1 2009 01:31:23 +M5 executing on fajita command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ************************************************* + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** 58924 words stored in 3784810 bytes @@ -28,6 +28,8 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +74,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868687391000 because target called exit() +Exiting @ tick 868682305500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 547b9bbcd..9ef20eecb 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1452666 # Simulator instruction rate (inst/s) -host_mem_usage 201308 # Number of bytes of host memory used -host_seconds 1029.48 # Real time elapsed on the host -host_tick_rate 843810674 # Simulator tick rate (ticks/s) +host_inst_rate 942344 # Simulator instruction rate (inst/s) +host_mem_usage 199592 # Number of bytes of host memory used +host_seconds 1586.98 # Real time elapsed on the host +host_tick_rate 547379933 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492527 # Number of instructions simulated -sim_seconds 0.868687 # Number of seconds simulated -sim_ticks 868687391000 # Number of ticks simulated +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 0.868682 # Number of seconds simulated +sim_ticks 868682305500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737374783 # number of cpu cycles simulated -system.cpu.num_insts 1495492527 # Number of instructions executed -system.cpu.num_refs 533548974 # Number of memory references +system.cpu.numCycles 1737364612 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533548971 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index bcc04f400..793578856 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -12,6 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr index eae22fffc..94d399eab 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index c73c77520..3b8d98147 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 16 2009 20:04:39 -M5 revision Unknown:Unknown -M5 commit date Unknown -M5 started Jan 16 2009 21:37:18 -M5 executing on zizzer +M5 compiled Feb 1 2009 00:35:14 +M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase +M5 started Feb 1 2009 01:51:40 +M5 executing on fajita command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ************************************************* + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** 58924 words stored in 3784810 bytes @@ -28,6 +28,8 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +74,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2391380158000 because target called exit() +Exiting @ tick 2391369984000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index ddf39d868..c473a6423 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1062568 # Simulator instruction rate (inst/s) -host_mem_usage 208792 # Number of bytes of host memory used -host_seconds 1407.43 # Real time elapsed on the host -host_tick_rate 1699108877 # Simulator tick rate (ticks/s) +host_inst_rate 856633 # Simulator instruction rate (inst/s) +host_mem_usage 207060 # Number of bytes of host memory used +host_seconds 1745.77 # Real time elapsed on the host +host_tick_rate 1369809690 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495492527 # Number of instructions simulated -sim_seconds 2.391380 # Number of seconds simulated -sim_ticks 2391380158000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102185 # number of ReadReq accesses(hits+misses) +sim_insts 1495482356 # Number of instructions simulated +sim_seconds 2.391370 # Number of seconds simulated +sim_ticks 2391369984000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382375372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses @@ -30,16 +30,16 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # m system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.782576 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses @@ -50,11 +50,11 @@ system.cpu.dcache.demand_mshr_misses 3192961 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 533262385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069424 # number of overall hits +system.cpu.dcache.overall_hits 530069421 # number of overall hits system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses system.cpu.dcache.overall_misses 3192961 # number of overall misses @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.151091 # Cycle average of tags in use -system.cpu.dcache.total_refs 530744414 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use +system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1737374721 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1737371908 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617622.434412 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1737374721 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1737371908 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1737374721 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1737371908 # number of overall hits +system.cpu.icache.overall_hits 1737361737 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.848487 # Cycle average of tags in use -system.cpu.icache.total_refs 1737371908 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use +system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.686345 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4782760316 # number of cpu cycles simulated -system.cpu.num_insts 1495492527 # Number of instructions executed -system.cpu.num_refs 533548974 # Number of memory references +system.cpu.numCycles 4782739968 # number of cpu cycles simulated +system.cpu.num_insts 1495482356 # Number of instructions executed +system.cpu.num_refs 533548971 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3a2c48ff2..13ff2455f 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index bedb92044..346eca640 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 5 2008 23:38:14 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 20:02:35 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2835210954000 because target called exit() +Exiting @ tick 2835189187500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index a2bce703e..d428992be 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2012716 # Simulator instruction rate (inst/s) -host_mem_usage 194900 # Number of bytes of host memory used -host_seconds 2311.91 # Real time elapsed on the host -host_tick_rate 1226349708 # Simulator tick rate (ticks/s) +host_inst_rate 896643 # Simulator instruction rate (inst/s) +host_mem_usage 197076 # Number of bytes of host memory used +host_seconds 5189.55 # Real time elapsed on the host +host_tick_rate 546326494 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 2.835211 # Number of seconds simulated -sim_ticks 2835210954000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 2.835189 # Number of seconds simulated +sim_ticks 2835189187500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5670421909 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.numCycles 5670378376 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index caa9f8677..64329243b 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index c5e3246b3..f677c72d6 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 10:43:38 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 18:30:11 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 7645253019000 because target called exit() +Exiting @ tick 7645209486000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 5c98d4cbd..6bbf1280e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1139442 # Simulator instruction rate (inst/s) -host_mem_usage 201800 # Number of bytes of host memory used -host_seconds 4083.77 # Real time elapsed on the host -host_tick_rate 1872105757 # Simulator tick rate (ticks/s) +host_inst_rate 483951 # Simulator instruction rate (inst/s) +host_mem_usage 204540 # Number of bytes of host memory used +host_seconds 9614.98 # Real time elapsed on the host +host_tick_rate 795135330 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 7.645253 # Number of seconds simulated -sim_ticks 7645253019000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 7.645209 # Number of seconds simulated +sim_ticks 7645209486000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.377593 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 78020119000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 5670378338 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5670377663 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8400559.500741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5670378338 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5670377663 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5670378338 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5670421196 # number of overall hits +system.cpu.icache.overall_hits 5670377663 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use -system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.334555 # Cycle average of tags in use +system.cpu.icache.total_refs 5670377663 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25740.146811 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 6038871723000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15290506038 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.numCycles 15290418972 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index a50589b32..b8de37bf3 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -49,7 +49,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 1d99c3015..eea857771 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:16:46 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:57:21 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009373500 because target called exit() +122 123 124 Exiting @ tick 130009362500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 2581f730b..90a051575 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2311586 # Simulator instruction rate (inst/s) -host_mem_usage 202280 # Number of bytes of host memory used -host_seconds 94.57 # Real time elapsed on the host -host_tick_rate 1374811015 # Simulator tick rate (ticks/s) +host_inst_rate 697777 # Simulator instruction rate (inst/s) +host_mem_usage 204448 # Number of bytes of host memory used +host_seconds 313.27 # Real time elapsed on the host +host_tick_rate 415001936 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated +sim_insts 218595300 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009373500 # Number of ticks simulated +sim_ticks 130009362500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018748 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.numCycles 260018726 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165364 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 764f17d51..6c4741848 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2008 18:23:31 -M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e -M5 commit date Sat Nov 08 21:06:07 2008 -0800 -M5 started Nov 9 2008 18:29:22 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:12:20 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469714000 because target called exit() +122 123 124 Exiting @ tick 337469692000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 897f4bc38..91975530b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 937563 # Simulator instruction rate (inst/s) -host_mem_usage 210412 # Number of bytes of host memory used -host_seconds 233.15 # Real time elapsed on the host -host_tick_rate 1447418160 # Simulator tick rate (ticks/s) +host_inst_rate 495446 # Simulator instruction rate (inst/s) +host_mem_usage 211916 # Number of bytes of host memory used +host_seconds 441.21 # Real time elapsed on the host +host_tick_rate 764874761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595322 # Number of instructions simulated +sim_insts 218595300 # Number of instructions simulated sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469714000 # Number of ticks simulated +sim_ticks 337469692000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.541033 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 260018574 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 260013881 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # ms system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 55404.619859 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 260018574 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits +system.cpu.icache.demand_hits 260013881 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 4693 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 260018574 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013903 # number of overall hits +system.cpu.icache.overall_hits 260013881 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use -system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1453.991128 # Cycle average of tags in use +system.cpu.icache.total_refs 260013881 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2031.720476 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939428 # number of cpu cycles simulated -system.cpu.num_insts 218595322 # Number of instructions executed +system.cpu.numCycles 674939384 # number of cpu cycles simulated +system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165364 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 7fa8be29e..66f32751d 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 5 2008 23:03:02 -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 -M5 commit date Wed Nov 05 16:19:17 2008 -0500 -M5 started Nov 6 2008 00:18:22 -M5 executing on zizzer -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 18:30:07 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5518000 because target called exit() +Exiting @ tick 5513500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 3c3c458ce..2ee3e5703 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 557395 # Simulator instruction rate (inst/s) -host_mem_usage 190704 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 320851262 # Simulator tick rate (ticks/s) +host_inst_rate 5132 # Simulator instruction rate (inst/s) +host_mem_usage 192872 # Number of bytes of host memory used +host_seconds 1.85 # Real time elapsed on the host +host_tick_rate 2983162 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated +sim_insts 9484 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5518000 # Number of ticks simulated +sim_ticks 5513500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11037 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.numCycles 11028 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 9c811f04f..e9fb59225 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 00:19:20 -M5 executing on tater -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing +M5 compiled Dec 26 2008 18:29:56 +M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 +M5 commit date Fri Dec 26 18:25:21 2008 -0800 +M5 started Dec 26 2008 19:57:21 +M5 executing on fajita +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33851000 because target called exit() +Exiting @ tick 33842000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index cb9de2cde..4bf18211b 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106773 # Simulator instruction rate (inst/s) -host_mem_usage 197592 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 379942758 # Simulator tick rate (ticks/s) +host_inst_rate 494241 # Simulator instruction rate (inst/s) +host_mem_usage 200332 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1743803782 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9493 # Number of instructions simulated +sim_insts 9484 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33851000 # Number of ticks simulated +sim_ticks 33842000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 81.592815 # Cycle average of tags in use system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 10998 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 10770 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.020731 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.020731 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 47.236842 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 10998 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits +system.cpu.icache.demand_hits 10770 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.020731 # miss rate for demand accesses system.cpu.icache.demand_misses 228 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.020731 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 10998 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10779 # number of overall hits +system.cpu.icache.overall_hits 10770 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.020731 # miss rate for overall accesses system.cpu.icache.overall_misses 228 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.020731 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use -system.cpu.icache.total_refs 10779 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 107.523643 # Cycle average of tags in use +system.cpu.icache.total_refs 10770 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -219,13 +219,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 129.119087 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67702 # number of cpu cycles simulated -system.cpu.num_insts 9493 # Number of instructions executed +system.cpu.numCycles 67684 # number of cpu cycles simulated +system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |