diff options
| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-23 13:50:57 +0100 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-23 13:50:57 +0100 |
| commit | dbdb9ab518f919cf71c0acd03c16738202eeb61f (patch) | |
| tree | c2d0b6ca90110f7607e108628337e828bdb067ba /tests | |
| parent | f3f06e1684c6575e25b965ab0585473bb47e58cc (diff) | |
| download | gem5-dbdb9ab518f919cf71c0acd03c16738202eeb61f.tar.xz | |
arm, stats: Update stats to reflect changes to generic timer
The addition of a virtual timer affects stats in minor and o3.
Diffstat (limited to 'tests')
12 files changed, 3407 insertions, 3476 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index 302db364d..d9c429968 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/work/gem5/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -165,7 +163,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -179,7 +177,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu0.dcache] type=BaseCache @@ -202,7 +199,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -649,7 +645,7 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -662,7 +658,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -773,7 +768,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -899,7 +893,7 @@ dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -913,7 +907,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu1.dcache] type=BaseCache @@ -936,7 +929,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -1383,7 +1375,7 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -1396,7 +1388,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -1507,7 +1498,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -1621,7 +1611,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1657,7 +1646,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1686,7 +1674,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -2025,7 +2013,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -2038,7 +2027,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -2056,6 +2044,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -2225,7 +2214,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -2407,7 +2396,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index ef8cccd23..6375e36ce 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,19 +1,19 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled May 6 2015 17:58:20 +gem5 started May 6 2015 20:43:49 +gem5 executing on e104799-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual + Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x36c6a30 0x36c6a30 - 0: system.cpu1.isa: ISA system set to: 0x36c6a30 0x36c6a30 +info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x50ed000 0x50ed000 + 0: system.cpu1.isa: ISA system set to: 0x50ed000 0x50ed000 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2846097440000 because m5_exit instruction encountered +Exiting @ tick 2846106511000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index bb4196597..6bbef9107 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846145 # Number of seconds simulated -sim_ticks 2846145040000 # Number of ticks simulated -final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846107 # Number of seconds simulated +sim_ticks 2846106511000 # Number of ticks simulated +final_tick 2846106511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162017 # Simulator instruction rate (inst/s) -host_op_rate 196203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3671761280 # Simulator tick rate (ticks/s) -host_mem_usage 648900 # Number of bytes of host memory used -host_seconds 775.14 # Real time elapsed on the host -sim_insts 125586921 # Number of instructions simulated -sim_ops 152085297 # Number of ops (including micro ops) simulated +host_inst_rate 154405 # Simulator instruction rate (inst/s) +host_op_rate 186958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3504377822 # Simulator tick rate (ticks/s) +host_mem_usage 600496 # Number of bytes of host memory used +host_seconds 812.16 # Real time elapsed on the host +sim_insts 125401163 # Number of instructions simulated +sim_ops 151839522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1669760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1336112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8514432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 219648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 604112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 400768 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory +system.physmem.bytes_read::total 12756096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1669760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 219648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1889408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8854144 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8871708 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6262 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138346 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142737 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3103 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 586682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2991607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 140813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4481946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 586682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 663857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3110967 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3117138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3110967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 586682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 475610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2991607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 140813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199279 # Number of read requests accepted -system.physmem.writeReqs 179082 # Number of write requests accepted -system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12467 # Per bank write bursts -system.physmem.perBankRdBursts::1 12549 # Per bank write bursts -system.physmem.perBankRdBursts::2 12590 # Per bank write bursts -system.physmem.perBankRdBursts::3 12626 # Per bank write bursts -system.physmem.perBankRdBursts::4 14976 # Per bank write bursts -system.physmem.perBankRdBursts::5 12125 # Per bank write bursts -system.physmem.perBankRdBursts::6 13379 # Per bank write bursts -system.physmem.perBankRdBursts::7 13505 # Per bank write bursts -system.physmem.perBankRdBursts::8 12274 # Per bank write bursts -system.physmem.perBankRdBursts::9 12440 # Per bank write bursts -system.physmem.perBankRdBursts::10 11813 # Per bank write bursts -system.physmem.perBankRdBursts::11 11246 # Per bank write bursts -system.physmem.perBankRdBursts::12 11354 # Per bank write bursts -system.physmem.perBankRdBursts::13 11924 # Per bank write bursts -system.physmem.perBankRdBursts::14 11833 # Per bank write bursts -system.physmem.perBankRdBursts::15 12082 # Per bank write bursts -system.physmem.perBankWrBursts::0 9603 # Per bank write bursts -system.physmem.perBankWrBursts::1 9871 # Per bank write bursts -system.physmem.perBankWrBursts::2 10084 # Per bank write bursts -system.physmem.perBankWrBursts::3 9904 # Per bank write bursts -system.physmem.perBankWrBursts::4 9385 # Per bank write bursts -system.physmem.perBankWrBursts::5 9666 # Per bank write bursts -system.physmem.perBankWrBursts::6 10609 # Per bank write bursts -system.physmem.perBankWrBursts::7 10482 # Per bank write bursts -system.physmem.perBankWrBursts::8 9764 # Per bank write bursts -system.physmem.perBankWrBursts::9 9386 # Per bank write bursts -system.physmem.perBankWrBursts::10 9428 # Per bank write bursts -system.physmem.perBankWrBursts::11 9248 # Per bank write bursts -system.physmem.perBankWrBursts::12 9294 # Per bank write bursts -system.physmem.perBankWrBursts::13 9689 # Per bank write bursts -system.physmem.perBankWrBursts::14 9592 # Per bank write bursts -system.physmem.perBankWrBursts::15 9183 # Per bank write bursts +system.physmem.bw_total::total 7599085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199856 # Number of read requests accepted +system.physmem.writeReqs 178961 # Number of write requests accepted +system.physmem.readBursts 199856 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178961 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12785664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5120 # Total number of bytes read from write queue +system.physmem.bytesWritten 9927488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12756096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11190044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23813 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14250 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12367 # Per bank write bursts +system.physmem.perBankRdBursts::1 12533 # Per bank write bursts +system.physmem.perBankRdBursts::2 12905 # Per bank write bursts +system.physmem.perBankRdBursts::3 12918 # Per bank write bursts +system.physmem.perBankRdBursts::4 15006 # Per bank write bursts +system.physmem.perBankRdBursts::5 12397 # Per bank write bursts +system.physmem.perBankRdBursts::6 13141 # Per bank write bursts +system.physmem.perBankRdBursts::7 13266 # Per bank write bursts +system.physmem.perBankRdBursts::8 12256 # Per bank write bursts +system.physmem.perBankRdBursts::9 12318 # Per bank write bursts +system.physmem.perBankRdBursts::10 12174 # Per bank write bursts +system.physmem.perBankRdBursts::11 11385 # Per bank write bursts +system.physmem.perBankRdBursts::12 11522 # Per bank write bursts +system.physmem.perBankRdBursts::13 12342 # Per bank write bursts +system.physmem.perBankRdBursts::14 11687 # Per bank write bursts +system.physmem.perBankRdBursts::15 11559 # Per bank write bursts +system.physmem.perBankWrBursts::0 9829 # Per bank write bursts +system.physmem.perBankWrBursts::1 10209 # Per bank write bursts +system.physmem.perBankWrBursts::2 10296 # Per bank write bursts +system.physmem.perBankWrBursts::3 10100 # Per bank write bursts +system.physmem.perBankWrBursts::4 9093 # Per bank write bursts +system.physmem.perBankWrBursts::5 9584 # Per bank write bursts +system.physmem.perBankWrBursts::6 10130 # Per bank write bursts +system.physmem.perBankWrBursts::7 10398 # Per bank write bursts +system.physmem.perBankWrBursts::8 9607 # Per bank write bursts +system.physmem.perBankWrBursts::9 9596 # Per bank write bursts +system.physmem.perBankWrBursts::10 9832 # Per bank write bursts +system.physmem.perBankWrBursts::11 9707 # Per bank write bursts +system.physmem.perBankWrBursts::12 9196 # Per bank write bursts +system.physmem.perBankWrBursts::13 9428 # Per bank write bursts +system.physmem.perBankWrBursts::14 9291 # Per bank write bursts +system.physmem.perBankWrBursts::15 8821 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 107 # Number of times write queue was full causing retry -system.physmem.totGap 2846144533500 # Total gap between requests +system.physmem.numWrRetry 44 # Number of times write queue was full causing retry +system.physmem.totGap 2846106004500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 551 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198700 # Read request sizes (log2) +system.physmem.readPktSize::6 199276 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174691 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174570 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 48017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,164 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 536 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.481807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 139.408554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.811796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47817 52.39% 52.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18099 19.83% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6231 6.83% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3556 3.90% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2836 3.11% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1554 1.70% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 946 1.04% 88.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1020 1.12% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9214 10.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91273 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.298296 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 554.918828 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6572 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 49 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.965201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.421700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.995255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47261 52.01% 52.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18080 19.90% 71.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6274 6.90% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3625 3.99% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2837 3.12% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1606 1.77% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.10% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1046 1.15% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9138 10.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90865 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6548 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.509316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.919891 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6546 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads -system.physmem.totQLat 5766362365 # Total ticks spent queuing -system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6548 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.689218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.640113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.676171 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6193 94.58% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 92 1.41% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.37% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.24% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 27 0.41% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 36 0.55% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.38% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.18% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.26% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.05% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 21 0.32% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.27% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.17% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.08% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.02% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.12% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::912-927 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6548 # Writes before turning the bus around for reads +system.physmem.totQLat 5702655246 # Total ticks spent queuing +system.physmem.totMemAccLat 9448455246 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 998880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28545.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47295.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing -system.physmem.readRowHits 165729 # Number of row buffer hits during reads -system.physmem.writeRowHits 97368 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes -system.physmem.avgGap 7522298.90 # Average gap between requests -system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.569329 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states -system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing +system.physmem.readRowHits 166460 # Number of row buffer hits during reads +system.physmem.writeRowHits 97567 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.89 # Row buffer hit rate for writes +system.physmem.avgGap 7513142.24 # Average gap between requests +system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359425080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 196114875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815357400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 516060720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83232319410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634649447000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905662152725 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.569541 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719260667390 # Time in different power states +system.physmem_0.memoryStateTime::REF 95037540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31802228860 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.475203 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states -system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states +system.physmem_1.actEnergy 327514320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178703250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 742887600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489097440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82208245725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635547757250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905387633825 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.473086 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720763679724 # Time in different power states +system.physmem_1.memoryStateTime::REF 95037540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30305178276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -371,15 +363,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 33812647 # Number of BP lookups -system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits +system.cpu0.branchPred.lookups 20636360 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13610949 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1051916 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13187821 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9315921 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.640336 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3367590 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 213586 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,58 +402,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 65253 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 69356 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69356 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46232 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23124 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69356 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69356 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69356 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6817 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9525.708083 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8414.892081 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6090.769517 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6639 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 162 2.38% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6817 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5248 76.98% 76.98% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1569 23.02% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6817 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69356 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69356 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6817 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6817 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 76173 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22995822 # DTB read hits -system.cpu0.dtb.read_misses 59685 # DTB read misses -system.cpu0.dtb.write_hits 17147924 # DTB write hits -system.cpu0.dtb.write_misses 5568 # DTB write misses +system.cpu0.dtb.read_hits 17307432 # DTB read hits +system.cpu0.dtb.read_misses 63365 # DTB read misses +system.cpu0.dtb.write_hits 14534577 # DTB write hits +system.cpu0.dtb.write_misses 5991 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1432 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1922 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23055507 # DTB read accesses -system.cpu0.dtb.write_accesses 17153492 # DTB write accesses +system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17370797 # DTB read accesses +system.cpu0.dtb.write_accesses 14540568 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40143746 # DTB hits -system.cpu0.dtb.misses 65253 # DTB misses -system.cpu0.dtb.accesses 40208999 # DTB accesses +system.cpu0.dtb.hits 31842009 # DTB hits +system.cpu0.dtb.misses 69356 # DTB misses +system.cpu0.dtb.accesses 31911365 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,39 +483,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3866 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3833 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9827.457901 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8615.260983 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5288.530479 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 893 37.04% 37.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1467 60.85% 97.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 9 0.37% 98.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.62% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2111 87.56% 87.56% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 68390761 # ITB inst hits -system.cpu0.itb.inst_misses 3866 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38721907 # ITB inst hits +system.cpu0.itb.inst_misses 3833 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -532,131 +524,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2217 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7269 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses -system.cpu0.itb.hits 68390761 # DTB hits -system.cpu0.itb.misses 3866 # DTB misses -system.cpu0.itb.accesses 68394627 # DTB accesses -system.cpu0.numCycles 225488562 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38725740 # ITB inst accesses +system.cpu0.itb.hits 38721907 # DTB hits +system.cpu0.itb.misses 3833 # DTB misses +system.cpu0.itb.accesses 38725740 # DTB accesses +system.cpu0.numCycles 164661578 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104715622 # Number of instructions committed -system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.153342 # CPI: cycles per instruction -system.cpu0.ipc 0.464394 # IPC: instructions per cycle +system.cpu0.committedInsts 79519346 # Number of instructions committed +system.cpu0.committedOps 95696233 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5042389 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1874 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527576937 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.070711 # CPI: cycles per instruction +system.cpu0.ipc 0.482926 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed -system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 678004 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed +system.cpu0.tickCycles 128007340 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36654238 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714687 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.798460 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30351139 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715199 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.437334 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.798460 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978122 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978122 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 80249956 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 80249956 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21509384 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21509384 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16060534 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16060534 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307394 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307394 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357644 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 357644 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352742 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352742 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37569918 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37569918 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 37877312 # number of overall hits -system.cpu0.dcache.overall_hits::total 37877312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 441440 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 441440 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555221 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555221 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131923 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131923 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20844 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20844 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21317 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21317 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 996661 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 996661 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1128584 # number of overall misses -system.cpu0.dcache.overall_misses::total 1128584 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5848521453 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5848521453 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8885926805 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8885926805 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 320729731 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 320729731 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481626159 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 481626159 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 602000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 602000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14734448258 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14734448258 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14734448258 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14734448258 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21950824 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21950824 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16615755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16615755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439317 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 439317 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378488 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378488 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38566579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38566579 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39005896 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020110 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020110 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033415 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033415 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300291 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025843 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028934 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028934 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63691793 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63691793 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15776398 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15776398 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13416114 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13416114 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321622 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321622 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365571 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365571 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361457 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361457 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29192512 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29192512 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29514134 # number of overall hits +system.cpu0.dcache.overall_hits::total 29514134 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 464236 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 464236 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 577383 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 577383 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136671 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136671 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21082 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21082 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20299 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20299 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1041619 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1041619 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1178290 # number of overall misses +system.cpu0.dcache.overall_misses::total 1178290 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6143546304 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6143546304 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9155597212 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9155597212 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 318010226 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 318010226 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454779772 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 454779772 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15299143516 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15299143516 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15299143516 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15299143516 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16240634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16240634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13993497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13993497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458293 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 458293 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386653 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386653 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381756 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381756 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30234131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30234131 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30692424 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30692424 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028585 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028585 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041261 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041261 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298218 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298218 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054524 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054524 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053173 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053173 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034452 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034452 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038390 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038390 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.670599 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.670599 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15857.060585 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15857.060585 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15084.442937 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14687.849891 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,149 +657,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks -system.cpu0.dcache.writebacks::total 490183 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371857 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312047 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312047 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99536 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6041 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6041 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 683904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 683904 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 783440 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 514395 # number of writebacks +system.cpu0.dcache.writebacks::total 514395 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72393 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 72393 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253509 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 253509 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14653 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14653 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 325902 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 325902 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 325902 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 325902 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391843 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391843 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323874 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323874 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103461 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103461 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20299 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20299 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 715717 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715717 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 819178 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 819178 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39471 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4433666662 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4433666662 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4919386398 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4919386398 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621821456 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621821456 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96313514 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96313514 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423613728 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423613728 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 205000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 205000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9353053060 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9353053060 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974874516 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10974874516 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276413999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276413999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259254500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259254500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535668499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535668499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024127 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023145 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023145 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225753 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225753 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016627 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053173 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053173 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023672 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023672 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026690 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026690 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11314.905873 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11314.905873 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15189.198262 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15189.198262 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15675.679299 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15675.679299 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14981.103438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14981.103438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20868.699345 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20868.699345 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13068.088448 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13068.088448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13397.423412 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13397.423412 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209772.098450 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209772.098450 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170775.713911 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170775.713911 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190916.584302 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190916.584302 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1884730 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.784347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 66497574 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1885242 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.272699 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1966290 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.784569 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36747505 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1966802 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.683886 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784569 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 138650918 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 138650918 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 66497574 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 66497574 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 66497574 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 66497574 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 66497574 # number of overall hits -system.cpu0.icache.overall_hits::total 66497574 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1885257 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1885257 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1885257 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1885257 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1885257 # number of overall misses -system.cpu0.icache.overall_misses::total 1885257 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17590953808 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17590953808 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 17590953808 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17590953808 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 17590953808 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17590953808 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 68382831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 68382831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 68382831 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 68382831 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 68382831 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 68382831 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027569 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027569 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027569 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027569 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027569 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027569 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9330.798829 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9330.798829 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9330.798829 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9330.798829 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79395451 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79395451 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36747505 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36747505 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36747505 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36747505 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36747505 # number of overall hits +system.cpu0.icache.overall_hits::total 36747505 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1966814 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1966814 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1966814 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1966814 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1966814 # number of overall misses +system.cpu0.icache.overall_misses::total 1966814 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18563219293 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18563219293 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18563219293 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18563219293 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18563219293 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18563219293 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38714319 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38714319 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38714319 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38714319 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38714319 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38714319 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050803 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050803 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050803 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050803 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050803 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050803 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9438.217998 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9438.217998 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9438.217998 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9438.217998 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,436 +808,425 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1885257 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1885257 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1885257 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1885257 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1885257 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1885257 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1966814 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1966814 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1966814 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1966814 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1966814 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1966814 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15697482196 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15697482196 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15697482196 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15697482196 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15697482196 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15697482196 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16587142707 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16587142707 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16587142707 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16587142707 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16587142707 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16587142707 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027569 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027569 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027569 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8326.441539 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050803 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050803 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050803 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8433.508561 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1754468 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1754508 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838523 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1838641 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 221228 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 285273 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16083.611278 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2784455 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 301530 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.234421 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8638.017947 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.519313 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.077213 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4655.233239 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1567.458030 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1162.305536 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.527223 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003694 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284133 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095670 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070942 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1030 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15217 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 273 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 232831 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 300437 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16148.129146 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2913009 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 316676 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.198705 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2826267479000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6686.637120 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.827012 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.093258 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5824.484196 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1950.328123 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1638.759437 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.408120 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355498 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119039 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.100022 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985604 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15214 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 310 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 388 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 298 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4109 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7718 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3035 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062866 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928772 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 52971740 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 52971740 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77753 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4353 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1821437 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 376273 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2279816 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 490181 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 490181 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28296 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28296 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1798 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1798 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212312 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 212312 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77753 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4353 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1821437 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 588585 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2492128 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77753 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4353 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1821437 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 588585 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2492128 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 63820 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 101159 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 165890 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 28131 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 28131 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43311 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43311 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 788 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 63820 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144470 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 209201 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 788 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 63820 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144470 # number of overall misses -system.cpu0.l2cache.overall_misses::total 209201 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27073496 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2907382734 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2926155686 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5863387416 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 516960426 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 516960426 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396286408 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396286408 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 563999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 563999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2178252172 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2178252172 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 27073496 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2907382734 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5104407858 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8041639588 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 27073496 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2775500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2907382734 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5104407858 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8041639588 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78541 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4476 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1885257 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 477432 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2445706 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 490181 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 490181 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21316 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21316 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 255623 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 255623 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78541 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4476 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1885257 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 733055 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2701329 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78541 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4476 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1885257 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 733055 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2701329 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027480 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.033852 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.211881 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.067829 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.498538 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.498538 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.915650 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.915650 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169433 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169433 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027480 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033852 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197079 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.077444 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027480 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033852 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197079 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.077444 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22565.040650 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 45555.981416 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28926.301031 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35345.032347 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18376.894742 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18376.894742 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.638078 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.638078 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 563999 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 563999 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50293.278197 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50293.278197 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 38439.776043 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 38439.776043 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4157 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7950 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2796 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928589 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 55309423 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 55309423 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81547 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1895666 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 400950 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2382403 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 514393 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 514393 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28717 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28717 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1850 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1850 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223495 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 223495 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 81547 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1895666 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 624445 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2605898 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 81547 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1895666 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 624445 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2605898 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 820 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 71148 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 100778 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 172883 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26770 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26770 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18449 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18449 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44897 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44897 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 820 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 71148 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 145675 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 217780 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 820 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 71148 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 145675 # number of overall misses +system.cpu0.l2cache.overall_misses::total 217780 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28707498 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3099498 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3273175214 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3026145651 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 6331127861 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 497876262 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 497876262 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 373490824 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 373490824 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 199000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 199000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2237004716 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2237004716 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28707498 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3099498 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3273175214 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5263150367 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 8568132577 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28707498 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3099498 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3273175214 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5263150367 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 8568132577 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 82367 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4377 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1966814 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501728 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2555286 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 514393 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 514393 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55487 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55487 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20299 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20299 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268392 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 268392 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 82367 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4377 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1966814 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 770120 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2823678 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 82367 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4377 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1966814 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 770120 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2823678 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031300 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036174 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.200862 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.067657 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.482455 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.482455 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.908863 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.908863 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.167281 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.167281 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031300 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036174 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189159 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.077126 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031300 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036174 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189159 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.077126 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22624.072993 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46005.161269 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30027.839915 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36620.881527 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18598.291446 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18598.291446 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20244.502358 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.502358 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49825.260396 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49825.260396 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22624.072993 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46005.161269 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36129.400151 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39343.064455 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22624.072993 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46005.161269 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36129.400151 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39343.064455 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 91 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.333333 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 196267 # number of writebacks -system.cpu0.l2cache.writebacks::total 196267 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 50 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 373 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 423 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2918 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 2918 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 50 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3291 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3341 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 50 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3291 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3341 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 788 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 123 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 63770 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100786 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 165467 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 233242 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 28131 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28131 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19518 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19518 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40393 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40393 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 788 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 123 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63770 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141179 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 205860 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 788 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 123 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63770 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141179 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 439102 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 200924 # number of writebacks +system.cpu0.l2cache.writebacks::total 200924 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 68 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 431 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3081 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3081 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 68 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3512 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3580 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 68 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3512 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3580 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 820 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 137 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 71080 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100347 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 172384 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246966 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 246966 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26770 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26770 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18449 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18449 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41816 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41816 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 820 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 137 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71080 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142163 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 214200 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 820 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 137 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71080 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142163 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246966 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 461166 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32800 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23753 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58965 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1976000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2484151766 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2249231613 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4757297879 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14218858632 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 550871371 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 550871371 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 288938194 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 288938194 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 466499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 466499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1582913137 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1582913137 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1976000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2484151766 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3832144750 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6340211016 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1976000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2484151766 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3832144750 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20559069648 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42838 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23361000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2208000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2800542786 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2349073394 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5175185180 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14549193181 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14549193181 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 539459030 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 539459030 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 271290805 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 271290805 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 160000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 160000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1612964489 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1612964489 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23361000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2208000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2800542786 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3962037883 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6788149669 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23361000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2208000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2800542786 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3962037883 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14549193181 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21337342850 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5391279750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5673424250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4065113000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4065113000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113041750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395186250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115835500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115835500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9456392750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9738537250 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.211100 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067656 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7228877250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7511021750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.200003 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067462 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.498538 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.498538 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158018 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158018 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076207 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482455 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482455 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908863 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.908863 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155802 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155802 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075859 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163321 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23409.502965 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30021.261718 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58911.725424 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20151.626074 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20151.626074 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14704.905686 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14704.905686 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38572.902454 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38572.902454 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 661406 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2715743 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2641226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 514393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 305303 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43016 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112820 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297586 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284185 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3940361 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2387083 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11736 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6514027 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126091520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86470884 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17508 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329468 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 212909380 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 677925 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4032687 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.164340 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.370584 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3369954 83.57% 83.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 662733 16.43% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4032687 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2258839735 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115861999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2960687293 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1231161241 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7364989 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 92493743 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 5430284 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits +system.cpu1.branchPred.lookups 18540788 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6039472 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 931744 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9588411 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 6940637 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.385685 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8266914 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 716215 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1275,60 +1256,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 30040 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26399 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26399 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19296 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7103 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26399 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26399 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26399 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9779.693548 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8843.591627 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5628.626467 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 924 33.87% 33.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 61.25% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 66 2.42% 97.54% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.13% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 1 0.04% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1622643264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1622643264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1622643264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2007 73.57% 73.57% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 721 26.43% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2728 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26399 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26399 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2728 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2728 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29127 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5155380 # DTB read hits -system.cpu1.dtb.read_misses 27847 # DTB read misses -system.cpu1.dtb.write_hits 4232538 # DTB write hits -system.cpu1.dtb.write_misses 2193 # DTB write misses +system.cpu1.dtb.read_hits 10801915 # DTB read hits +system.cpu1.dtb.read_misses 24746 # DTB read misses +system.cpu1.dtb.write_hits 6805241 # DTB write hits +system.cpu1.dtb.write_misses 1653 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 413 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5183227 # DTB read accesses -system.cpu1.dtb.write_accesses 4234731 # DTB write accesses +system.cpu1.dtb.perms_faults 271 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10826661 # DTB read accesses +system.cpu1.dtb.write_accesses 6806894 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9387918 # DTB hits -system.cpu1.dtb.misses 30040 # DTB misses -system.cpu1.dtb.accesses 9417958 # DTB accesses +system.cpu1.dtb.hits 17607156 # DTB hits +system.cpu1.dtb.misses 26399 # DTB misses +system.cpu1.dtb.accesses 17633555 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1358,40 +1340,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2268 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2259 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9888.739946 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9049.592552 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4688.260195 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 127 11.35% 11.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 167 14.92% 26.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 537 47.99% 74.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 96.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 16 1.43% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 11 0.98% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1622052264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1622052264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1622052264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10199097 # ITB inst hits -system.cpu1.itb.inst_misses 2268 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3378 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39782626 # ITB inst hits +system.cpu1.itb.inst_misses 2259 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1400,130 +1385,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1864 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses -system.cpu1.itb.hits 10199097 # DTB hits -system.cpu1.itb.misses 2268 # DTB misses -system.cpu1.itb.accesses 10201365 # DTB accesses -system.cpu1.numCycles 54377537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39784885 # ITB inst accesses +system.cpu1.itb.hits 39782626 # DTB hits +system.cpu1.itb.misses 2259 # DTB misses +system.cpu1.itb.accesses 39784885 # DTB accesses +system.cpu1.numCycles 114626006 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20871299 # Number of instructions committed -system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.605374 # CPI: cycles per instruction -system.cpu1.ipc 0.383822 # IPC: instructions per cycle +system.cpu1.committedInsts 45881817 # Number of instructions committed +system.cpu1.committedOps 56143289 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4843481 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2780 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576973220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.498288 # CPI: cycles per instruction +system.cpu1.ipc 0.400274 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed -system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 231595 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8898721 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 231963 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90493998000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.666397 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942708 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.942708 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 368 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.718750 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18845353 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18845353 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4715534 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4715534 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3905905 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3905905 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65439 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65439 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88128 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88128 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80091 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80091 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8621439 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8621439 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8686878 # number of overall hits -system.cpu1.dcache.overall_hits::total 8686878 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 182965 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 182965 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 168408 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 168408 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35586 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35586 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17713 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17713 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23494 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23494 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 351373 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 351373 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 386959 # number of overall misses -system.cpu1.dcache.overall_misses::total 386959 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2670008756 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2670008756 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4196907972 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4196907972 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325609985 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325609985 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550485715 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550485715 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 359500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 359500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6866916728 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6866916728 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6866916728 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6866916728 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4898499 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4898499 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4074313 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4074313 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101025 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 101025 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105841 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105841 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103585 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 103585 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8972812 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8972812 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9073837 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9073837 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037351 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041334 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.041334 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.352249 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.352249 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167355 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167355 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226809 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226809 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039160 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039160 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042646 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042646 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24921.072467 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24921.072467 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18382.543047 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18382.543047 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23430.906402 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23430.906402 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed +system.cpu1.tickCycles 97881179 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 16744827 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 194211 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.569028 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17169326 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 194582 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 88.236970 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90524286500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.569028 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 371 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.724609 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 35245180 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 35245180 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10415746 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10415746 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6512410 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6512410 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50058 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50058 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80074 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80074 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71526 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71526 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16928156 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16928156 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 16978214 # number of overall hits +system.cpu1.dcache.overall_hits::total 16978214 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 157191 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 157191 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 144867 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 144867 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30819 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30819 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16921 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16921 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23675 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23675 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 302058 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 302058 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 332877 # number of overall misses +system.cpu1.dcache.overall_misses::total 332877 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2309301217 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2309301217 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3857781581 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3857781581 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316145498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 316145498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557553671 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557553671 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 527500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 527500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6167082798 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6167082798 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6167082798 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6167082798 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10572937 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10572937 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6657277 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6657277 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80877 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80877 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96995 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96995 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95201 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95201 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17230214 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17230214 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17311091 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17311091 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014867 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.014867 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021761 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021761 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381060 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381060 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174452 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174452 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248684 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248684 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017531 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.017531 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019229 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.019229 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14691.052395 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14691.052395 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26629.816183 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26629.816183 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18683.617871 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18683.617871 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23550.313453 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23550.313453 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19543.097301 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19543.097301 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20416.882844 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20416.882844 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18526.611325 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18526.611325 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1532,148 +1517,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks -system.cpu1.dcache.writebacks::total 138038 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18091 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62532 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62532 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12272 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12272 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 80623 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 80623 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 80623 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 80623 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164874 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164874 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105876 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105876 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34136 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 34136 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5441 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5441 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23494 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23494 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270750 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270750 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 304886 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 304886 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5716 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10726 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2161886054 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2161886054 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2482626291 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2482626291 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 533136002 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 533136002 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89692006 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89692006 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 513974285 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 513974285 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 347500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 347500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4644512345 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4644512345 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5177648347 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5177648347 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 978236749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 978236749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848797501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848797501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827034250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827034250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033658 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025986 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.337897 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.337897 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226809 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030174 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030174 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033601 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033601 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117850 # number of writebacks +system.cpu1.dcache.writebacks::total 117850 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15942 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15942 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52278 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 68220 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 68220 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 68220 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 68220 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141249 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 141249 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92589 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92589 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4886 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4886 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23675 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23675 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 233838 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 233838 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263747 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263747 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14605 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1867063577 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1867063577 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2294961861 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2294961861 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 485499507 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 485499507 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80204246 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80204246 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520729829 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520729829 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 512500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 512500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4162025438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4162025438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4647524945 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4647524945 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322107500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322107500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843997501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843997501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166105001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166105001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013359 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013359 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013908 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013908 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369808 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369808 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050374 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050374 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248684 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248684 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013571 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013571 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015236 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13218.242798 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24786.549817 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16232.555652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16415.113795 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.924139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.924139 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17798.755711 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17798.755711 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17621.148089 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17621.148089 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158994.008901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158994.008901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154490.407255 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154490.407255 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156968.652312 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156968.652312 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 1038832 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.324542 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 9157675 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 1039344 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.811014 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324542 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 947892 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.324313 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38832195 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 948404 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.944782 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72125006000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324313 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21433382 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21433382 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 9157675 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9157675 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9157675 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9157675 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9157675 # number of overall hits -system.cpu1.icache.overall_hits::total 9157675 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1039344 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 1039344 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 1039344 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 1039344 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 1039344 # number of overall misses -system.cpu1.icache.overall_misses::total 1039344 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9221968883 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9221968883 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9221968883 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9221968883 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9221968883 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9221968883 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10197019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10197019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10197019 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10197019 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10197019 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10197019 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.101926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.101926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.101926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.101926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.101926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.101926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8872.874508 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8872.874508 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8872.874508 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80509602 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80509602 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 38832195 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38832195 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38832195 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38832195 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38832195 # number of overall hits +system.cpu1.icache.overall_hits::total 38832195 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 948404 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 948404 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 948404 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 948404 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 948404 # number of overall misses +system.cpu1.icache.overall_misses::total 948404 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8190397665 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8190397665 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8190397665 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8190397665 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8190397665 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8190397665 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39780599 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39780599 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39780599 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39780599 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39780599 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39780599 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023841 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023841 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023841 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023841 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023841 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023841 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8635.979672 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8635.979672 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8635.979672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8635.979672 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1682,415 +1667,415 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039344 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 1039344 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039344 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 1039344 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039344 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 1039344 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948404 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 948404 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 948404 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 948404 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 948404 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 948404 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8180244117 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8180244117 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8180244117 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8180244117 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8180244117 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8180244117 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10330000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10330000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.101926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.101926 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.101926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7870.583865 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92232.142857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7240674335 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7240674335 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7240674335 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7240674335 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7240674335 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7240674335 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10306250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10306250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10306250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10306250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023841 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023841 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023841 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7634.588567 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7634.588567 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7634.588567 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92020.089286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92020.089286 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 272919 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 272954 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 197682 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197698 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 68790 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 69865 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15664.735857 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1313161 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 84814 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.482833 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58310 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54781 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15316.530997 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1176536 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69755 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.866691 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6115.525293 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.132908 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.972099 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5626.461246 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2273.619533 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1588.024777 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.373262 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003670 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000059 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.343412 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138771 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.096925 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.956100 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1163 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 7883.130354 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 45.774786 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.102173 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4372.978904 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2161.890501 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 852.654278 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.481148 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002794 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266905 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052042 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934847 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1060 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13867 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 654 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 402 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6148 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7266 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.070984 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 25009138 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 25009138 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33079 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2665 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1011889 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 130945 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1178578 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 138038 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 138038 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1986 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1986 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1041 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1041 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38169 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 38169 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33079 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2665 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1011889 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 169114 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1216747 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33079 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2665 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1011889 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 169114 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1216747 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 706 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 27455 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73504 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 101884 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29526 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29526 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22453 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22453 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36197 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36197 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 706 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 27455 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 109701 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 138081 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 706 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 27455 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 109701 # number of overall misses -system.cpu1.l2cache.overall_misses::total 138081 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17675980 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4473998 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1080327485 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1722703491 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2825180954 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 558586766 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 558586766 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449048470 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449048470 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 339500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 339500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429113805 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1429113805 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17675980 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4473998 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1080327485 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3151817296 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4254294759 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17675980 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4473998 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1080327485 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3151817296 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4254294759 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33785 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2884 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1039344 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 204449 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1280462 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 138038 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 138038 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31512 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31512 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23494 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23494 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74366 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 74366 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33785 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2884 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1039344 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 278815 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1354828 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33785 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2884 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1039344 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 278815 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1354828 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075936 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026416 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.359522 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.079568 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936976 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936976 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955691 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955691 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.486741 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.486741 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075936 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026416 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.393454 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.101918 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075936 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026416 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.393454 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.101918 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20429.214612 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 39349.025132 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23436.867259 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27729.387872 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18918.470704 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18918.470704 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19999.486483 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19999.486483 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6188 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7370 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064697 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.846375 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 22471002 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 22471002 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28799 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2667 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927404 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 105047 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1063917 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117850 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117850 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1629 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1629 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 948 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 948 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27664 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27664 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28799 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2667 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 927404 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 132711 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1091581 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28799 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2667 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 927404 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 132711 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1091581 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 641 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 224 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 21000 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 70995 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 92860 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28409 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28409 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22727 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22727 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34889 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34889 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 641 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 224 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 21000 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 105884 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 127749 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 641 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 224 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 21000 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 105884 # number of overall misses +system.cpu1.l2cache.overall_misses::total 127749 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14838480 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4527497 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 735996245 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1568239223 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 2323601445 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 538393885 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 538393885 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 458698584 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 458698584 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 502500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 502500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1371520229 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1371520229 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14838480 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4527497 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 735996245 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2939759452 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3695121674 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14838480 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4527497 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 735996245 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2939759452 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3695121674 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29440 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2891 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 948404 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 176042 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1156777 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 117850 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 117850 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30038 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30038 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23675 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23675 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62553 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62553 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29440 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2891 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 948404 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 238595 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1219330 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29440 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2891 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 948404 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 238595 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1219330 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077482 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022142 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.403284 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.080275 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.945769 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.945769 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.959958 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.959958 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.557751 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.557751 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077482 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022142 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443781 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.104770 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077482 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022142 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443781 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.104770 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20212.040179 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35047.440238 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22089.431974 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25022.630250 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18951.525397 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18951.525397 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20182.979892 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20182.979892 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39481.553858 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39481.553858 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30810.138679 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30810.138679 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39310.964172 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39310.964172 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20212.040179 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35047.440238 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27763.962941 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 28924.857917 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20212.040179 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35047.440238 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27763.962941 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 28924.857917 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 20.500000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 37239 # number of writebacks -system.cpu1.l2cache.writebacks::total 37239 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 26 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 127 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 350 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 350 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 477 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 503 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 477 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 503 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 706 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 27429 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73377 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 101731 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 35271 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29526 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29526 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22453 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22453 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35847 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 35847 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 706 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27429 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109224 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 137578 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 706 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27429 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109224 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 172849 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 31909 # number of writebacks +system.cpu1.l2cache.writebacks::total 31909 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 25 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 89 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 233 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 233 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 25 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 322 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 25 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 322 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 347 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 641 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 224 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20975 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70906 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 92746 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23372 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 23372 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28409 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28409 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22727 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22727 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34656 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34656 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 641 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 224 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20975 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105562 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 127402 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 641 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 224 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20975 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105562 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23372 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 150774 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5828 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14717 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10838 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3049500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 898741765 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1240067767 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2154933028 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1274079828 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 492031029 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 492031029 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 337561796 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 337561796 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 287500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 287500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1155906813 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1155906813 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3049500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 898741765 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2395974580 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3310839841 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3049500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 898741765 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2395974580 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4584919669 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9388000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 932474750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941862750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811133499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811133499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9388000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1743608249 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1752996249 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.358901 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.079449 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26653 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3070499 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 597837255 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1104689269 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1716260015 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 913442152 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 913442152 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453224001 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453224001 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 342962233 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 342962233 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 437500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 437500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1116530031 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1116530031 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3070499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 597837255 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2221219300 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2832790046 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3070499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 597837255 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2221219300 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 913442152 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3746232198 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9363750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205259000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214622750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754356999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754356999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9363750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959615999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3968979749 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402779 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080176 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936976 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936976 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955691 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955691 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.482035 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.482035 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101546 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.945769 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.945769 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959958 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959958 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554026 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554026 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104485 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123653 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 669363 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1570481 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1215284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117850 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42118 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67041 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1897032 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 831140 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7228 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62942 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2798342 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60705024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25653404 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86487752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 646083 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1988037 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.303225 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459652 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1385215 69.68% 69.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 602822 30.32% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1988037 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 835355978 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80571000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423456915 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410007475 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4338499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33513487 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30987 # Transaction distribution -system.iobus.trans_dist::ReadResp 30987 # Transaction distribution +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2099,7 +2084,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2115,16 +2100,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2140,10 +2125,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2154,7 +2139,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2184,52 +2169,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198954212 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36786767 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36403 # number of replacements -system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 14.479130 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270363169000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479130 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904946 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904946 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328077 # Number of tag accesses -system.iocache.tags.data_accesses 328077 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses -system.iocache.ReadReq_misses::total 229 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses -system.iocache.demand_misses::total 229 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 229 # number of overall misses -system.iocache.overall_misses::total 229 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6677842621 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6677842621 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29476377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29476377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29476377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 229 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 229 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31382127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31382127 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655722318 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6655722318 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31382127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31382127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31382127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31382127 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 229 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 229 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 229 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 229 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2238,40 +2223,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128717.803493 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128717.803493 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23020 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129144.555556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129144.555556 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183737.917348 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183737.917348 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129144.555556 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129144.555556 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22459 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3484 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.607348 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.547813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36174 # number of writebacks -system.iocache.writebacks::total 36174 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 229 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 229 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 229 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 229 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 229 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 229 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17561377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17561377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4794158657 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4794158657 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17561377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17561377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17561377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17561377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18687627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18687627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772040352 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772040352 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18687627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18687627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18687627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18687627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2280,593 +2265,568 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76903.814815 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76903.814815 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131736.979682 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131736.979682 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 136197 # number of replacements -system.l2c.tags.tagsinuse 64163.282922 # Cycle average of tags in use -system.l2c.tags.total_refs 379817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200471 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.894623 # Average number of references to valid blocks. +system.l2c.tags.replacements 136145 # number of replacements +system.l2c.tags.tagsinuse 64036.316369 # Cycle average of tags in use +system.l2c.tags.total_refs 380367 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200629 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.895872 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12850.317421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.201711 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6628.601764 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1957.826461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32727.538139 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.180445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851989 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4115.294958 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1518.513926 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4266.925013 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.196080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001056 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12112.427093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.878570 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.028766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8551.494132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2840.139732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35681.498153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.446887 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2203.793190 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 582.329943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1973.279904 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184821 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.029874 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.499383 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.062794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023171 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.065108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979054 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30066 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5589 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24336 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3041 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30776 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.458771 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.520782 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5295828 # Number of tag accesses -system.l2c.tags.data_accesses 5295828 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 375 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 73 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 43717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 47365 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45781 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 167 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 27 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 21454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 8059 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178003 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 233506 # number of Writeback hits -system.l2c.Writeback_hits::total 233506 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2927 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 947 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3874 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 89 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4056 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2216 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 375 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 43717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45781 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 167 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8059 # number of demand (read+write) hits -system.l2c.demand_hits::total 184275 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 375 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits -system.l2c.overall_hits::cpu0.inst 43717 # number of overall hits -system.l2c.overall_hits::cpu0.data 51421 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45781 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 167 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21454 # number of overall hits -system.l2c.overall_hits::cpu1.data 13201 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 8059 # number of overall hits -system.l2c.overall_hits::total 184275 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 130 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.130485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043337 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544456 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000251 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033627 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977117 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30113 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5558 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24416 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3300 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30690 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.459488 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.523788 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5288124 # Number of tag accesses +system.l2c.tags.data_accesses 5288124 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 404 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 85 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 48346 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 49709 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47536 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 123 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17643 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9297 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5444 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178619 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232833 # number of Writeback hits +system.l2c.Writeback_hits::total 232833 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2833 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 761 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3594 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 327 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4206 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1689 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5895 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 404 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 48346 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 53915 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47536 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 123 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17643 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5444 # number of demand (read+write) hits +system.l2c.demand_hits::total 184514 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 404 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits +system.l2c.overall_hits::cpu0.inst 48346 # number of overall hits +system.l2c.overall_hits::cpu0.data 53915 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47536 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 123 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17643 # number of overall hits +system.l2c.overall_hits::cpu1.data 10986 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5444 # number of overall hits +system.l2c.overall_hits::total 184514 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 138 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 20052 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8676 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 40 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5975 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2283 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq misses -system.l2c.ReadReq_misses::total 176209 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8724 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4132 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12856 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 807 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1210 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2017 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8457 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19529 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 130 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 22734 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9861 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 133208 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 22 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3332 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1132 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6262 # number of ReadReq misses +system.l2c.ReadReq_misses::total 176690 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 9235 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2955 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12190 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 697 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1269 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1966 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11244 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8331 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19575 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 138 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 20052 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19748 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5975 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10740 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) misses -system.l2c.demand_misses::total 195738 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 130 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 21105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133208 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3332 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9463 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6262 # number of demand (read+write) misses +system.l2c.demand_misses::total 196265 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 138 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 20052 # number of overall misses -system.l2c.overall_misses::cpu0.data 19748 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 129939 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5975 # number of overall misses -system.l2c.overall_misses::cpu1.data 10740 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 9112 # number of overall misses -system.l2c.overall_misses::total 195738 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 10973000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 22734 # number of overall misses +system.l2c.overall_misses::cpu0.data 21105 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133208 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 22 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3332 # number of overall misses +system.l2c.overall_misses::cpu1.data 9463 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6262 # number of overall misses +system.l2c.overall_misses::total 196265 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11906500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1610371008 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 763651868 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3426000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 494933758 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 205725771 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17729270285 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8986748 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6209345 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 15196093 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132469 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1093465 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2225934 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1027113188 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 693883201 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1720996389 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 10973000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1830615779 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 872554898 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13804634964 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1919000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 276050505 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 100986272 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 812337192 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17711087610 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 10802199 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3228400 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14030599 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1283464 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1219962 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2503426 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1032599700 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 678696974 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1711296674 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 11906500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1610371008 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1790765056 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 3426000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 494933758 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 899608972 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19450266674 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 10973000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1830615779 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1905154598 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13804634964 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1919000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 276050505 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 779683246 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 812337192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19422384284 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 11906500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1610371008 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1790765056 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 3426000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 494933758 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 899608972 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19450266674 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 505 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 74 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 63769 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 56041 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 175720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 207 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 28 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 27429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13268 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 17171 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 354212 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 233506 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 233506 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11651 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5079 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 16730 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1056 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2355 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15128 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10673 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25801 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 505 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 74 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 63769 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 71169 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 207 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 27429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23941 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17171 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 380013 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 505 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 74 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 63769 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 71169 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 207 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 27429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23941 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17171 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 380013 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.314447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.154815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.217835 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.172068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.497468 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748777 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.813546 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.768440 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764205 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.931486 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.856476 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.731888 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.792373 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.756909 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.013514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.314447 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.277480 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.035714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.217835 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.448603 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.515082 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.013514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.314447 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.277480 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.035714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.217835 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.448603 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.515082 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 1830615779 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1905154598 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13804634964 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1919000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 276050505 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 779683246 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 812337192 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19422384284 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 542 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 86 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 71080 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 59570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180744 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 145 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 20975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11706 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 355309 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 232833 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 232833 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 12068 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3716 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 15784 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 858 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1435 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2293 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15450 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10020 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25470 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 542 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 86 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 71080 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 75020 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180744 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 145 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 20975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 20449 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11706 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 380779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 542 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 86 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 71080 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 75020 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180744 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 145 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 20975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 20449 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11706 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 380779 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011628 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.319837 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.165536 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.158856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.108543 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.497285 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.765247 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795210 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.772301 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812354 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.884321 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.857392 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.727767 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.831437 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.768551 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.011628 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.319837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281325 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.158856 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.462761 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.515430 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.011628 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.319837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281325 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.158856 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.462761 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.515430 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80309.745063 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 88018.887506 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85650 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82834.101757 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 90112.032852 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 100615.009931 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1030.117836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1502.745644 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1182.023413 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1403.307311 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 903.690083 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1103.586515 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92766.725795 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82048.386071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 88125.167136 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80523.259391 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 88485.437380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82848.290816 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 89210.487633 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 100238.200294 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1169.702112 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1092.521151 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1150.992535 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1841.411765 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 961.356974 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1273.360122 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91835.618997 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81466.447485 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 87422.563167 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 99368.884294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80523.259391 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 90270.296044 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82848.290816 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82392.818979 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98959.999409 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 99368.884294 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 80523.259391 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 90270.296044 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82848.290816 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82392.818979 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98959.999409 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102293 # number of writebacks -system.l2c.writebacks::total 102293 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 130 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 102156 # number of writebacks +system.l2c.writebacks::total 102156 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 138 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 20049 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8676 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5975 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2283 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 176206 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8724 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4132 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12856 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 807 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1210 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2017 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11072 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8457 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19529 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 130 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 22733 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9861 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 22 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3332 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1132 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 176689 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 9235 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2955 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12190 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 697 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1269 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1966 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11244 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8331 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19575 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 138 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 20049 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 19748 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5975 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10740 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195735 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 130 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 22733 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 21105 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 22 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3332 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9463 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 196264 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 138 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 20049 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 19748 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5975 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10740 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195735 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 22733 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 21105 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 22 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3332 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9463 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 196264 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5712 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38624 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31175 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14601 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38466 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31021 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10722 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69799 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26537 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69487 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1359057992 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 655200132 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 420043242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 177097729 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15550639879 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 155599187 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 74220106 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 229819293 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14429805 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21503704 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 35933509 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 890221812 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 588134799 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1478356611 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1545823471 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 749260602 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 234290995 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 86797728 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15526768230 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 164742191 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52500445 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 217242636 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12465195 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22538766 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35003961 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 893597800 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 574508526 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1468106326 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1359057992 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1545421944 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 420043242 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 765232528 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17028996490 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1545823471 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1642858402 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 234290995 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 661306254 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16994874556 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1359057992 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1545421944 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 420043242 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 765232528 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17028996490 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1545823471 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1642858402 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 234290995 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 661306254 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16994874556 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4816468250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6816000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 820420250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5848412500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3580583500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 717922501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4298506001 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714675750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6791250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919935500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5846110500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2762262500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533068501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4295331001 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8397051750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6816000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1538342751 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10146918501 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154815 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172068 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.497459 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748777 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813546 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.768440 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764205 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.931486 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.856476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.731888 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792373 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.756909 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.515074 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.515074 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6476938250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6791250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453004001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10141441501 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165536 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.497283 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.765247 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795210 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.772301 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812354 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.884321 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857392 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.831437 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.768551 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281325 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.462761 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.515428 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.462761 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.515428 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69544.140830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75700.579190 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75982.212960 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76676.438163 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87876.258454 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17838.894532 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.648054 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17821.381132 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17884.067432 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17761.044917 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.659715 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79473.301316 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68960.332013 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74999.046028 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215059 # Transaction distribution -system.membus.trans_dist::ReadResp 215059 # Transaction distribution -system.membus.trans_dist::WriteReq 31175 # Transaction distribution -system.membus.trans_dist::WriteResp 31175 # Transaction distribution -system.membus.trans_dist::Writeback 138467 # Transaction distribution +system.membus.trans_dist::ReadReq 215398 # Transaction distribution +system.membus.trans_dist::ReadResp 215398 # Transaction distribution +system.membus.trans_dist::WriteReq 31021 # Transaction distribution +system.membus.trans_dist::WriteResp 31021 # Transaction distribution +system.membus.trans_dist::Writeback 138346 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 39963 # Transaction distribution -system.membus.trans_dist::ReadExResp 19392 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 76455 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40833 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14266 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 39995 # Transaction distribution +system.membus.trans_dist::ReadExResp 19465 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894055 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126068 # Total snoops (count) -system.membus.snoop_fanout::samples 580884 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19310684 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19503012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24138468 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124155 # Total snoops (count) +system.membus.snoop_fanout::samples 578323 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 578323 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580884 # Request fanout histogram -system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 578323 # Request fanout histogram +system.membus.reqLayer0.occupancy 88747000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12490999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1169123868 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1173969642 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37485233 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2899,44 +2859,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 293844 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 516846 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516831 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31021 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232833 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79939 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41160 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 121099 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51726 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51726 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338123 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1421869 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34155096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5564428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39719524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 288847 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 989795 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036873 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.188451 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 953298 96.31% 96.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36497 3.69% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 989795 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 786931704 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 682239026 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 258695257 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index b2af2f1b4..23230d1e0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/work/gem5/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -165,7 +163,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -179,7 +177,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -202,7 +199,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -662,7 +658,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -773,7 +768,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -862,7 +856,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -891,7 +884,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1230,7 +1223,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1243,7 +1237,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1261,6 +1254,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1430,7 +1424,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1612,7 +1606,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index e4f6e6f46..a77dec169 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,18 +1,18 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +gem5 compiled May 6 2015 17:58:20 +gem5 started May 6 2015 19:26:45 +gem5 executing on e104799-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor + Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x3fbcc30 0x3fbcc30 +info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.isa: ISA system set to: 0x3b57000 0x3b57000 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2852831758500 because m5_exit instruction encountered +Exiting @ tick 2852795541500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index d6c8679c7..60c7bcf62 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852840 # Number of seconds simulated -sim_ticks 2852839554500 # Number of ticks simulated -final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852796 # Number of seconds simulated +sim_ticks 2852795541500 # Number of ticks simulated +final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169032 # Simulator instruction rate (inst/s) -host_op_rate 204382 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4294589830 # Simulator tick rate (ticks/s) -host_mem_usage 620820 # Number of bytes of host memory used -host_seconds 664.29 # Real time elapsed on the host -sim_insts 112285680 # Number of instructions simulated -sim_ops 135768245 # Number of ops (including micro ops) simulated +host_inst_rate 152327 # Simulator instruction rate (inst/s) +host_op_rate 184181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3876544573 # Simulator tick rate (ticks/s) +host_mem_usage 573860 # Number of bytes of host memory used +host_seconds 735.91 # Real time elapsed on the host +sim_insts 112099513 # Number of instructions simulated +sim_ops 135541235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory +system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170389 # Number of read requests accepted -system.physmem.writeReqs 165345 # Number of write requests accepted -system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10917 # Per bank write bursts -system.physmem.perBankRdBursts::1 10861 # Per bank write bursts -system.physmem.perBankRdBursts::2 10721 # Per bank write bursts -system.physmem.perBankRdBursts::3 10725 # Per bank write bursts -system.physmem.perBankRdBursts::4 13339 # Per bank write bursts -system.physmem.perBankRdBursts::5 10813 # Per bank write bursts -system.physmem.perBankRdBursts::6 11142 # Per bank write bursts -system.physmem.perBankRdBursts::7 10985 # Per bank write bursts -system.physmem.perBankRdBursts::8 10153 # Per bank write bursts -system.physmem.perBankRdBursts::9 10280 # Per bank write bursts -system.physmem.perBankRdBursts::10 10274 # Per bank write bursts -system.physmem.perBankRdBursts::11 9203 # Per bank write bursts -system.physmem.perBankRdBursts::12 10314 # Per bank write bursts -system.physmem.perBankRdBursts::13 10760 # Per bank write bursts -system.physmem.perBankRdBursts::14 10035 # Per bank write bursts -system.physmem.perBankRdBursts::15 9744 # Per bank write bursts -system.physmem.perBankWrBursts::0 9017 # Per bank write bursts -system.physmem.perBankWrBursts::1 9225 # Per bank write bursts -system.physmem.perBankWrBursts::2 9344 # Per bank write bursts -system.physmem.perBankWrBursts::3 9210 # Per bank write bursts -system.physmem.perBankWrBursts::4 8591 # Per bank write bursts -system.physmem.perBankWrBursts::5 8923 # Per bank write bursts -system.physmem.perBankWrBursts::6 9235 # Per bank write bursts -system.physmem.perBankWrBursts::7 9154 # Per bank write bursts -system.physmem.perBankWrBursts::8 8919 # Per bank write bursts -system.physmem.perBankWrBursts::9 8830 # Per bank write bursts -system.physmem.perBankWrBursts::10 8770 # Per bank write bursts -system.physmem.perBankWrBursts::11 8263 # Per bank write bursts -system.physmem.perBankWrBursts::12 8824 # Per bank write bursts -system.physmem.perBankWrBursts::13 8884 # Per bank write bursts -system.physmem.perBankWrBursts::14 8238 # Per bank write bursts -system.physmem.perBankWrBursts::15 8054 # Per bank write bursts +system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169771 # Number of read requests accepted +system.physmem.writeReqs 164823 # Number of write requests accepted +system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10712 # Per bank write bursts +system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::2 10571 # Per bank write bursts +system.physmem.perBankRdBursts::3 10533 # Per bank write bursts +system.physmem.perBankRdBursts::4 13317 # Per bank write bursts +system.physmem.perBankRdBursts::5 10551 # Per bank write bursts +system.physmem.perBankRdBursts::6 11242 # Per bank write bursts +system.physmem.perBankRdBursts::7 11054 # Per bank write bursts +system.physmem.perBankRdBursts::8 10299 # Per bank write bursts +system.physmem.perBankRdBursts::9 10415 # Per bank write bursts +system.physmem.perBankRdBursts::10 10045 # Per bank write bursts +system.physmem.perBankRdBursts::11 9308 # Per bank write bursts +system.physmem.perBankRdBursts::12 10198 # Per bank write bursts +system.physmem.perBankRdBursts::13 10751 # Per bank write bursts +system.physmem.perBankRdBursts::14 10066 # Per bank write bursts +system.physmem.perBankRdBursts::15 10147 # Per bank write bursts +system.physmem.perBankWrBursts::0 8889 # Per bank write bursts +system.physmem.perBankWrBursts::1 8834 # Per bank write bursts +system.physmem.perBankWrBursts::2 9167 # Per bank write bursts +system.physmem.perBankWrBursts::3 9119 # Per bank write bursts +system.physmem.perBankWrBursts::4 8534 # Per bank write bursts +system.physmem.perBankWrBursts::5 8844 # Per bank write bursts +system.physmem.perBankWrBursts::6 9286 # Per bank write bursts +system.physmem.perBankWrBursts::7 9148 # Per bank write bursts +system.physmem.perBankWrBursts::8 9054 # Per bank write bursts +system.physmem.perBankWrBursts::9 9024 # Per bank write bursts +system.physmem.perBankWrBursts::10 8594 # Per bank write bursts +system.physmem.perBankWrBursts::11 8355 # Per bank write bursts +system.physmem.perBankWrBursts::12 8781 # Per bank write bursts +system.physmem.perBankWrBursts::13 8812 # Per bank write bursts +system.physmem.perBankWrBursts::14 8169 # Per bank write bursts +system.physmem.perBankWrBursts::15 8428 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 37 # Number of times write queue was full causing retry -system.physmem.totGap 2852839149500 # Total gap between requests +system.physmem.numWrRetry 51 # Number of times write queue was full causing retry +system.physmem.totGap 2852795136500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169832 # Read request sizes (log2) +system.physmem.readPktSize::6 169214 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160964 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160442 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,160 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5903 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5572 94.39% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.46% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 13 0.22% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 7 0.12% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads -system.physmem.totQLat 1723482630 # Total ticks spent queuing -system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads +system.physmem.totQLat 1681739444 # Total ticks spent queuing +system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing -system.physmem.readRowHits 140451 # Number of row buffer hits during reads -system.physmem.writeRowHits 109320 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes -system.physmem.avgGap 8497319.75 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.459893 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 140075 # Number of row buffer hits during reads +system.physmem.writeRowHits 109026 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes +system.physmem.avgGap 8526139.55 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.449413 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states +system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.354525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states +system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.351340 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states +system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -332,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31043514 # Number of BP lookups -system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits +system.cpu.branchPred.lookups 31028841 # Number of BP lookups +system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -371,59 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 65823 # Table walker walks requested -system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66007 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24809902 # DTB read hits -system.cpu.dtb.read_misses 58990 # DTB read misses -system.cpu.dtb.write_hits 19469042 # DTB write hits -system.cpu.dtb.write_misses 6833 # DTB write misses +system.cpu.dtb.read_hits 24765986 # DTB read hits +system.cpu.dtb.read_misses 59321 # DTB read misses +system.cpu.dtb.write_hits 19441821 # DTB write hits +system.cpu.dtb.write_misses 6686 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24868892 # DTB read accesses -system.cpu.dtb.write_accesses 19475875 # DTB write accesses +system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24825307 # DTB read accesses +system.cpu.dtb.write_accesses 19448507 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44278944 # DTB hits -system.cpu.dtb.misses 65823 # DTB misses -system.cpu.dtb.accesses 44344767 # DTB accesses +system.cpu.dtb.hits 44207807 # DTB hits +system.cpu.dtb.misses 66007 # DTB misses +system.cpu.dtb.accesses 44273814 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -453,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5435 # Table walker walks requested -system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5444 # Table walker walks requested +system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57700454 # ITB inst hits -system.cpu.itb.inst_misses 5435 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57608448 # ITB inst hits +system.cpu.itb.inst_misses 5444 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -492,274 +493,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57705889 # ITB inst accesses -system.cpu.itb.hits 57700454 # DTB hits -system.cpu.itb.misses 5435 # DTB misses -system.cpu.itb.accesses 57705889 # DTB accesses -system.cpu.numCycles 315730000 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57613892 # ITB inst accesses +system.cpu.itb.hits 57608448 # DTB hits +system.cpu.itb.misses 5444 # DTB misses +system.cpu.itb.accesses 57613892 # DTB accesses +system.cpu.numCycles 315454477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112285680 # Number of instructions committed -system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112099513 # Number of instructions committed +system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.811846 # CPI: cycles per instruction -system.cpu.ipc 0.355638 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.814058 # CPI: cycles per instruction +system.cpu.ipc 0.355359 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842413 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks. +system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked +system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842088 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41425130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41781539 # number of overall hits -system.cpu.dcache.overall_hits::total 41781539 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 491811 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 491811 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547829 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547829 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 170067 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 170067 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22347 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22347 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41360470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41360470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41717116 # number of overall hits +system.cpu.dcache.overall_hits::total 41717116 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 491782 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 491782 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547820 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169860 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169860 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22518 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22518 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1039640 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1039640 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1209707 # number of overall misses -system.cpu.dcache.overall_misses::total 1209707 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7276171447 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7276171447 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23463335520 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23463335520 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282730000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 282730000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30739506967 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30739506967 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30739506967 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30739506967 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23610199 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23610199 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18854571 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18854571 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526476 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526476 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466056 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466056 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460233 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460233 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42464770 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42464770 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42991246 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42991246 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020830 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020830 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029056 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323029 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.323029 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1039602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1039602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1209462 # number of overall misses +system.cpu.dcache.overall_misses::total 1209462 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7264308005 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7264308005 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23337097788 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23337097788 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285724000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 285724000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30601405793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30601405793 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30601405793 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30601405793 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23566505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23566505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18833567 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18833567 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526506 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526506 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466021 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466021 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460200 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460200 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42400072 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42400072 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42926578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42926578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020868 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020868 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029087 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029087 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322617 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.322617 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048320 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048320 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024482 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024482 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.649666 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.649666 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42829.670426 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42829.670426 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12651.810086 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12651.810086 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29567.453125 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29567.453125 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25410.704383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25410.704383 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024519 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024519 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028175 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028175 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14771.398719 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14771.398719 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42599.937549 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42599.937549 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12688.693490 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12688.693490 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29435.693461 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29435.693461 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25301.667843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25301.667843 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 252 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.318182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697807 # number of writebacks -system.cpu.dcache.writebacks::total 697807 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74753 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74753 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249005 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249005 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14114 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14114 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 323758 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 323758 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 323758 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 323758 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298824 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298824 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121668 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121668 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8233 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 697883 # number of writebacks +system.cpu.dcache.writebacks::total 697883 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74969 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74969 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14294 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14294 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324010 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324010 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324010 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324010 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416813 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 416813 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298779 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298779 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121645 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121645 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8224 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8224 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 715882 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 715882 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837550 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837550 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 715592 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715592 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837237 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703692140 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703692140 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12347213418 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12347213418 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562689830 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562689830 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105383000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105383000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18050905558 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18050905558 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19613595388 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19613595388 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837245750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837245750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4509635000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4509635000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346880750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346880750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017664 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017664 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015849 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015849 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231099 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231099 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5688327646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5688327646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12278776156 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12278776156 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1560607790 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1560607790 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106146500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106146500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17967103802 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17967103802 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19527711592 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19527711592 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837082750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837082750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510053000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510053000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10347135750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10347135750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017687 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017687 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017647 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017647 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016858 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016858 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019482 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019482 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13676.016621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13676.016621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41319.349912 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41319.349912 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12843.885245 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12843.885245 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12800.072877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12800.072877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25214.917484 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25214.917484 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23417.820295 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23417.820295 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187523.957530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187523.957530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163493.274843 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163493.274843 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176234.108600 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176234.108600 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25108.027762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23323.994988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23323.994988 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187518.721087 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187518.721087 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163508.429105 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163508.429105 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176238.451909 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897053 # number of replacements -system.cpu.icache.tags.tagsinuse 511.399913 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54794053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897565 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.910379 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.399913 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 2896868 # number of replacements +system.cpu.icache.tags.tagsinuse 511.399912 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54702268 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.879908 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15532248250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.399912 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60589206 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60589206 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54794053 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54794053 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54794053 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54794053 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54794053 # number of overall hits -system.cpu.icache.overall_hits::total 54794053 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897577 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897577 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897577 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897577 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897577 # number of overall misses -system.cpu.icache.overall_misses::total 2897577 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39289899153 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39289899153 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39289899153 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39289899153 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39289899153 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39289899153 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57691630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57691630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57691630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57691630 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57691630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57691630 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050225 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050225 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050225 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050225 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050225 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050225 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.570342 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13559.570342 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13559.570342 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13559.570342 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54702268 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54702268 # number of overall hits +system.cpu.icache.overall_hits::total 54702268 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2897392 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2897392 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2897392 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2897392 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2897392 # number of overall misses +system.cpu.icache.overall_misses::total 2897392 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39291591662 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39291591662 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39291591662 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39291591662 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39291591662 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39291591662 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57599660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57599660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57599660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57599660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57599660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57599660 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050302 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050302 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050302 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13561.020277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13561.020277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13561.020277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13561.020277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,200 +769,200 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897577 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897577 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897577 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897577 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897577 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897577 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897392 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897392 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897392 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897392 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897392 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897392 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34933961847 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34933961847 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34933961847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34933961847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34933961847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34933961847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34935956838 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34935956838 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34935956838 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34935956838 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34935956838 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34935956838 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050225 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050225 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050225 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.266959 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12056.266959 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050302 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050302 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050302 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.725305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.725305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 97102 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65057.867689 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4043768 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162361 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.906030 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96519 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65064.584640 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4043303 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 161770 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.994146 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47470.110176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.851294 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12225.097724 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5294.799022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724336 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47432.807159 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.814603 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12239.354143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5328.608352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.723767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080792 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992704 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65201 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.081308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 39 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65212 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994888 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36586462 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36586462 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69776 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4408 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2874567 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 532630 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3481381 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 697807 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 697807 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 52 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 52 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164524 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164524 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69776 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4408 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2874567 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 697154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3645905 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69776 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4408 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2874567 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 697154 # number of overall hits -system.cpu.l2cache.overall_hits::total 3645905 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 120 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 22985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14324 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37431 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2777 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2777 # number of UpgradeReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6950 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55839 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000595 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995056 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 36587667 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36587667 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4500 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2874373 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 532417 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3481647 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697883 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697883 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 51 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 165019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 165019 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 70357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4500 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2874373 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 697436 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3646666 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 70357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4500 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2874373 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 697436 # number of overall hits +system.cpu.l2cache.overall_hits::total 3646666 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 117 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 22990 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14260 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37368 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2783 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2783 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131476 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131476 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 120 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 22985 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 145800 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168907 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 120 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 22985 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 145800 # number of overall misses -system.cpu.l2cache.overall_misses::total 168907 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10600250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 179750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1839480250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1206111580 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3056371830 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1094965 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1094965 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10223101190 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10223101190 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10600250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 179750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1839480250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11429212770 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13279473020 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10600250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 179750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1839480250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11429212770 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13279473020 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69896 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4410 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 546954 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3518812 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 697807 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 697807 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2829 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2829 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 130931 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130931 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 117 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 22990 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145191 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168299 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 117 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 22990 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145191 # number of overall misses +system.cpu.l2cache.overall_misses::total 168299 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10468750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1843397750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1191861290 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3045810290 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1125464 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1125464 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10149479687 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10149479687 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10468750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1843397750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11341340977 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13195289977 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10468750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1843397750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11341340977 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13195289977 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70474 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4501 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897363 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 546677 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3519015 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 697883 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 697883 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2834 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2834 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296000 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296000 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4410 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2897552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 842954 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3814812 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4410 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2897552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 842954 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3814812 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001717 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000454 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007933 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.010637 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981619 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981619 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295950 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295950 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4501 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2897363 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 842627 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3814965 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4501 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2897363 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 842627 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3814965 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001660 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000222 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007935 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026085 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010619 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982004 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982004 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.444176 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.444176 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001717 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000454 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007933 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172963 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.044277 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001717 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000454 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007933 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172963 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.044277 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88335.416667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80029.595388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84202.148841 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81653.491224 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 394.297803 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 394.297803 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77756.405656 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77756.405656 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78620.027708 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78620.027708 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442409 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.442409 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001660 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000222 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007935 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172308 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044115 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001660 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000222 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007935 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172308 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044115 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89476.495726 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80182.590257 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83580.735624 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81508.517716 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 404.406755 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 404.406755 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77517.774148 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77517.774148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89476.495726 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80182.590257 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78113.250663 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78403.852530 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89476.495726 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80182.590257 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78113.250663 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78403.852530 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -970,38 +971,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88550 # number of writebacks -system.cpu.l2cache.writebacks::total 88550 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22965 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14184 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37271 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2777 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2777 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88028 # number of writebacks +system.cpu.l2cache.writebacks::total 88028 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 146 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 146 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 146 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22969 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14114 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37201 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2783 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2783 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131476 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131476 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 120 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22965 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 145660 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168747 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 120 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22965 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 145660 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168747 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130931 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130931 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 117 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 117 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145045 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168132 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34300 # number of ReadReq MSHR uncacheable @@ -1010,130 +1011,130 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61883 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9096750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 154250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550905750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1018516170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2578672920 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49510277 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49510277 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8577805310 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8577805310 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9096750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 154250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550905750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9596321480 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11156478230 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9096750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 154250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550905750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9596321480 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11156478230 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9004250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1554748750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1005120210 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2568943210 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49466283 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49466283 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8511009313 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8511009313 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9004250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1554748750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9516129523 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11079952523 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9004250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1554748750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9516129523 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11079952523 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400947000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592676750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4150934000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4150934000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400789000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592518750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151344500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151344500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551881000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743610750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025933 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981619 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981619 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9552133500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743863250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025818 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982004 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982004 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444176 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444176 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044235 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044235 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67533.453081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71807.400592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69187.113842 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17828.691754 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17828.691754 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.365983 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.365983 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044072 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044072 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67689.004746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71214.411931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69055.756834 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17774.445922 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17774.445922 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65003.775370 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65003.775370 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173507.677975 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163051.800292 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150488.851829 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173502.602159 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163047.193878 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150503.734184 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150503.734184 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162693.209109 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3578143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697807 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296000 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801472 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158425 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8481796 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185646272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98800797 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 279584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284744293 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61425 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4638617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.029225 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.168438 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60910 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4503052 97.08% 97.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 135565 2.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4638617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3012663750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4356641403 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341917112 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10549250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88533000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1230,23 +1231,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198836241 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36810509 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031382 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270536492000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031382 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1260,14 +1261,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29235877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29235877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6642330855 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6642330855 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29235877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29235877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29235877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29235877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1284,19 +1285,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124939.645299 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124939.645299 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183368.232525 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183368.232525 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124939.645299 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124939.645299 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.518745 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1310,14 +1311,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16926877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16926877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4758664873 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4758664873 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16926877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16926877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16926877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16926877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1326,66 +1327,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71805 # Transaction distribution -system.membus.trans_dist::ReadResp 71805 # Transaction distribution +system.membus.trans_dist::ReadReq 71735 # Transaction distribution +system.membus.trans_dist::ReadResp 71735 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124740 # Transaction distribution +system.membus.trans_dist::Writeback 124218 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4589 # Transaction distribution -system.membus.trans_dist::ReadExReq 129666 # Transaction distribution -system.membus.trans_dist::ReadExResp 129666 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution +system.membus.trans_dist::ReadExReq 129118 # Transaction distribution +system.membus.trans_dist::ReadExResp 129118 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447521 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16555296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16719005 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 394644 # Request fanout histogram +system.membus.snoop_fanout::samples 393527 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394644 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394644 # Request fanout histogram -system.membus.reqLayer0.occupancy 90290000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 393527 # Request fanout histogram +system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1707500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 172f27cee..9332ae5c7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/work/gem5/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -223,7 +221,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -295,9 +292,9 @@ opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList1] type=FUDesc @@ -309,23 +306,23 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 sys [system.cpu0.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu0.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu0.fuPool.FUList2] type=FUDesc @@ -337,9 +334,9 @@ opList=system.cpu0.fuPool.FUList2.opList [system.cpu0.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc @@ -351,9 +348,9 @@ opList=system.cpu0.fuPool.FUList3.opList [system.cpu0.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu0.fuPool.FUList4] type=FUDesc @@ -365,184 +362,184 @@ opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 s [system.cpu0.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu0.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu0.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu0.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu0.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu0.icache] type=BaseCache @@ -565,7 +562,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -676,7 +672,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -860,7 +855,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -932,9 +926,9 @@ opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList1] type=FUDesc @@ -946,23 +940,23 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 sys [system.cpu1.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu1.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu1.fuPool.FUList2] type=FUDesc @@ -974,9 +968,9 @@ opList=system.cpu1.fuPool.FUList2.opList [system.cpu1.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc @@ -988,9 +982,9 @@ opList=system.cpu1.fuPool.FUList3.opList [system.cpu1.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu1.fuPool.FUList4] type=FUDesc @@ -1002,184 +996,184 @@ opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 s [system.cpu1.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu1.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu1.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu1.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu1.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu1.icache] type=BaseCache @@ -1202,7 +1196,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -1313,7 +1306,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -1427,7 +1419,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1463,7 +1454,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1831,7 +1821,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1861,6 +1852,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index d603a7ffb..cd7aeb29d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,20 +1,19 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 15:52:40 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled May 6 2015 17:58:20 +gem5 started May 6 2015 18:01:09 +gem5 executing on e104799-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x4163810 0x4163810 - 0: system.cpu1.isa: ISA system set to: 0x4163810 0x4163810 +info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x4207000 0x4207000 + 0: system.cpu1.isa: ISA system set to: 0x4207000 0x4207000 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -30,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2625395606000 because m5_exit instruction encountered +Exiting @ tick 2625378187500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index f9cde53a3..22fe8f355 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.625378 # Nu sim_ticks 2625378187500 # Number of ticks simulated final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94574 # Simulator instruction rate (inst/s) -host_op_rate 114754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2065319127 # Simulator tick rate (ticks/s) -host_mem_usage 650700 # Number of bytes of host memory used -host_seconds 1271.17 # Real time elapsed on the host +host_inst_rate 105357 # Simulator instruction rate (inst/s) +host_op_rate 127837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2300779000 # Simulator tick rate (ticks/s) +host_mem_usage 602544 # Number of bytes of host memory used +host_seconds 1141.08 # Real time elapsed on the host sim_insts 120220550 # Number of instructions simulated sim_ops 145872273 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1570,8 +1570,8 @@ system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # La system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 35319893 # Number of BP lookups -system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted +system.cpu1.branchPred.lookups 35319894 # Number of BP lookups +system.cpu1.branchPred.condPredicted 12619407 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits @@ -1801,7 +1801,7 @@ system.cpu1.numWorkItemsStarted 0 # nu system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered +system.cpu1.fetch.Branches 35319894 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 1af28cf10..f06fb64e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/work/gem5/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -226,7 +224,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -298,9 +295,9 @@ opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList1] type=FUDesc @@ -312,16 +309,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu0.fuPool.FUList2] type=FUDesc @@ -333,23 +330,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys [system.cpu0.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu0.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu0.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc @@ -361,23 +358,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys [system.cpu0.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu0.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu0.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu0.fuPool.FUList4] type=FUDesc @@ -389,9 +386,9 @@ opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5] type=FUDesc @@ -403,142 +400,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s [system.cpu0.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList6] type=FUDesc @@ -550,9 +547,9 @@ opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu0.fuPool.FUList7] type=FUDesc @@ -564,16 +561,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu0.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu0.fuPool.FUList8] type=FUDesc @@ -585,9 +582,9 @@ opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu0.icache] type=BaseCache @@ -610,7 +607,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -865,9 +861,9 @@ opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList1] type=FUDesc @@ -879,16 +875,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu1.fuPool.FUList2] type=FUDesc @@ -900,23 +896,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys [system.cpu1.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu1.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu1.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc @@ -928,23 +924,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys [system.cpu1.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu1.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu1.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu1.fuPool.FUList4] type=FUDesc @@ -956,9 +952,9 @@ opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5] type=FUDesc @@ -970,142 +966,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s [system.cpu1.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList6] type=FUDesc @@ -1117,9 +1113,9 @@ opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu1.fuPool.FUList7] type=FUDesc @@ -1131,16 +1127,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu1.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu1.fuPool.FUList8] type=FUDesc @@ -1152,9 +1148,9 @@ opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu1.isa] type=ArmISA @@ -1285,7 +1281,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1321,7 +1316,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1689,7 +1683,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1719,6 +1714,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 8b56b1fe5..8e9e85e8f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 11:13:13 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled May 6 2015 17:58:20 +gem5 started May 6 2015 20:51:07 +gem5 executing on e104799-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x351fd50 0x351fd50 - 0: system.cpu1.isa: ISA system set to: 0x351fd50 0x351fd50 + 0: system.cpu0.isa: ISA system set to: 0x4a64c00 0x4a64c00 + 0: system.cpu1.isa: ISA system set to: 0x4a64c00 0x4a64c00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index db0feca69..ea24a0d2d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.804323 # Nu sim_ticks 2804323403500 # Number of ticks simulated final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111575 # Simulator instruction rate (inst/s) -host_op_rate 135423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2674508102 # Simulator tick rate (ticks/s) -host_mem_usage 626368 # Number of bytes of host memory used -host_seconds 1048.54 # Real time elapsed on the host +host_inst_rate 111566 # Simulator instruction rate (inst/s) +host_op_rate 135412 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2674295919 # Simulator tick rate (ticks/s) +host_mem_usage 578464 # Number of bytes of host memory used +host_seconds 1048.62 # Real time elapsed on the host sim_insts 116990114 # Number of instructions simulated sim_ops 141995948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -347,8 +347,8 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26894348 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13975310 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 26894349 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13975311 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 545296 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 16832825 # Number of BTB lookups system.cpu0.branchPred.BTBHits 12628735 # Number of BTB hits @@ -574,7 +574,7 @@ system.cpu0.numWorkItemsStarted 0 # nu system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.fetch.icacheStallCycles 39965142 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 103919162 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26894348 # Number of branches that fetch encountered +system.cpu0.fetch.Branches 26894349 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 19302280 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 61475471 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 3204102 # Number of cycles fetch has spent squashing |