diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
| commit | e76442e203bd4ce18e897658a17756a3d00bdeb8 (patch) | |
| tree | 93af3959085146bd965f4f7e8ad8e1dad142ce3d /tests | |
| parent | 7bb65dd4345401f40eccb5c23b563558dfd9e854 (diff) | |
| download | gem5-e76442e203bd4ce18e897658a17756a3d00bdeb8.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests')
19 files changed, 4933 insertions, 4915 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 993fcc90f..158348d27 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125946 # Number of seconds simulated -sim_ticks 5125946039500 # Number of ticks simulated -final_tick 5125946039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.121937 # Number of seconds simulated +sim_ticks 5121937205500 # Number of ticks simulated +final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214937 # Simulator instruction rate (inst/s) -host_op_rate 424847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2699457200 # Simulator tick rate (ticks/s) -host_mem_usage 751580 # Number of bytes of host memory used -host_seconds 1898.88 # Real time elapsed on the host -sim_insts 408140259 # Number of instructions simulated -sim_ops 806733017 # Number of ops (including micro ops) simulated +host_inst_rate 133395 # Simulator instruction rate (inst/s) +host_op_rate 263673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1674179733 # Simulator tick rate (ticks/s) +host_mem_usage 798472 # Number of bytes of host memory used +host_seconds 3059.37 # Real time elapsed on the host +sim_insts 408103625 # Number of instructions simulated +sim_ops 806672783 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1045568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11875520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1045568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1045568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9590656 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168702 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory +system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149854 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149854 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 203976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2106329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2316747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1871002 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1871002 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1871002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2106329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4187749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185555 # Number of read requests accepted -system.physmem.writeReqs 196574 # Number of write requests accepted -system.physmem.readBursts 185555 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196574 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11866560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 12447744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11875520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12580736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2049 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1754 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11700 # Per bank write bursts -system.physmem.perBankRdBursts::1 10942 # Per bank write bursts -system.physmem.perBankRdBursts::2 11772 # Per bank write bursts -system.physmem.perBankRdBursts::3 11534 # Per bank write bursts -system.physmem.perBankRdBursts::4 11556 # Per bank write bursts -system.physmem.perBankRdBursts::5 11202 # Per bank write bursts -system.physmem.perBankRdBursts::6 11589 # Per bank write bursts -system.physmem.perBankRdBursts::7 11470 # Per bank write bursts -system.physmem.perBankRdBursts::8 10957 # Per bank write bursts -system.physmem.perBankRdBursts::9 11574 # Per bank write bursts -system.physmem.perBankRdBursts::10 11037 # Per bank write bursts -system.physmem.perBankRdBursts::11 11773 # Per bank write bursts -system.physmem.perBankRdBursts::12 12032 # Per bank write bursts -system.physmem.perBankRdBursts::13 13037 # Per bank write bursts -system.physmem.perBankRdBursts::14 11759 # Per bank write bursts -system.physmem.perBankRdBursts::15 11481 # Per bank write bursts -system.physmem.perBankWrBursts::0 13445 # Per bank write bursts -system.physmem.perBankWrBursts::1 12349 # Per bank write bursts -system.physmem.perBankWrBursts::2 11384 # Per bank write bursts -system.physmem.perBankWrBursts::3 11463 # Per bank write bursts -system.physmem.perBankWrBursts::4 12267 # Per bank write bursts -system.physmem.perBankWrBursts::5 12371 # Per bank write bursts -system.physmem.perBankWrBursts::6 11486 # Per bank write bursts -system.physmem.perBankWrBursts::7 11359 # Per bank write bursts -system.physmem.perBankWrBursts::8 11596 # Per bank write bursts -system.physmem.perBankWrBursts::9 12338 # Per bank write bursts -system.physmem.perBankWrBursts::10 11770 # Per bank write bursts -system.physmem.perBankWrBursts::11 12080 # Per bank write bursts -system.physmem.perBankWrBursts::12 12282 # Per bank write bursts -system.physmem.perBankWrBursts::13 12669 # Per bank write bursts -system.physmem.perBankWrBursts::14 12453 # Per bank write bursts -system.physmem.perBankWrBursts::15 13184 # Per bank write bursts +system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185035 # Number of read requests accepted +system.physmem.writeReqs 196277 # Number of write requests accepted +system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11869 # Per bank write bursts +system.physmem.perBankRdBursts::1 11279 # Per bank write bursts +system.physmem.perBankRdBursts::2 11900 # Per bank write bursts +system.physmem.perBankRdBursts::3 11555 # Per bank write bursts +system.physmem.perBankRdBursts::4 12140 # Per bank write bursts +system.physmem.perBankRdBursts::5 11427 # Per bank write bursts +system.physmem.perBankRdBursts::6 11446 # Per bank write bursts +system.physmem.perBankRdBursts::7 11418 # Per bank write bursts +system.physmem.perBankRdBursts::8 11156 # Per bank write bursts +system.physmem.perBankRdBursts::9 11288 # Per bank write bursts +system.physmem.perBankRdBursts::10 11167 # Per bank write bursts +system.physmem.perBankRdBursts::11 11604 # Per bank write bursts +system.physmem.perBankRdBursts::12 11474 # Per bank write bursts +system.physmem.perBankRdBursts::13 12255 # Per bank write bursts +system.physmem.perBankRdBursts::14 11757 # Per bank write bursts +system.physmem.perBankRdBursts::15 11165 # Per bank write bursts +system.physmem.perBankWrBursts::0 12900 # Per bank write bursts +system.physmem.perBankWrBursts::1 13064 # Per bank write bursts +system.physmem.perBankWrBursts::2 11983 # Per bank write bursts +system.physmem.perBankWrBursts::3 10698 # Per bank write bursts +system.physmem.perBankWrBursts::4 10899 # Per bank write bursts +system.physmem.perBankWrBursts::5 11057 # Per bank write bursts +system.physmem.perBankWrBursts::6 11263 # Per bank write bursts +system.physmem.perBankWrBursts::7 11237 # Per bank write bursts +system.physmem.perBankWrBursts::8 11985 # Per bank write bursts +system.physmem.perBankWrBursts::9 12151 # Per bank write bursts +system.physmem.perBankWrBursts::10 12710 # Per bank write bursts +system.physmem.perBankWrBursts::11 12714 # Per bank write bursts +system.physmem.perBankWrBursts::12 13328 # Per bank write bursts +system.physmem.perBankWrBursts::13 13119 # Per bank write bursts +system.physmem.perBankWrBursts::14 12767 # Per bank write bursts +system.physmem.perBankWrBursts::15 11952 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5125945988000 # Total gap between requests +system.physmem.totGap 5121937091000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185555 # Read request sizes (log2) +system.physmem.readPktSize::6 185035 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196574 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 375 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196277 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -156,324 +156,321 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 10935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 13963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.362060 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.476414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.898646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27996 37.23% 37.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17297 23.00% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7451 9.91% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.59% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3004 4.00% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2064 2.74% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1408 1.87% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1199 1.59% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10568 14.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75192 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7811 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.734349 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.550807 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7810 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7811 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7811 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.900269 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.294695 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.961495 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6395 81.87% 81.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 66 0.84% 82.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 12 0.15% 82.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 258 3.30% 86.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 186 2.38% 88.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.64% 89.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 38 0.49% 89.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 45 0.58% 90.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 169 2.16% 92.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.14% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 12 0.15% 92.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.20% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 26 0.33% 93.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.20% 93.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 15 0.19% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 41 0.52% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 93 1.19% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.17% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.12% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 19 0.24% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 147 1.88% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.17% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.05% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 20 0.26% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 9 0.12% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 5 0.06% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.35% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 13 0.17% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.05% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.14% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.13% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.06% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 7 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 7 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 4 0.05% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7811 # Writes before turning the bus around for reads -system.physmem.totQLat 1990259250 # Total ticks spent queuing -system.physmem.totMemAccLat 5466790500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 927075000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10734.08 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads +system.physmem.totQLat 1977045500 # Total ticks spent queuing +system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29484.08 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing -system.physmem.readRowHits 152358 # Number of row buffer hits during reads -system.physmem.writeRowHits 152360 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.32 # Row buffer hit rate for writes -system.physmem.avgGap 13414176.86 # Average gap between requests -system.physmem.pageHitRate 80.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 277686360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 151515375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 715759200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 622883520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129454885665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2962010423250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3428034983850 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.761488 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4927497903250 # Time in different power states -system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing +system.physmem.readRowHits 151994 # Number of row buffer hits during reads +system.physmem.writeRowHits 151865 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes +system.physmem.avgGap 13432404.67 # Average gap between requests +system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764386 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states +system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27281453250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 290765160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 158651625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 730470000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 637450560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129625961760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2961860356500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3428105486085 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.775242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4927247811250 # Time in different power states -system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.765080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states +system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27531190000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 87010872 # Number of BP lookups -system.cpu.branchPred.condPredicted 87010872 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 908907 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80241948 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78260393 # Number of BTB hits +system.cpu.branchPred.lookups 86925803 # Number of BP lookups +system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.530525 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1567280 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 181222 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449757362 # number of cpu cycles simulated +system.cpu.numCycles 449601109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27680627 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429642410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 87010872 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79827673 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418150440 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1906654 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 150208 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 58666 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 213443 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 140 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9233721 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 451702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447207287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.895606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.052695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281559277 62.96% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2214583 0.50% 63.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72218429 16.15% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1625336 0.36% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2151026 0.48% 80.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2311115 0.52% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1533968 0.34% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1910699 0.43% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81682854 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447207287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193462 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.955276 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23009193 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264931793 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150859313 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7453661 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 953327 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 839350026 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 953327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25875798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223334745 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13198087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154759437 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29085893 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835811014 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 482001 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12419616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 206377 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13783403 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 998347758 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1815644422 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1116079946 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 122 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964783456 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33564300 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467714 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 471747 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39093495 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17396694 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10208602 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1304613 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1095322 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 830247357 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1203823 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824890478 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 241321 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23772173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36627244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152885 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447207287 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844537 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418419 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262823455 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13859186 3.10% 61.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10127573 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6921797 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74369123 16.63% 82.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4467728 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72848553 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1214671 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575201 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447207287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2002012 72.04% 72.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 252 0.01% 72.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1516 0.05% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 615311 22.14% 94.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160020 5.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292641 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796440241 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150873 0.02% 96.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125700 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued @@ -497,101 +494,101 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18469737 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9411286 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824890478 # Type of FU issued -system.cpu.iq.rate 1.834079 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2779111 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003369 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2100008470 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855235960 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820301631 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 204 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 226 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 827376851 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1872015 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued +system.cpu.iq.rate 1.833938 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3394675 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15480 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14595 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1778587 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224947 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72059 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 953327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205633916 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9395655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831451180 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157138 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17396694 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10208602 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 706837 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415978 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8079838 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14595 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 523025 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 540470 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1063495 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 823253062 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18064803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1501922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27249763 # number of memory reference insts executed -system.cpu.iew.exec_branches 83367725 # Number of branches executed -system.cpu.iew.exec_stores 9184960 # Number of stores executed -system.cpu.iew.exec_rate 1.830438 # Inst execution rate -system.cpu.iew.wb_sent 822742058 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 820301688 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641478984 # num instructions producing a value -system.cpu.iew.wb_consumers 1051241156 # num instructions consuming a value +system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed +system.cpu.iew.exec_branches 83328554 # Number of branches executed +system.cpu.iew.exec_stores 9168598 # Number of stores executed +system.cpu.iew.exec_rate 1.830370 # Inst execution rate +system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641244168 # num instructions producing a value +system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823876 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610211 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24588739 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050938 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 921334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443513076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818961 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675251 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272623912 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11196719 2.52% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3582296 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74597527 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2432522 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1609310 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 947533 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71068767 16.02% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5454490 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443513076 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408140259 # Number of instructions committed -system.cpu.commit.committedOps 806733017 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle +system.cpu.commit.committedInsts 408103625 # Number of instructions committed +system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22432033 # Number of memory references committed -system.cpu.commit.loads 14002018 # Number of loads committed -system.cpu.commit.membars 475437 # Number of memory barriers committed -system.cpu.commit.branches 82233213 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735520454 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156067 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171671 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783865362 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145082 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121451 0.02% 97.22% # Class of committed instruction +system.cpu.commit.refs 22427037 # Number of memory references committed +system.cpu.commit.loads 14000251 # Number of loads committed +system.cpu.commit.membars 475479 # Number of memory barriers committed +system.cpu.commit.branches 82225235 # Number of branches committed +system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.int_insts 735463006 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156113 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction @@ -615,167 +612,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13999436 1.74% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8430015 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806733017 # Class of committed instruction -system.cpu.commit.bw_lim_events 5454490 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction +system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1269302111 # The number of ROB reads -system.cpu.rob.rob_writes 1666357608 # The number of ROB writes -system.cpu.timesIdled 293383 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2550075 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9802132382 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408140259 # Number of Instructions Simulated -system.cpu.committedOps 806733017 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101968 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101968 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907468 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907468 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1093345902 # number of integer regfile reads -system.cpu.int_regfile_writes 656583711 # number of integer regfile writes -system.cpu.fp_regfile_reads 57 # number of floating regfile reads -system.cpu.cc_regfile_reads 416569502 # number of cc regfile reads -system.cpu.cc_regfile_writes 322266839 # number of cc regfile writes -system.cpu.misc_regfile_reads 265844677 # number of misc regfile reads -system.cpu.misc_regfile_writes 400270 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1661069 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997995 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19180634 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1661581 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.543605 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1268751952 # The number of ROB reads +system.cpu.rob.rob_writes 1665400460 # The number of ROB writes +system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 408103625 # Number of Instructions Simulated +system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads +system.cpu.int_regfile_writes 656343554 # number of integer regfile writes +system.cpu.fp_regfile_reads 191 # number of floating regfile reads +system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads +system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes +system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads +system.cpu.misc_regfile_writes 400219 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1658771 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997995 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88533012 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88533012 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11025921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11025921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8086239 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086239 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65769 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65769 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19112160 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19112160 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19177929 # number of overall hits -system.cpu.dcache.overall_hits::total 19177929 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1799370 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1799370 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334097 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334097 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406460 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406460 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2133467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2133467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2539927 # number of overall misses -system.cpu.dcache.overall_misses::total 2539927 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26521555176 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26521555176 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12869537398 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12869537398 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39391092574 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39391092574 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39391092574 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39391092574 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12825291 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12825291 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8420336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8420336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 472229 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 472229 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21245627 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21245627 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21717856 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21717856 # number of overall (read+write) accesses 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-system.cpu.dcache.ReadReq_avg_miss_latency::total 14739.356095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38520.362045 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38520.362045 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18463.417796 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18463.417796 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15508.749887 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15508.749887 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 376355 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits 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misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses +system.cpu.dcache.overall_misses::total 2536228 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles 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# number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 40236 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353688 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1562436 # number of writebacks -system.cpu.dcache.writebacks::total 1562436 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 828680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 828680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 43973 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 43973 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 872653 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 872653 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 872653 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 872653 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970690 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970690 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290124 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290124 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403005 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 403005 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1260814 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1260814 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1663819 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1663819 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12262338773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12262338773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11212126848 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11212126848 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584774002 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584774002 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23474465621 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23474465621 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29059239623 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29059239623 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97396245500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97396245500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2569003000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2569003000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99965248500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99965248500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075686 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075686 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853410 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853410 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076611 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076611 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12632.600287 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12632.600287 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38645.981884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38645.981884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13857.828072 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13857.828072 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18618.500128 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18618.500128 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17465.385131 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17465.385131 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks +system.cpu.dcache.writebacks::total 1560107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits 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+system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -783,58 +780,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 76914 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.799700 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 113377 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 76929 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.473788 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 194539504500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.799700 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.987481 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.987481 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 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-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77987 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 77987 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77987 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 77987 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77987 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 77987 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 949066206 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 949066206 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 949066206 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 949066206 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 949066206 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 949066206 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191387 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 191387 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191387 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 191387 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191387 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 191387 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407483 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407483 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407483 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407483 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407483 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407483 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12169.543719 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12169.543719 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12169.543719 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12169.543719 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770692 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770692 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770692 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 935770692 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770692 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 935770692 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177435 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177435 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177435 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177435 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177435 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177435 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,180 +840,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21202 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21202 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77987 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77987 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77987 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 77987 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77987 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 77987 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 792970936 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 792970936 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 792970936 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 792970936 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 792970936 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 792970936 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407483 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407483 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407483 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10167.988716 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624452 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624452 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624452 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624452 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624452 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624452 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448965 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448965 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448965 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 998047 # number of replacements -system.cpu.icache.tags.tagsinuse 509.614894 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8172291 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 998559 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.184084 # Average number of references to valid blocks. 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+system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10232340 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10232340 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8172291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8172291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8172291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8172291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8172291 # number of overall hits -system.cpu.icache.overall_hits::total 8172291 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061429 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061429 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061429 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061429 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061429 # number of overall misses -system.cpu.icache.overall_misses::total 1061429 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14726887378 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14726887378 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14726887378 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14726887378 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14726887378 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14726887378 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9233720 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9233720 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9233720 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9233720 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9233720 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9233720 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114951 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.114951 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.114951 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.114951 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.114951 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.114951 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13874.585467 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13874.585467 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13874.585467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13874.585467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13874.585467 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7528 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.974522 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits +system.cpu.icache.overall_hits::total 8118136 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses +system.cpu.icache.overall_misses::total 1063017 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses 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12093795712 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12093795712 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12093795712 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12093795712 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12093795712 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for overall accesses 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for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 15839 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.015286 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25359 # Total number of references to valid blocks. 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ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses 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miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342475 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342475 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342475 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342475 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112952 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64819.666116 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3838789 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176912 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.698862 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112445 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50506.549042 # Average occupied blocks per requestor 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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 594 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54407 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35127054 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35127054 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69856 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13439 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 982174 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1337175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2402644 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1586883 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1586883 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 35103909 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 35103909 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69111 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12768 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 984459 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1335184 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2401522 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154161 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154161 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69856 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 13439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 982174 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1491336 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2556805 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69856 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 13439 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 982174 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1491336 # number of overall hits -system.cpu.l2cache.overall_hits::total 2556805 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 68 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16339 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52237 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1483 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1483 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133848 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133848 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 68 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169673 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186085 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 68 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169673 # number of overall misses -system.cpu.l2cache.overall_misses::total 186085 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6082250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 393250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1247981750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2833529749 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4087986999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17399310 # number of UpgradeReq miss cycles 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miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1247981750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12170491459 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13424948709 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69924 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13444 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 998513 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1373000 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2454881 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1586883 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1586883 # number of Writeback accesses(hits+misses) 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# miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464735 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.464735 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000972 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000372 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016363 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102151 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.067843 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000972 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000372 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016363 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102151 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.067843 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89444.852941 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78650 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76380.546545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79093.642680 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.456630 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11732.508429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11732.508429 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69757.947149 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1045537500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10004443034 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11054910784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4538750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1045537500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10004443034 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11054910784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89282348000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89282348000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2403570000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2403570000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91685918000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91685918000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026127 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829564 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829564 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463364 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463364 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067690 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067690 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1304,63 +1301,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3077249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3076704 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1586883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1997133 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6136134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 33399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 169113 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8335779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63904832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208116125 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1068096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5832064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278921117 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60473 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4391663 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010846 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103577 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278739955 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 59032 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4387424 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010858 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103635 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4344032 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47631 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4391663 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4077594873 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 562500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1502063776 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3145123125 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 25073734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 117041135 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225706 # Transaction distribution -system.iobus.trans_dist::ReadResp 225706 # Transaction distribution -system.iobus.trans_dist::WriteReq 57738 # Transaction distribution -system.iobus.trans_dist::WriteResp 11018 # Transaction distribution +system.iobus.trans_dist::ReadReq 225722 # Transaction distribution +system.iobus.trans_dist::ReadResp 225722 # Transaction distribution +system.iobus.trans_dist::WriteReq 57753 # Transaction distribution +system.iobus.trans_dist::WriteResp 11033 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.iobus.trans_dist::MessageReq 1643 # Transaction distribution system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1376,15 +1373,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471626 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1400,19 +1397,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915656 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1442,54 +1439,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448351206 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460608000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52362260 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.091535 # Cycle average of tags in use +system.iocache.tags.replacements 47584 # number of replacements +system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992994629000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091535 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005721 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005721 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428679 # Number of tag accesses -system.iocache.tags.data_accesses 428679 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.tags.tag_accesses 428751 # Number of tag accesses +system.iocache.tags.data_accesses 428751 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses +system.iocache.ReadReq_misses::total 919 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses -system.iocache.demand_misses::total 911 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses -system.iocache.overall_misses::total 911 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147981947 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 147981947 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12360245999 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12360245999 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 147981947 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 147981947 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 147981947 # number of overall miss cycles -system.iocache.overall_miss_latency::total 147981947 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses +system.iocache.demand_misses::total 919 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses +system.iocache.overall_misses::total 919 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles +system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1498,40 +1495,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162439.019759 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264560.059910 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264560.059910 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162439.019759 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162439.019759 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70832 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9173 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.721792 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 911 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 911 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 911 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 911 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100584447 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9930786019 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9930786019 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100584447 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100584447 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1540,75 +1537,75 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110411.028540 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212559.632256 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212559.632256 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662583 # Transaction distribution -system.membus.trans_dist::ReadResp 662574 # Transaction distribution -system.membus.trans_dist::WriteReq 13905 # Transaction distribution -system.membus.trans_dist::WriteResp 13905 # Transaction distribution -system.membus.trans_dist::Writeback 149854 # Transaction distribution +system.membus.trans_dist::ReadReq 662612 # Transaction distribution +system.membus.trans_dist::ReadResp 662585 # Transaction distribution +system.membus.trans_dist::WriteReq 13919 # Transaction distribution +system.membus.trans_dist::WriteResp 13919 # Transaction distribution +system.membus.trans_dist::Writeback 149557 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2216 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution -system.membus.trans_dist::ReadExReq 133558 # Transaction distribution -system.membus.trans_dist::ReadExResp 133558 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution +system.membus.trans_dist::ReadExReq 133043 # Transaction distribution +system.membus.trans_dist::ReadExResp 133041 # Transaction distribution system.membus.trans_dist::MessageReq 1643 # Transaction distribution system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 9 # Transaction distribution +system.membus.trans_dist::BadAddressError 27 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1869505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18451136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20243357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26255049 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1599 # Total snoops (count) -system.membus.snoop_fanout::samples 385491 # Request fanout histogram +system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1603 # Total snoops (count) +system.membus.snoop_fanout::samples 384714 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385491 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385491 # Request fanout histogram -system.membus.reqLayer0.occupancy 251614500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 384714 # Request fanout histogram +system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583372000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1995485500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3161579497 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54941740 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 92c4535bc..384e2ffa5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305804 # Number of seconds simulated -sim_ticks 5305803886500 # Number of ticks simulated -final_tick 5305803886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305853 # Number of seconds simulated +sim_ticks 5305853045500 # Number of ticks simulated +final_tick 5305853045500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199055 # Simulator instruction rate (inst/s) -host_op_rate 381625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9885187347 # Simulator tick rate (ticks/s) -host_mem_usage 854320 # Number of bytes of host memory used -host_seconds 536.74 # Real time elapsed on the host -sim_insts 106841423 # Number of instructions simulated -sim_ops 204834575 # Number of ops (including micro ops) simulated +host_inst_rate 145601 # Simulator instruction rate (inst/s) +host_op_rate 279059 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7202357719 # Simulator tick rate (ticks/s) +host_mem_usage 842312 # Number of bytes of host memory used +host_seconds 736.68 # Real time elapsed on the host +sim_insts 107261903 # Number of instructions simulated +sim_ops 205578304 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11434048 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11434048 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9128256 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9128256 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178657 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178657 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 142629 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 142629 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2155008 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2155008 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1720428 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1720428 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3875436 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3875436 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178657 # Number of read requests accepted -system.mem_ctrls.writeReqs 142629 # Number of write requests accepted -system.mem_ctrls.readBursts 178657 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 142629 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11379712 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54336 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9119680 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11434048 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9128256 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 849 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11415232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11415232 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9161984 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9161984 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 178363 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 178363 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 143156 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 143156 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2151441 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2151441 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1726769 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1726769 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3878211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3878211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 178363 # Number of read requests accepted +system.mem_ctrls.writeReqs 143156 # Number of write requests accepted +system.mem_ctrls.readBursts 178363 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 143156 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11360576 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54656 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9153536 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11415232 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9161984 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 854 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 10773 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10609 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10875 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11019 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11847 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 12404 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11308 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10254 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10790 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10382 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10431 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 13895 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 11043 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10450 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11056 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10672 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 8646 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8740 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8909 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9072 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9699 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8889 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8365 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8684 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8653 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8512 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9107 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8716 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9206 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 9007 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10856 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10881 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10729 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11226 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11595 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12060 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10544 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10640 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10408 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10338 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14247 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10851 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10803 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10683 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8741 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8453 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8515 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9195 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9530 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 9142 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8665 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8844 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8855 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8455 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9314 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8873 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8616 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9161 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9108 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5305803752000 # Total gap between requests +system.mem_ctrls.totGap 5305852911000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178657 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 178363 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 142629 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177742 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 143156 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 177440 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 69 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2048 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2805 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8516 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9095 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8606 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9164 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9192 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8373 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9017 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9032 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8415 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8498 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8325 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8422 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8038 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8077 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8151 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7943 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 121 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 110 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 90 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 88 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 71 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2057 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2808 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8578 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9141 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8600 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9219 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8361 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9057 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9077 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8449 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8526 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8348 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8471 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8178 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 125 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 101 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 94 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 73 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 27 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 19 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,370 +184,373 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60600 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.272739 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.847297 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.861949 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20364 33.60% 33.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14670 24.21% 57.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6315 10.42% 68.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3448 5.69% 73.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2734 4.51% 78.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1855 3.06% 81.50% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1401 2.31% 83.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1433 2.36% 86.17% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8380 13.83% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60600 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7887 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.539115 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 318.374099 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7881 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60721 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 337.841076 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 199.411090 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 344.057801 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20489 33.74% 33.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14673 24.16% 57.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6364 10.48% 68.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3396 5.59% 73.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2745 4.52% 78.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1826 3.01% 81.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1362 2.24% 83.75% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1430 2.36% 86.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8436 13.89% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60721 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7928 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.388118 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.537098 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7922 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7887 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7887 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.067072 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.711824 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.086646 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5792 73.44% 73.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 155 1.97% 75.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 18 0.23% 75.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 48 0.61% 76.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 474 6.01% 82.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 162 2.05% 84.48% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 48 0.61% 85.09% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 632 8.01% 93.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 129 1.64% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 11 0.14% 94.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 12 0.15% 95.03% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 299 3.79% 98.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 7 0.09% 98.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 7 0.09% 99.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 8 0.10% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 6 0.08% 99.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 1 0.01% 99.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.48% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 11 0.14% 99.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 6 0.08% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 1 0.01% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 8 0.10% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 7 0.09% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7887 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1946379497 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5280279497 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 889040000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10946.52 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7928 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7928 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.040363 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.696882 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 3.983964 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5814 73.34% 73.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 181 2.28% 75.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 14 0.18% 75.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 36 0.45% 76.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 489 6.17% 82.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 149 1.88% 84.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 53 0.67% 85.14% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 653 8.24% 93.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 113 1.43% 94.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 3 0.04% 94.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 312 3.94% 98.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 4 0.05% 98.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 10 0.13% 99.12% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 5 0.06% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 9 0.11% 99.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 9 0.11% 99.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 4 0.05% 99.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 5 0.06% 99.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.65% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 2 0.03% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 1 0.01% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::49 2 0.03% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7928 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1963253998 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5291547748 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 887545000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 11060.03 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29696.52 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29810.03 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.29 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 141783 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 117919 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.74 # Row buffer hit rate for reads +system.mem_ctrls.avgWrQLen 24.94 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 141459 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118352 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.69 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16514270.00 # Average gap between requests -system.mem_ctrls.pageHitRate 81.07 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 229566960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 125259750 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 694894200 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 466333200 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149180699250 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052619831250 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549865642530 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.053779 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5078135564501 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls.avgGap 16502455.25 # Average gap between requests +system.mem_ctrls.pageHitRate 81.05 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 231139440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 126117750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 696134400 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 465251040 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149731396200 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052164794250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549966942360 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.066980 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177173880000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 50492285499 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 51294057500 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 228569040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 124715250 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 692000400 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 457034400 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 149006937600 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3052772253750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549830568360 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.047168 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5078398943499 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_1.actEnergy 227911320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 124356375 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 688428000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 461544480 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 149042883510 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3052768752750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549865985715 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.047952 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177173880000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 50232498501 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 50287445500 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10611607773 # number of cpu cycles simulated +system.cpu0.numCycles 10611706091 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58312369 # Number of instructions committed -system.cpu0.committedOps 112077158 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 105052932 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 985826 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9959513 # number of instructions that are conditional controls -system.cpu0.num_int_insts 105052932 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 198024346 # number of times the integer registers were read -system.cpu0.num_int_register_writes 89262745 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.committedInsts 59111887 # Number of instructions committed +system.cpu0.committedOps 113456709 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106426265 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu0.num_func_calls 1016173 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10055603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106426265 # number of integer instructions +system.cpu0.num_fp_insts 48 # number of float instructions +system.cpu0.num_int_register_reads 200823032 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90335124 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60301130 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43624803 # number of times the CC registers were written -system.cpu0.num_mem_refs 12143482 # number of memory refs -system.cpu0.num_load_insts 7354533 # Number of load instructions -system.cpu0.num_store_insts 4788949 # Number of store instructions -system.cpu0.num_idle_cycles 10094720432.678099 # Number of idle cycles -system.cpu0.num_busy_cycles 516887340.321903 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048710 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951290 # Percentage of idle cycles -system.cpu0.Branches 11277737 # Number of branches fetched -system.cpu0.op_class::No_OpClass 133660 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 99659673 88.92% 89.04% # Class of executed instruction -system.cpu0.op_class::IntMult 84103 0.08% 89.11% # Class of executed instruction -system.cpu0.op_class::IntDiv 57076 0.05% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::MemRead 7354533 6.56% 95.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 4788949 4.27% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 61044422 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44109295 # number of times the CC registers were written +system.cpu0.num_mem_refs 12452626 # number of memory refs +system.cpu0.num_load_insts 7522002 # Number of load instructions +system.cpu0.num_store_insts 4930624 # Number of store instructions +system.cpu0.num_idle_cycles 10088968020.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 522738070.665901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049261 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950739 # Percentage of idle cycles +system.cpu0.Branches 11433567 # Number of branches fetched +system.cpu0.op_class::No_OpClass 130284 0.11% 0.11% # Class of executed instruction +system.cpu0.op_class::IntAlu 100735872 88.79% 88.90% # Class of executed instruction +system.cpu0.op_class::IntMult 86129 0.08% 88.98% # Class of executed instruction +system.cpu0.op_class::IntDiv 56904 0.05% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::MemRead 7517799 6.63% 95.65% # Class of executed instruction +system.cpu0.op_class::MemWrite 4930624 4.35% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 112077994 # Class of executed instruction +system.cpu0.op_class::total 113457628 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10608678164 # number of cpu cycles simulated +system.cpu1.numCycles 10608768454 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48529054 # Number of instructions committed -system.cpu1.committedOps 92757417 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89083939 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1759211 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8292881 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89083939 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 172769101 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73668949 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.committedInsts 48150016 # Number of instructions committed +system.cpu1.committedOps 92121595 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88447961 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu1.num_func_calls 1752470 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8220366 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88447961 # number of integer instructions +system.cpu1.num_fp_insts 48 # number of float instructions +system.cpu1.num_int_register_reads 171418684 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73201141 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 51289512 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33065409 # number of times the CC registers were written -system.cpu1.num_mem_refs 14308473 # number of memory refs -system.cpu1.num_load_insts 9217545 # Number of load instructions -system.cpu1.num_store_insts 5090928 # Number of store instructions -system.cpu1.num_idle_cycles 10270312186.995054 # Number of idle cycles -system.cpu1.num_busy_cycles 338365977.004946 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031895 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968105 # Percentage of idle cycles -system.cpu1.Branches 10658677 # Number of branches fetched -system.cpu1.op_class::No_OpClass 173276 0.19% 0.19% # Class of executed instruction -system.cpu1.op_class::IntAlu 78104057 84.20% 84.39% # Class of executed instruction -system.cpu1.op_class::IntMult 100669 0.11% 84.50% # Class of executed instruction -system.cpu1.op_class::IntDiv 71662 0.08% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::MemRead 9217545 9.94% 94.51% # Class of executed instruction -system.cpu1.op_class::MemWrite 5090928 5.49% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 50927854 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32747914 # number of times the CC registers were written +system.cpu1.num_mem_refs 14125904 # number of memory refs +system.cpu1.num_load_insts 9133896 # Number of load instructions +system.cpu1.num_store_insts 4992008 # Number of store instructions +system.cpu1.num_idle_cycles 10273983246.713898 # Number of idle cycles +system.cpu1.num_busy_cycles 334785207.286102 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031557 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968443 # Percentage of idle cycles +system.cpu1.Branches 10582274 # Number of branches fetched +system.cpu1.op_class::No_OpClass 169782 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 77660292 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntMult 98483 0.11% 84.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 71910 0.08% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatCvt 16 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::MemRead 9129755 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4992008 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92758137 # Class of executed instruction +system.cpu1.op_class::total 92122246 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857916 # Transaction distribution -system.iobus.trans_dist::ReadResp 857916 # Transaction distribution -system.iobus.trans_dist::WriteReq 36558 # Transaction distribution -system.iobus.trans_dist::WriteResp 36558 # Transaction distribution -system.iobus.trans_dist::MessageReq 1920 # Transaction distribution -system.iobus.trans_dist::MessageResp 1920 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 857753 # Transaction distribution +system.iobus.trans_dist::ReadResp 857753 # Transaction distribution +system.iobus.trans_dist::WriteReq 36065 # Transaction distribution +system.iobus.trans_dist::WriteResp 36065 # Transaction distribution +system.iobus.trans_dist::MessageReq 1791 # Transaction distribution +system.iobus.trans_dist::MessageResp 1791 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5802 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5758 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 964 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 742772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702492 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 400 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 86270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1792788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85378 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1791218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3266 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 482 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1932 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7471 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 476 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1485538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971862 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1970762 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3366 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6089 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15515 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10473 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2031220 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51075 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2028533 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10107000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10224000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 145000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1059500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 97500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 55000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 28599000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 20660000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1327000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1276000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 39157000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31144500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23099500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 23664000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 469010624 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 468374820 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8240920 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7594080 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 1330000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 1329500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2415044 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2404400 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2023919000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 2023552000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 76513000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 60655000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -564,48 +567,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10911216 # delay histogram for all message -system.ruby.delayHist::mean 0.442136 # delay histogram for all message -system.ruby.delayHist::stdev 1.829254 # delay histogram for all message -system.ruby.delayHist | 10308626 94.48% 94.48% | 1272 0.01% 94.49% | 600907 5.51% 100.00% | 150 0.00% 100.00% | 203 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10911216 # delay histogram for all message +system.ruby.delayHist::samples 10895286 # delay histogram for all message +system.ruby.delayHist::mean 0.442462 # delay histogram for all message +system.ruby.delayHist::stdev 1.830078 # delay histogram for all message +system.ruby.delayHist | 10293202 94.47% 94.47% | 1309 0.01% 94.49% | 600320 5.51% 100.00% | 166 0.00% 100.00% | 230 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10895286 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152209035 -system.ruby.outstanding_req_hist::mean 1.000112 -system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010600 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152191931 99.99% 99.99% | 17104 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152209035 +system.ruby.outstanding_req_hist::samples 152835093 +system.ruby.outstanding_req_hist::mean 1.000166 +system.ruby.outstanding_req_hist::gmean 1.000115 +system.ruby.outstanding_req_hist::stdev 0.012900 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152809657 99.98% 99.98% | 25436 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152835093 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152209034 -system.ruby.latency_hist::mean 3.436503 -system.ruby.latency_hist::gmean 3.107893 -system.ruby.latency_hist::stdev 5.762527 -system.ruby.latency_hist | 152200028 99.99% 99.99% | 6260 0.00% 100.00% | 2677 0.00% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152209034 +system.ruby.latency_hist::samples 152835092 +system.ruby.latency_hist::mean 3.434217 +system.ruby.latency_hist::gmean 3.107238 +system.ruby.latency_hist::stdev 5.763379 +system.ruby.latency_hist | 152826007 99.99% 99.99% | 6324 0.00% 100.00% | 2683 0.00% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152835092 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149542283 +system.ruby.hit_latency_hist::samples 150173515 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149542283 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149542283 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150173515 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150173515 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2666751 -system.ruby.miss_latency_hist::mean 27.914090 -system.ruby.miss_latency_hist::gmean 22.539704 -system.ruby.miss_latency_hist::stdev 35.853723 -system.ruby.miss_latency_hist | 2657745 99.66% 99.66% | 6260 0.23% 99.90% | 2677 0.10% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2666751 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 10785659 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 531574 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11317233 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 67530179 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 328872 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 67859051 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2661577 +system.ruby.miss_latency_hist::mean 27.933965 +system.ruby.miss_latency_hist::gmean 22.542647 +system.ruby.miss_latency_hist::stdev 36.007083 +system.ruby.miss_latency_hist | 2652492 99.66% 99.66% | 6324 0.24% 99.90% | 2683 0.10% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2661577 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11100819 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532265 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11633084 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68582952 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323144 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68906096 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -616,12 +619,12 @@ system.ruby.l1_cntrl0.prefetcher.partial_hits 0 system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12972395 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1316773 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14289168 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 58254050 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 489532 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58743582 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12795048 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313851 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108899 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57694696 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 492317 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58187013 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -631,613 +634,602 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 10 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2439158 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227593 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2666751 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2434372 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227205 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2661577 # Number of cache demand accesses system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.030084 -system.ruby.network.routers0.msg_count.Control::0 860446 -system.ruby.network.routers0.msg_count.Request_Control::2 42982 -system.ruby.network.routers0.msg_count.Response_Data::1 889304 -system.ruby.network.routers0.msg_count.Response_Control::1 509254 -system.ruby.network.routers0.msg_count.Response_Control::2 506406 -system.ruby.network.routers0.msg_count.Writeback_Data::0 297072 -system.ruby.network.routers0.msg_count.Writeback_Data::1 216 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40606 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 15762 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 507294 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 298509 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 176 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 170526 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6843272 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2923632 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 126096 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4058352 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21492648 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12672 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1364208 +system.ruby.network.routers1.throttle0.link_utilization 0.082198 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+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380360 +system.ruby.network.routers3.throttle1.link_utilization 0.008341 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 178725 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 114940 system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12888144 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 925440 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12868200 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 919520 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 815 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 809 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58680 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58248 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000224 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47551 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380408 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47545 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.038501 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42982 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 848348 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 493076 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 343856 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 61081056 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3944608 -system.ruby.network.routers6.throttle1.link_utilization 0.082209 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40219 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796151 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1241782 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 321752 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129322872 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9934256 -system.ruby.network.routers6.throttle2.link_utilization 0.059751 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2666751 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203534 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 124997 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1764444 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 575124 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 402 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1113406 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21334008 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14654448 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 999976 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14115552 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41408928 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 28944 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8907248 -system.ruby.network.routers6.throttle3.link_utilization 0.005283 -system.ruby.network.routers6.throttle3.msg_count.Control::0 178187 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97745 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15738 -system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47551 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1425496 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7037640 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 125904 -system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380408 +system.ruby.network.routers6.throttle0.link_utilization 0.038287 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42371 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 843260 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494161 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 338968 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60714720 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953288 +system.ruby.network.routers6.throttle1.link_utilization 0.082198 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40332 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796167 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1239377 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 322656 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129324024 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9915016 +system.ruby.network.routers6.throttle2.link_utilization 0.059676 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2661577 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203207 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123979 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1763102 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574628 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 370 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1112755 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21292616 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14630904 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 991832 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14104816 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41373216 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26640 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8902040 +system.ruby.network.routers6.throttle3.link_utilization 0.005284 +system.ruby.network.routers6.throttle3.msg_count.Control::0 177916 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97855 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15288 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47545 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1423328 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7045560 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers6.throttle4.link_utilization 0.000255 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 815 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 809 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58680 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58248 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6119725 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.753707 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.339234 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5543761 90.59% 90.59% | 388 0.01% 90.59% | 575170 9.40% 99.99% | 147 0.00% 100.00% | 201 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6119725 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6112062 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754100 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.339998 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5536581 90.58% 90.58% | 390 0.01% 90.59% | 574653 9.40% 99.99% | 162 0.00% 100.00% | 217 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6112062 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4708290 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.044976 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595659 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4681222 99.43% 99.43% | 442 0.01% 99.43% | 339 0.01% 99.44% | 545 0.01% 99.45% | 25596 0.54% 100.00% | 141 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4708290 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4700521 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045023 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.596216 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4673467 99.42% 99.42% | 451 0.01% 99.43% | 352 0.01% 99.44% | 567 0.01% 99.45% | 25509 0.54% 100.00% | 158 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 10 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4700521 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 83201 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000120 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015504 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83196 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 83201 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 82703 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000121 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015550 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 82698 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 82703 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 14928118 -system.ruby.LD.latency_hist::mean 4.887199 -system.ruby.LD.latency_hist::gmean 3.596426 -system.ruby.LD.latency_hist::stdev 9.328249 -system.ruby.LD.latency_hist | 14912021 99.89% 99.89% | 13966 0.09% 99.99% | 828 0.01% 99.99% | 820 0.01% 100.00% | 357 0.00% 100.00% | 111 0.00% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist::total 14928118 +system.ruby.LD.latency_hist::samples 15017729 +system.ruby.LD.latency_hist::mean 4.875602 +system.ruby.LD.latency_hist::gmean 3.591894 +system.ruby.LD.latency_hist::stdev 9.357091 +system.ruby.LD.latency_hist | 15001612 99.89% 99.89% | 13925 0.09% 99.99% | 816 0.01% 99.99% | 883 0.01% 100.00% | 364 0.00% 100.00% | 107 0.00% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.latency_hist::total 15017729 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13535758 +system.ruby.LD.hit_latency_hist::samples 13626729 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535758 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13535758 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13626729 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13626729 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1392360 -system.ruby.LD.miss_latency_hist::mean 23.233506 -system.ruby.LD.miss_latency_hist::gmean 20.962083 -system.ruby.LD.miss_latency_hist::stdev 23.700852 -system.ruby.LD.miss_latency_hist | 1376263 98.84% 98.84% | 13966 1.00% 99.85% | 828 0.06% 99.91% | 820 0.06% 99.97% | 357 0.03% 99.99% | 111 0.01% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1392360 +system.ruby.LD.miss_latency_hist::samples 1391000 +system.ruby.LD.miss_latency_hist::mean 23.249665 +system.ruby.LD.miss_latency_hist::gmean 20.961439 +system.ruby.LD.miss_latency_hist::stdev 23.941766 +system.ruby.LD.miss_latency_hist | 1374883 98.84% 98.84% | 13925 1.00% 99.84% | 816 0.06% 99.90% | 883 0.06% 99.96% | 364 0.03% 99.99% | 107 0.01% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1391000 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9504180 -system.ruby.ST.latency_hist::mean 5.187204 -system.ruby.ST.latency_hist::gmean 3.302390 -system.ruby.ST.latency_hist::stdev 17.665644 -system.ruby.ST.latency_hist | 9498362 99.94% 99.94% | 3775 0.04% 99.98% | 1993 0.02% 100.00% | 29 0.00% 100.00% | 20 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9504180 +system.ruby.ST.latency_hist::samples 9551573 +system.ruby.ST.latency_hist::mean 5.175450 +system.ruby.ST.latency_hist::gmean 3.300314 +system.ruby.ST.latency_hist::stdev 17.651144 +system.ruby.ST.latency_hist | 9545752 99.94% 99.94% | 3768 0.04% 99.98% | 2002 0.02% 100.00% | 25 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9551573 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9152723 +system.ruby.ST.hit_latency_hist::samples 9200826 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9152723 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9152723 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9200826 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9200826 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 351457 -system.ruby.ST.miss_latency_hist::mean 62.146880 -system.ruby.ST.miss_latency_hist::gmean 40.269218 -system.ruby.ST.miss_latency_hist::stdev 71.205537 -system.ruby.ST.miss_latency_hist | 345639 98.34% 98.34% | 3775 1.07% 99.42% | 1993 0.57% 99.99% | 29 0.01% 99.99% | 20 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351457 +system.ruby.ST.miss_latency_hist::samples 350747 +system.ruby.ST.miss_latency_hist::mean 62.242032 +system.ruby.ST.miss_latency_hist::gmean 40.314149 +system.ruby.ST.miss_latency_hist::stdev 71.440751 +system.ruby.ST.miss_latency_hist | 344926 98.34% 98.34% | 3768 1.07% 99.41% | 2002 0.57% 99.99% | 25 0.01% 99.99% | 25 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 350747 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126602633 -system.ruby.IFETCH.latency_hist::mean 3.119985 -system.ruby.IFETCH.latency_hist::gmean 3.036795 -system.ruby.IFETCH.latency_hist::stdev 2.244898 -system.ruby.IFETCH.latency_hist | 126595894 99.99% 99.99% | 5742 0.00% 100.00% | 458 0.00% 100.00% | 336 0.00% 100.00% | 141 0.00% 100.00% | 58 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126602633 +system.ruby.IFETCH.latency_hist::samples 127093109 +system.ruby.IFETCH.latency_hist::mean 3.119052 +system.ruby.IFETCH.latency_hist::gmean 3.036517 +system.ruby.IFETCH.latency_hist::stdev 2.234317 +system.ruby.IFETCH.latency_hist | 127086454 99.99% 99.99% | 5646 0.00% 100.00% | 489 0.00% 100.00% | 322 0.00% 100.00% | 142 0.00% 100.00% | 52 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 127093109 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125784229 +system.ruby.IFETCH.hit_latency_hist::samples 126277648 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125784229 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125784229 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126277648 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126277648 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 818404 -system.ruby.IFETCH.miss_latency_hist::mean 21.561079 -system.ruby.IFETCH.miss_latency_hist::gmean 19.774643 -system.ruby.IFETCH.miss_latency_hist::stdev 20.911893 -system.ruby.IFETCH.miss_latency_hist | 811665 99.18% 99.18% | 5742 0.70% 99.88% | 458 0.06% 99.93% | 336 0.04% 99.98% | 141 0.02% 99.99% | 58 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 818404 +system.ruby.IFETCH.miss_latency_hist::samples 815461 +system.ruby.IFETCH.miss_latency_hist::mean 21.554760 +system.ruby.IFETCH.miss_latency_hist::gmean 19.772157 +system.ruby.IFETCH.miss_latency_hist::stdev 20.880175 +system.ruby.IFETCH.miss_latency_hist | 808806 99.18% 99.18% | 5646 0.69% 99.88% | 489 0.06% 99.94% | 322 0.04% 99.98% | 142 0.02% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 815461 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 494795 -system.ruby.RMW_Read.latency_hist::mean 6.019475 -system.ruby.RMW_Read.latency_hist::gmean 3.954538 -system.ruby.RMW_Read.latency_hist::stdev 10.125129 -system.ruby.RMW_Read.latency_hist | 494623 99.97% 99.97% | 131 0.03% 99.99% | 11 0.00% 99.99% | 18 0.00% 100.00% | 7 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494795 +system.ruby.RMW_Read.latency_hist::samples 493321 +system.ruby.RMW_Read.latency_hist::mean 6.020581 +system.ruby.RMW_Read.latency_hist::gmean 3.953173 +system.ruby.RMW_Read.latency_hist::stdev 10.251314 +system.ruby.RMW_Read.latency_hist | 493148 99.96% 99.96% | 127 0.03% 99.99% | 17 0.00% 99.99% | 15 0.00% 100.00% | 9 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 493321 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 429248 +system.ruby.RMW_Read.hit_latency_hist::samples 428061 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 429248 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428061 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428061 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65547 -system.ruby.RMW_Read.miss_latency_hist::mean 25.793126 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.141988 -system.ruby.RMW_Read.miss_latency_hist::stdev 17.977211 -system.ruby.RMW_Read.miss_latency_hist | 65375 99.74% 99.74% | 131 0.20% 99.94% | 11 0.02% 99.95% | 18 0.03% 99.98% | 7 0.01% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65547 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.latency_hist::samples 339654 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.341447 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.777860 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.189753 -system.ruby.Locked_RMW_Read.latency_hist | 339308 99.90% 99.90% | 89 0.03% 99.92% | 236 0.07% 99.99% | 2 0.00% 99.99% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339654 +system.ruby.RMW_Read.miss_latency_hist::samples 65260 +system.ruby.RMW_Read.miss_latency_hist::mean 25.833527 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.149766 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.493474 +system.ruby.RMW_Read.miss_latency_hist | 65087 99.73% 99.73% | 127 0.19% 99.93% | 17 0.03% 99.96% | 15 0.02% 99.98% | 9 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65260 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 +system.ruby.Locked_RMW_Read.latency_hist::samples 339680 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.345204 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780937 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.076413 +system.ruby.Locked_RMW_Read.latency_hist | 339429 99.93% 99.93% | 234 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339680 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300671 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300571 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300671 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300671 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38983 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.400739 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.361163 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.695962 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38637 99.11% 99.11% | 89 0.23% 99.34% | 236 0.61% 99.95% | 2 0.01% 99.95% | 6 0.02% 99.97% | 3 0.01% 99.97% | 2 0.01% 99.98% | 3 0.01% 99.99% | 2 0.01% 99.99% | 3 0.01% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38983 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300571 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300571 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39109 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.369199 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.378025 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.121215 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38858 99.36% 99.36% | 234 0.60% 99.96% | 11 0.03% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 39109 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339654 +system.ruby.Locked_RMW_Write.latency_hist::samples 339680 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339654 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339680 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339680 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 -system.ruby.Directory_Controller.Fetch 178187 0.00% 0.00% -system.ruby.Directory_Controller.Data 97745 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178657 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142629 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 815 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339680 +system.ruby.Directory_Controller.Fetch 177916 0.00% 0.00% +system.ruby.Directory_Controller.Data 97855 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 178363 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 143156 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 809 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15738 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 178187 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 44884 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 44884 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 95548 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1852 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15738 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 178187 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 95548 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1852 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1852 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 815 +system.ruby.Directory_Controller.CleanReplacement 15288 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 177916 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 447 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45301 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 447 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45301 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 96058 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1435 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15288 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 177916 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 96058 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1435 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1435 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 809 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 815 +system.ruby.DMA_Controller.Data | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 809 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 815 +system.ruby.DMA_Controller.READY.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 809 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 815 +system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6103954 40.89% 40.89% | 8824164 59.11% 100.00% -system.ruby.L1Cache_Controller.Load::total 14928118 -system.ruby.L1Cache_Controller.Ifetch | 67859054 53.60% 53.60% | 58743585 46.40% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126602639 -system.ruby.L1Cache_Controller.Store | 5213279 48.82% 48.82% | 5465004 51.18% 100.00% -system.ruby.L1Cache_Controller.Store::total 10678283 -system.ruby.L1Cache_Controller.Inv | 16394 48.51% 48.51% | 17401 51.49% 100.00% -system.ruby.L1Cache_Controller.Inv::total 33795 -system.ruby.L1Cache_Controller.L1_Replacement | 832783 31.89% 31.89% | 1778531 68.11% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2611314 -system.ruby.L1Cache_Controller.Fwd_GETX | 12220 50.79% 50.79% | 11839 49.21% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 24059 -system.ruby.L1Cache_Controller.Fwd_GETS | 14364 56.68% 56.68% | 10979 43.32% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25343 +system.ruby.L1Cache_Controller.Load | 6268725 41.74% 41.74% | 8749004 58.26% 100.00% +system.ruby.L1Cache_Controller.Load::total 15017729 +system.ruby.L1Cache_Controller.Ifetch | 68906101 54.22% 54.22% | 58187014 45.78% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 127093115 +system.ruby.L1Cache_Controller.Store | 5364359 50.02% 50.02% | 5359895 49.98% 100.00% +system.ruby.L1Cache_Controller.Store::total 10724254 +system.ruby.L1Cache_Controller.Inv | 15938 47.70% 47.70% | 17476 52.30% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33414 +system.ruby.L1Cache_Controller.L1_Replacement | 827888 31.76% 31.76% | 1778547 68.24% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606435 +system.ruby.L1Cache_Controller.Fwd_GETX | 12260 51.09% 51.09% | 11738 48.91% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23998 +system.ruby.L1Cache_Controller.Fwd_GETS | 14169 56.03% 56.03% | 11118 43.97% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25287 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% -system.ruby.L1Cache_Controller.Data::total 1824 -system.ruby.L1Cache_Controller.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1283110 -system.ruby.L1Cache_Controller.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25347 -system.ruby.L1Cache_Controller.Data_all_Acks | 582883 43.69% 43.69% | 751335 56.31% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1334218 -system.ruby.L1Cache_Controller.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22252 -system.ruby.L1Cache_Controller.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 24076 -system.ruby.L1Cache_Controller.WB_Ack | 468087 27.72% 27.72% | 1220443 72.28% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1688530 -system.ruby.L1Cache_Controller.NP.Load | 281209 20.47% 20.47% | 1092251 79.53% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1373460 -system.ruby.L1Cache_Controller.NP.Ifetch | 328766 40.20% 40.20% | 488985 59.80% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817751 -system.ruby.L1Cache_Controller.NP.Store | 223831 53.02% 53.02% | 198319 46.98% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 422150 -system.ruby.L1Cache_Controller.NP.Inv | 5086 54.54% 54.54% | 4239 45.46% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9325 -system.ruby.L1Cache_Controller.I.Load | 8631 45.67% 45.67% | 10269 54.33% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18900 -system.ruby.L1Cache_Controller.I.Ifetch | 106 16.23% 16.23% | 547 83.77% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 653 -system.ruby.L1Cache_Controller.I.Store | 5805 50.11% 50.11% | 5779 49.89% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11584 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8985 51.90% 51.90% | 8328 48.10% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17313 -system.ruby.L1Cache_Controller.S.Load | 530372 50.22% 50.22% | 525759 49.78% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1056131 -system.ruby.L1Cache_Controller.S.Ifetch | 67530179 53.69% 53.69% | 58254050 46.31% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125784229 -system.ruby.L1Cache_Controller.S.Store | 12098 54.37% 54.37% | 10155 45.63% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22253 -system.ruby.L1Cache_Controller.S.Inv | 11044 46.05% 46.05% | 12940 53.95% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23984 -system.ruby.L1Cache_Controller.S.L1_Replacement | 355711 39.28% 39.28% | 549760 60.72% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 905471 -system.ruby.L1Cache_Controller.E.Load | 1138534 29.37% 29.37% | 2737774 70.63% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3876308 -system.ruby.L1Cache_Controller.E.Store | 81127 48.65% 48.65% | 85645 51.35% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166772 -system.ruby.L1Cache_Controller.E.Inv | 48 57.83% 57.83% | 35 42.17% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 83 -system.ruby.L1Cache_Controller.E.L1_Replacement | 171015 15.36% 15.36% | 942391 84.64% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1113406 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 278 59.40% 59.40% | 190 40.60% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 468 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1045 48.60% 48.60% | 1105 51.40% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2150 -system.ruby.L1Cache_Controller.M.Load | 4145208 48.18% 48.18% | 4458111 51.82% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8603319 -system.ruby.L1Cache_Controller.M.Store | 4890418 48.63% 48.63% | 5165106 51.37% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10055524 -system.ruby.L1Cache_Controller.M.Inv | 216 53.73% 53.73% | 186 46.27% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 402 -system.ruby.L1Cache_Controller.M.L1_Replacement | 297072 51.65% 51.65% | 278052 48.35% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 575124 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11941 50.62% 50.62% | 11649 49.38% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23590 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13319 57.43% 57.43% | 9874 42.57% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23193 +system.ruby.L1Cache_Controller.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% +system.ruby.L1Cache_Controller.Data::total 1855 +system.ruby.L1Cache_Controller.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1282695 +system.ruby.L1Cache_Controller.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25291 +system.ruby.L1Cache_Controller.Data_all_Acks | 578454 43.51% 43.51% | 751132 56.49% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1329586 +system.ruby.L1Cache_Controller.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22150 +system.ruby.L1Cache_Controller.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24005 +system.ruby.L1Cache_Controller.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1687383 +system.ruby.L1Cache_Controller.NP.Load | 280457 20.44% 20.44% | 1091772 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1372229 +system.ruby.L1Cache_Controller.NP.Ifetch | 323032 39.65% 39.65% | 491723 60.35% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 814755 +system.ruby.L1Cache_Controller.NP.Store | 225423 53.48% 53.48% | 196076 46.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421499 +system.ruby.L1Cache_Controller.NP.Inv | 4849 53.95% 53.95% | 4139 46.05% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8988 +system.ruby.L1Cache_Controller.I.Load | 8492 45.24% 45.24% | 10279 54.76% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18771 +system.ruby.L1Cache_Controller.I.Ifetch | 112 15.86% 15.86% | 594 84.14% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 706 +system.ruby.L1Cache_Controller.I.Store | 5744 50.09% 50.09% | 5723 49.91% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11467 +system.ruby.L1Cache_Controller.I.L1_Replacement | 9001 51.76% 51.76% | 8389 48.24% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17390 +system.ruby.L1Cache_Controller.S.Load | 552961 51.86% 51.86% | 513218 48.14% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1066179 +system.ruby.L1Cache_Controller.S.Ifetch | 68582952 54.31% 54.31% | 57694696 45.69% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126277648 +system.ruby.L1Cache_Controller.S.Store | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22150 +system.ruby.L1Cache_Controller.S.Inv | 10866 45.32% 45.32% | 13108 54.68% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 23974 +system.ruby.L1Cache_Controller.S.L1_Replacement | 349852 38.80% 38.80% | 551810 61.20% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 901662 +system.ruby.L1Cache_Controller.E.Load | 1151502 29.73% 29.73% | 2721068 70.27% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3872570 +system.ruby.L1Cache_Controller.E.Store | 80746 48.37% 48.37% | 86187 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166933 +system.ruby.L1Cache_Controller.E.Inv | 47 57.32% 57.32% | 35 42.68% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 82 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170526 15.32% 15.32% | 942229 84.68% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1112755 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 332 72.81% 72.81% | 124 27.19% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 456 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 992 45.23% 45.23% | 1201 54.77% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2193 +system.ruby.L1Cache_Controller.M.Load | 4275313 49.21% 49.21% | 4412667 50.79% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8687980 +system.ruby.L1Cache_Controller.M.Store | 5040297 49.89% 49.89% | 5061908 50.11% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10102205 +system.ruby.L1Cache_Controller.M.Inv | 176 47.57% 47.57% | 194 52.43% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 370 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298509 51.95% 51.95% | 276119 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574628 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11928 50.67% 50.67% | 11614 49.33% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23542 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13177 57.06% 57.06% | 9917 42.94% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23094 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1283110 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25347 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 354040 39.24% 39.24% | 548267 60.76% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902307 -system.ruby.L1Cache_Controller.IM.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1824 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 228843 52.98% 52.98% | 203068 47.02% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431911 -system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 1 -system.ruby.L1Cache_Controller.SM.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22252 -system.ruby.L1Cache_Controller.SM.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 24076 -system.ruby.L1Cache_Controller.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1282695 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25291 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348115 38.75% 38.75% | 550360 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898475 +system.ruby.L1Cache_Controller.IM.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1855 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230339 53.43% 53.43% | 200772 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431111 +system.ruby.L1Cache_Controller.SM.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22150 +system.ruby.L1Cache_Controller.SM.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24005 +system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 468086 27.72% 27.72% | 1220443 72.28% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1688529 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1 -system.ruby.L2Cache_Controller.L1_GET_INSTR 818404 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1392538 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 433736 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22253 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1688530 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95493 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15793 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 178187 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113483 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23599 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2150 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1627 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7690 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25347 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1739097 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 4394 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16549 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34274 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127364 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801825 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83907 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1933 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22252 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 275 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7330 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 2 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1687383 +system.ruby.L2Cache_Controller.L1_GET_INSTR 815461 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1391156 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 432966 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22150 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1687383 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95998 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15348 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 177916 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 113143 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23468 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2193 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1505 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7534 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25291 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1737811 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 3594 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16427 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 34220 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127269 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799004 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 83018 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1958 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22150 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 257 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7192 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1248836 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 280379 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95073 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8368 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1950 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1248475 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 279741 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95619 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8056 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1564 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25343 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 24059 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1688529 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 145 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 95 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 245 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113483 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1950 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 347 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 245 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25287 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23998 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1687383 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 122 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 113143 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1564 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 310 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 42 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1351 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7330 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 276 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 277 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 2 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34274 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16549 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127364 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 131 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24185 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 47 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1714912 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23196 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2149 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25345 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1245 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7192 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 260 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 260 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 34220 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16427 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127269 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 115 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24108 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 41 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1713703 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23085 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2191 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 13 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25276 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 767b8b8bc..5315d8c71 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.142213 # Number of seconds simulated -sim_ticks 5142212861500 # Number of ticks simulated -final_tick 5142212861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144107 # Number of seconds simulated +sim_ticks 5144107123500 # Number of ticks simulated +final_tick 5144107123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316771 # Simulator instruction rate (inst/s) -host_op_rate 629731 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6695034949 # Simulator tick rate (ticks/s) -host_mem_usage 960996 # Number of bytes of host memory used -host_seconds 768.06 # Real time elapsed on the host -sim_insts 243300298 # Number of instructions simulated -sim_ops 483673350 # Number of ops (including micro ops) simulated +host_inst_rate 180241 # Simulator instruction rate (inst/s) +host_op_rate 358324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3805676977 # Simulator tick rate (ticks/s) +host_mem_usage 1000324 # Number of bytes of host memory used +host_seconds 1351.69 # Real time elapsed on the host +sim_insts 243630211 # Number of instructions simulated +sim_ops 484343866 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 424320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5246720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 435328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5271168 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 163840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2163392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 379584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2979328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 167488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2239424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 369088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2863936 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11387840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 424320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 163840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 379584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9172160 # Number of bytes written to this memory -system.physmem.bytes_written::total 9172160 # Number of bytes written to this memory +system.physmem.bytes_read::total 11377408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 435328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 167488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 369088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 971904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9177088 # Number of bytes written to this memory +system.physmem.bytes_written::total 9177088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 82362 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2560 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 46552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 36 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44749 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177935 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143315 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143315 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177772 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143392 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143392 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1020323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 84627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1024700 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 420712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 579386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2214580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1783699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1783699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1783699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 435338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 556741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2211736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 84627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1784000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1784000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1784000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1020323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 84627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1024700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 420712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 579386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3998279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88878 # Number of read requests accepted -system.physmem.writeReqs 113942 # Number of write requests accepted -system.physmem.readBursts 88878 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 113942 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5683264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4928 # Total number of bytes read from write queue -system.physmem.bytesWritten 7207296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5688192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7292288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 77 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1310 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 940 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5243 # Per bank write bursts -system.physmem.perBankRdBursts::1 4719 # Per bank write bursts -system.physmem.perBankRdBursts::2 5104 # Per bank write bursts -system.physmem.perBankRdBursts::3 5729 # Per bank write bursts -system.physmem.perBankRdBursts::4 5898 # Per bank write bursts -system.physmem.perBankRdBursts::5 5027 # Per bank write bursts -system.physmem.perBankRdBursts::6 5470 # Per bank write bursts -system.physmem.perBankRdBursts::7 5567 # Per bank write bursts -system.physmem.perBankRdBursts::8 5651 # Per bank write bursts -system.physmem.perBankRdBursts::9 5723 # Per bank write bursts -system.physmem.perBankRdBursts::10 5167 # Per bank write bursts -system.physmem.perBankRdBursts::11 5483 # Per bank write bursts -system.physmem.perBankRdBursts::12 5886 # Per bank write bursts -system.physmem.perBankRdBursts::13 6693 # Per bank write bursts -system.physmem.perBankRdBursts::14 5960 # Per bank write bursts -system.physmem.perBankRdBursts::15 5481 # Per bank write bursts -system.physmem.perBankWrBursts::0 7238 # Per bank write bursts -system.physmem.perBankWrBursts::1 6716 # Per bank write bursts -system.physmem.perBankWrBursts::2 7069 # Per bank write bursts -system.physmem.perBankWrBursts::3 6723 # Per bank write bursts -system.physmem.perBankWrBursts::4 7013 # Per bank write bursts -system.physmem.perBankWrBursts::5 6703 # Per bank write bursts -system.physmem.perBankWrBursts::6 6619 # Per bank write bursts -system.physmem.perBankWrBursts::7 7556 # Per bank write bursts -system.physmem.perBankWrBursts::8 6486 # Per bank write bursts -system.physmem.perBankWrBursts::9 6985 # Per bank write bursts -system.physmem.perBankWrBursts::10 6508 # Per bank write bursts -system.physmem.perBankWrBursts::11 6763 # Per bank write bursts -system.physmem.perBankWrBursts::12 7496 # Per bank write bursts -system.physmem.perBankWrBursts::13 7338 # Per bank write bursts -system.physmem.perBankWrBursts::14 7696 # Per bank write bursts -system.physmem.perBankWrBursts::15 7705 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 32559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 435338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 71750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 556741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3995736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 88604 # Number of read requests accepted +system.physmem.writeReqs 101715 # Number of write requests accepted +system.physmem.readBursts 88604 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 101715 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5666496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4160 # Total number of bytes read from write queue +system.physmem.bytesWritten 6448384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5670656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6509760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 65 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 959 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 894 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5172 # Per bank write bursts +system.physmem.perBankRdBursts::1 4675 # Per bank write bursts +system.physmem.perBankRdBursts::2 4614 # Per bank write bursts +system.physmem.perBankRdBursts::3 5517 # Per bank write bursts +system.physmem.perBankRdBursts::4 6171 # Per bank write bursts +system.physmem.perBankRdBursts::5 5192 # Per bank write bursts +system.physmem.perBankRdBursts::6 5194 # Per bank write bursts +system.physmem.perBankRdBursts::7 5097 # Per bank write bursts +system.physmem.perBankRdBursts::8 5481 # Per bank write bursts +system.physmem.perBankRdBursts::9 5563 # Per bank write bursts +system.physmem.perBankRdBursts::10 5214 # Per bank write bursts +system.physmem.perBankRdBursts::11 5694 # Per bank write bursts +system.physmem.perBankRdBursts::12 5834 # Per bank write bursts +system.physmem.perBankRdBursts::13 6887 # Per bank write bursts +system.physmem.perBankRdBursts::14 6277 # Per bank write bursts +system.physmem.perBankRdBursts::15 5957 # Per bank write bursts +system.physmem.perBankWrBursts::0 6561 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 5964 # Per bank write bursts +system.physmem.perBankWrBursts::3 5948 # Per bank write bursts +system.physmem.perBankWrBursts::4 7233 # Per bank write bursts +system.physmem.perBankWrBursts::5 6043 # Per bank write bursts +system.physmem.perBankWrBursts::6 6495 # Per bank write bursts +system.physmem.perBankWrBursts::7 6502 # Per bank write bursts +system.physmem.perBankWrBursts::8 5629 # Per bank write bursts +system.physmem.perBankWrBursts::9 6174 # Per bank write bursts +system.physmem.perBankWrBursts::10 5473 # Per bank write bursts +system.physmem.perBankWrBursts::11 6467 # Per bank write bursts +system.physmem.perBankWrBursts::12 6126 # Per bank write bursts +system.physmem.perBankWrBursts::13 6747 # Per bank write bursts +system.physmem.perBankWrBursts::14 6614 # Per bank write bursts +system.physmem.perBankWrBursts::15 6682 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5141212728000 # Total gap between requests +system.physmem.totGap 5140299284500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88878 # Read request sizes (log2) +system.physmem.readPktSize::6 88604 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 113942 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 101715 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -165,479 +165,455 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::19 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.951538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.940976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.089751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16126 38.90% 38.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9571 23.09% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4083 9.85% 71.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2278 5.50% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1502 3.62% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1068 2.58% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 718 1.73% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 598 1.44% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5511 13.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41455 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.493423 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 181.058580 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4330 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 40184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.485168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.308895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.181387 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15726 39.13% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9443 23.50% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4063 10.11% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2232 5.55% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1531 3.81% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1042 2.59% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 702 1.75% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 613 1.53% 87.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4832 12.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40184 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.412092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 185.359125 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4132 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4333 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.989845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.182522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.410005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 65 1.50% 1.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.14% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.16% 1.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3364 77.64% 79.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 26 0.60% 80.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.53% 80.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 179 4.13% 84.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 85 1.96% 86.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 35 0.81% 87.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.58% 88.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.53% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 2.70% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.16% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.09% 91.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.09% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 14 0.32% 91.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.21% 92.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.23% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.81% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 78 1.80% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.05% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.09% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 7 0.16% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 92 2.12% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.16% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 24 0.55% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.07% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 4 0.09% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.32% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.09% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.12% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.16% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 6 0.14% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.07% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.07% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4333 # Writes before turning the bus around for reads -system.physmem.totQLat 976769250 # Total ticks spent queuing -system.physmem.totMemAccLat 2641788000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 444005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10999.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.366626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.429404 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.022185 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 69 1.67% 1.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 9 0.22% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 3347 80.94% 82.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 165 3.99% 86.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 114 2.76% 89.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 31 0.75% 90.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 101 2.44% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.27% 93.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 26 0.63% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 40 0.97% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 54 1.31% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 10 0.24% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 75 1.81% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.19% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 18 0.44% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.17% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.36% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 12 0.29% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 5 0.12% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.10% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4135 # Writes before turning the bus around for reads +system.physmem.totQLat 956383499 # Total ticks spent queuing +system.physmem.totMemAccLat 2616489749 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 442695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10801.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29749.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29551.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.09 # Average write queue length when enqueuing -system.physmem.readRowHits 70835 # Number of row buffer hits during reads -system.physmem.writeRowHits 89124 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.13 # Row buffer hit rate for writes -system.physmem.avgGap 25348647.71 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153097560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83370375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 333504600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 360527760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95043085920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2239708824000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2586157872855 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.947189 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3689335375500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128054940000 # Time in different power states +system.physmem.avgWrQLen 11.42 # Average write queue length when enqueuing +system.physmem.readRowHits 70796 # Number of row buffer hits during reads +system.physmem.writeRowHits 78315 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.73 # Row buffer hit rate for writes +system.physmem.avgGap 27008860.31 # Average gap between requests +system.physmem.pageHitRate 78.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 147178080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 80086875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 324729600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 329469120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94792163085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2243751115500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2589991237140 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.838461 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3691094925500 # Time in different power states +system.physmem_0.memoryStateTime::REF 128101480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17909174750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17513749500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 160302240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87313875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 359135400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 369210960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95555045385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2233887892500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580894363000 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.132718 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3688582993750 # Time in different power states -system.physmem_1.memoryStateTime::REF 128054940000 # Time in different power states +system.physmem_1.actEnergy 156612960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 365874600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 323429760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95660983305 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2237004864750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2584163561130 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.053818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3689804823000 # Time in different power states +system.physmem_1.memoryStateTime::REF 128101480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18657353000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18778765250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 905515045 # number of cpu cycles simulated +system.cpu0.numCycles 906748886 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71354866 # Number of instructions committed -system.cpu0.committedOps 145718889 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 133579753 # Number of integer alu accesses +system.cpu0.committedInsts 71802590 # Number of instructions committed +system.cpu0.committedOps 146381299 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134255761 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 936391 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14189595 # number of instructions that are conditional controls -system.cpu0.num_int_insts 133579753 # number of integer instructions +system.cpu0.num_func_calls 943296 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14239563 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134255761 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 244625676 # number of times the integer registers were read -system.cpu0.num_int_register_writes 114972528 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246209877 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115427878 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83222516 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55621681 # number of times the CC registers were written -system.cpu0.num_mem_refs 13385296 # number of memory refs -system.cpu0.num_load_insts 10015665 # Number of load instructions -system.cpu0.num_store_insts 3369631 # Number of store instructions -system.cpu0.num_idle_cycles 858514977.989050 # Number of idle cycles -system.cpu0.num_busy_cycles 47000067.010950 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051904 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948096 # Percentage of idle cycles -system.cpu0.Branches 15470512 # Number of branches fetched -system.cpu0.op_class::No_OpClass 89016 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132139784 90.68% 90.74% # Class of executed instruction -system.cpu0.op_class::IntMult 57056 0.04% 90.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 49774 0.03% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::MemRead 10013957 6.87% 97.69% # Class of executed instruction -system.cpu0.op_class::MemWrite 3369631 2.31% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83592437 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55838323 # number of times the CC registers were written +system.cpu0.num_mem_refs 13658115 # number of memory refs +system.cpu0.num_load_insts 10127652 # Number of load instructions +system.cpu0.num_store_insts 3530463 # Number of store instructions +system.cpu0.num_idle_cycles 859556134.264708 # Number of idle cycles +system.cpu0.num_busy_cycles 47192751.735292 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052046 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947954 # Percentage of idle cycles +system.cpu0.Branches 15533640 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89870 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132527069 90.54% 90.60% # Class of executed instruction +system.cpu0.op_class::IntMult 58535 0.04% 90.64% # Class of executed instruction +system.cpu0.op_class::IntDiv 49919 0.03% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::MemRead 10125945 6.92% 97.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 3530463 2.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 145719218 # Class of executed instruction +system.cpu0.op_class::total 146381801 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638885 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999440 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19690308 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639397 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.010701 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1639020 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19713831 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1639532 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.024060 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.361524 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 276.707159 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.930757 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.252659 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.540444 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.206896 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.995226 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 275.897813 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 106.106411 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.253897 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.538863 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.207239 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 235 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88564731 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88564731 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4814748 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2752692 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3969504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11536944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3244156 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1918293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2929310 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8091759 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19629 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10883 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59798 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8058904 # number of demand (read+write) hits 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accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3065079 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8417769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 168124 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76224 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 222085 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466433 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8537198 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4908042 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7819657 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21264897 # number of demand (read+write) accesses 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66279 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 189615 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406381 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 488043 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 238736 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 898883 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1625662 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 638530 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 305015 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1088498 # number of overall misses +system.cpu0.dcache.overall_misses::total 2032043 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2329828500 # number of ReadReq miss cycles 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mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14779.776295 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14497.486636 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19240.072062 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17321.901183 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17927.798001 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18030.403431 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16645.541223 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17064.427841 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable 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4645372892 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6749090142 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2103717250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4645372892 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6749090142 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2103717250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4645372892 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6749090142 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004220 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004220 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004220 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.872259 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23039 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23039 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23039 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23039 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23039 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23039 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 172473 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 384626 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 557099 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 172473 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 384626 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 557099 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 172473 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 384626 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 557099 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2070011500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4726513433 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6796524933 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2070011500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4726513433 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6796524933 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2070011500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4726513433 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6796524933 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004257 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004257 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004257 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608019043 # number of cpu cycles simulated +system.cpu1.numCycles 2608020264 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 36458068 # Number of instructions committed -system.cpu1.committedOps 70720299 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 65779411 # Number of integer alu accesses +system.cpu1.committedInsts 35983855 # Number of instructions committed +system.cpu1.committedOps 69821911 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64889046 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 521390 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6639276 # number of instructions that are conditional controls -system.cpu1.num_int_insts 65779411 # number of integer instructions +system.cpu1.num_func_calls 503439 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6569343 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64889046 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 122190876 # number of times the integer registers were read -system.cpu1.num_int_register_writes 56554100 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120388172 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55814326 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 37054979 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27544073 # number of times the CC registers were written -system.cpu1.num_mem_refs 5171486 # number of memory refs -system.cpu1.num_load_insts 3182631 # Number of load instructions -system.cpu1.num_store_insts 1988855 # Number of store instructions -system.cpu1.num_idle_cycles 2476913850.669656 # Number of idle cycles -system.cpu1.num_busy_cycles 131105192.330343 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050270 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949730 # Percentage of idle cycles -system.cpu1.Branches 7356329 # Number of branches fetched -system.cpu1.op_class::No_OpClass 36814 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 65455015 92.55% 92.61% # Class of executed instruction -system.cpu1.op_class::IntMult 34008 0.05% 92.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 24962 0.04% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::MemRead 3181010 4.50% 97.19% # Class of executed instruction -system.cpu1.op_class::MemWrite 1988855 2.81% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36581725 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27247591 # number of times the CC registers were written +system.cpu1.num_mem_refs 4980693 # number of memory refs +system.cpu1.num_load_insts 3049501 # Number of load instructions +system.cpu1.num_store_insts 1931192 # Number of store instructions +system.cpu1.num_idle_cycles 2477411639.002949 # Number of idle cycles +system.cpu1.num_busy_cycles 130608624.997051 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050080 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949920 # Percentage of idle cycles +system.cpu1.Branches 7257729 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34768 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64752658 92.74% 92.79% # Class of executed instruction +system.cpu1.op_class::IntMult 32117 0.05% 92.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 23661 0.03% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::MemRead 3047883 4.37% 97.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 1931192 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70720664 # Class of executed instruction +system.cpu1.op_class::total 69822279 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28980045 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28980045 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 316258 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26301179 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25662962 # Number of BTB hits +system.cpu2.branchPred.lookups 29145274 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29145274 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 322260 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26440523 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25789579 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.573428 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 575120 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 62760 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153675594 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.538082 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 584080 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63924 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153878746 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10522056 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142983634 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28980045 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26238082 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141648223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 664532 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102750 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5712 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8254 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 65359 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 18 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 587 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3403920 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 164909 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3818 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152684574 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.843447 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.027165 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10764874 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143615831 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29145274 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26373659 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141609884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 675175 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 95795 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 6373 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7380 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 61565 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 20 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 458 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3473911 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167436 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3564 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152883285 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.850280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.030640 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97834881 64.08% 64.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 827461 0.54% 64.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23508780 15.40% 80.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 590429 0.39% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 809590 0.53% 80.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 824910 0.54% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 565945 0.37% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 689592 0.45% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27032986 17.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97765346 63.95% 63.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 837203 0.55% 64.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23601513 15.44% 79.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 591420 0.39% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 819374 0.54% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 838216 0.55% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 577391 0.38% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 693159 0.45% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27159663 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152684574 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.188579 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.930425 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9666714 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93465476 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23018277 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4894255 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 332917 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278595760 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 332917 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11754676 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75764311 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4472306 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25597731 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13455764 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277400530 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 224282 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5843297 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 52985 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 5514893 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331330378 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605053013 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371514373 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 319639627 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11690749 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 161038 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 162632 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24003573 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6435164 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3706636 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 363903 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 318629 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275503234 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 421288 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273595538 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103309 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8356083 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12887842 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64640 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152684574 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.791900 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.394187 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152883285 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189404 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.933305 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9834703 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93251994 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 21466938 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4884733 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 338239 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279965546 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 338239 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11923429 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 75993663 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4610925 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24032799 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12877614 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278749384 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 221936 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5866894 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 51314 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4911660 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 333127303 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 607942521 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 373256279 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 196 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320819170 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12308133 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 159156 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 160655 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23900033 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6505190 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3599973 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 377004 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 316512 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276808275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 423236 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274695170 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 101004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8754938 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13676659 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 65243 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152883285 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.796764 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.395757 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90392452 59.20% 59.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5451363 3.57% 62.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3935423 2.58% 65.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3565723 2.34% 67.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22424664 14.69% 82.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2492768 1.63% 84.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23751475 15.56% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 460834 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 209872 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90394017 59.13% 59.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5385946 3.52% 62.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3961954 2.59% 65.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3603407 2.36% 67.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22510778 14.72% 82.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2513602 1.64% 83.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23841558 15.59% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 461559 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 210464 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152684574 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152883285 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1676714 85.59% 85.59% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 85.59% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 168 0.01% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 221197 11.29% 96.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 60976 3.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1679391 85.86% 85.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 6 0.00% 85.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 133 0.01% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 216471 11.07% 96.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 59961 3.07% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 82248 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263185371 96.20% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54901 0.02% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48803 0.02% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6793041 2.48% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3431174 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81534 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264357889 96.24% 96.27% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 55368 0.02% 96.29% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50253 0.02% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 68 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6828846 2.49% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3321212 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273595538 # Type of FU issued -system.cpu2.iq.rate 1.780345 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1959055 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007160 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 701937961 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284284863 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272009603 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 52 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275472321 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 698574 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274695170 # Type of FU issued +system.cpu2.iq.rate 1.785140 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1955962 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007120 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704330322 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285990572 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273107568 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 106 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 276569466 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 697735 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1169867 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6207 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4815 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 637978 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1221587 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6074 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4844 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 639616 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755628 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24889 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 755983 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21219 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 332917 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70606528 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1760004 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275924522 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 40123 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6435186 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3706636 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 246888 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 186471 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1275738 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4815 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 176824 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 191426 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 368250 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273027006 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6657386 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 516016 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 338239 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70808815 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1780684 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277231511 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 42116 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6505190 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3599973 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 246009 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 189602 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1292389 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4844 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 181953 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 192646 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374599 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274123146 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6692505 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 521898 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10001726 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27723980 # Number of branches executed -system.cpu2.iew.exec_stores 3344340 # Number of stores executed -system.cpu2.iew.exec_rate 1.776645 # Inst execution rate -system.cpu2.iew.wb_sent 272834661 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272009615 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 211997747 # num instructions producing a value -system.cpu2.iew.wb_consumers 347754146 # num instructions consuming a value +system.cpu2.iew.exec_refs 9929733 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27833627 # Number of branches executed +system.cpu2.iew.exec_stores 3237228 # Number of stores executed +system.cpu2.iew.exec_rate 1.781423 # Inst execution rate +system.cpu2.iew.wb_sent 273932637 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273107674 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213006118 # num instructions producing a value +system.cpu2.iew.wb_consumers 349346589 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.770025 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609620 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.774824 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609727 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8688913 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356648 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 319605 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151378980 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.765332 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.647504 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9088854 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357993 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325291 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 151524726 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.769617 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.649272 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94244642 62.26% 62.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4276340 2.82% 65.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1271564 0.84% 65.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24442364 16.15% 82.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1016704 0.67% 82.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 679552 0.45% 83.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 473445 0.31% 83.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23012596 15.20% 98.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1961773 1.30% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94238602 62.19% 62.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4221946 2.79% 64.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1274040 0.84% 65.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24556134 16.21% 82.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1017367 0.67% 82.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 681486 0.45% 83.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 477034 0.31% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23101810 15.25% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1956307 1.29% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151378980 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135487364 # Number of instructions committed -system.cpu2.commit.committedOps 267234162 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 151524726 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135843766 # Number of instructions committed +system.cpu2.commit.committedOps 268140656 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8333976 # Number of memory references committed -system.cpu2.commit.loads 5265318 # Number of loads committed -system.cpu2.commit.membars 160044 # Number of memory barriers committed -system.cpu2.commit.branches 27319158 # Number of branches committed -system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244126615 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428007 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46777 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 258753265 96.83% 96.84% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52699 0.02% 96.86% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 47480 0.02% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5265283 1.97% 98.85% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3068658 1.15% 100.00% # Class of committed instruction +system.cpu2.commit.refs 8243960 # Number of memory references committed +system.cpu2.commit.loads 5283603 # Number of loads committed +system.cpu2.commit.membars 162116 # Number of memory barriers committed +system.cpu2.commit.branches 27422801 # Number of branches committed +system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 244944567 # Number of committed integer instructions. +system.cpu2.commit.function_calls 433353 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 47848 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259747107 96.87% 96.89% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 53065 0.02% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48699 0.02% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5283564 1.97% 98.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2960357 1.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267234162 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1961773 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268140656 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1956307 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425310506 # The number of ROB reads -system.cpu2.rob.rob_writes 553158006 # The number of ROB writes -system.cpu2.timesIdled 113704 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 991020 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4914719574 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135487364 # Number of Instructions Simulated -system.cpu2.committedOps 267234162 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.134243 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.134243 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.881645 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.881645 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363574277 # number of integer regfile reads -system.cpu2.int_regfile_writes 217910153 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72980 # number of floating regfile reads +system.cpu2.rob.rob_reads 426769551 # The number of ROB reads +system.cpu2.rob.rob_writes 555823820 # The number of ROB writes +system.cpu2.timesIdled 116899 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 995461 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4917307163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135843766 # Number of Instructions Simulated +system.cpu2.committedOps 268140656 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.132763 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.132763 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882797 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882797 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364780652 # number of integer regfile reads +system.cpu2.int_regfile_writes 218921020 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73130 # number of floating regfile reads system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138812774 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106705933 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88766274 # number of misc regfile reads -system.cpu2.misc_regfile_writes 139734 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554581 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554581 # Transaction distribution -system.iobus.trans_dist::WriteReq 57732 # Transaction distribution -system.iobus.trans_dist::WriteResp 11012 # Transaction distribution +system.cpu2.cc_regfile_reads 139296056 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107100465 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89036481 # number of misc regfile reads +system.cpu2.misc_regfile_writes 137201 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554570 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554570 # Transaction distribution +system.iobus.trans_dist::WriteReq 57725 # Transaction distribution +system.iobus.trans_dist::WriteResp 11005 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1688 # Transaction distribution -system.iobus.trans_dist::MessageResp 1688 # Transaction distribution +system.iobus.trans_dist::MessageReq 1681 # Transaction distribution +system.iobus.trans_dist::MessageResp 1681 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3376 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3376 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7228002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129348 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227952 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605370 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2500128 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3570873 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2588568 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3583000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4563000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1230,64 +1207,64 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 318000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 404000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10022000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10340000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 273258249 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 221126240 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 301483000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 302697000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28884002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 28304753 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1044000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1088000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47568 # number of replacements -system.iocache.tags.tagsinuse 0.106184 # Cycle average of tags in use +system.iocache.tags.replacements 47566 # number of replacements +system.iocache.tags.tagsinuse 0.112009 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571396009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106184 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571390009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112009 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007001 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007001 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428607 # Number of tag accesses -system.iocache.tags.data_accesses 428607 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses +system.iocache.tags.tag_accesses 428589 # Number of tag accesses +system.iocache.tags.data_accesses 428589 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses +system.iocache.ReadReq_misses::total 901 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses -system.iocache.demand_misses::total 903 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses -system.iocache.overall_misses::total 903 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21110907 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21110907 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7547175340 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 7547175340 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 21110907 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21110907 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 21110907 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21110907 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses +system.iocache.demand_misses::total 901 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses +system.iocache.overall_misses::total 901 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132764027 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132764027 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6059046460 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6059046460 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132764027 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132764027 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132764027 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132764027 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1296,325 +1273,325 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 23378.634551 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 161540.568065 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 161540.568065 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 23378.634551 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 23378.634551 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 42516 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 147351.861265 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147351.861265 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147351.861265 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34598 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5560 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4497 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.646763 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.693573 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 186 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28512 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28512 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 186 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 186 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 186 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 186 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11438907 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6064547344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6064547344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11438907 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11438907 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.205980 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.610274 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.610274 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.205980 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.205980 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61499.500000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212701.576319 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212701.576319 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 738 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 23008 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 23008 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 738 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 738 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 738 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94361527 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 4862624466 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4862624466 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 94361527 # number of demand (read+write) MSHR miss cycles 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0.819090 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency 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requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1719.764589 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5034.334216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 365.232722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1988.868841 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.547985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 847.123033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3617.112946 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781971 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51221.575879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131319 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1714.525389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5051.845543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 364.783966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1988.075845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.500719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 853.175626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3622.680869 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781579 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026242 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076818 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.026162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077085 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005573 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030348 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000100 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.012926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989172 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64209 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7713 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52703 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979752 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33891817 # Number of tag accesses -system.l2c.tags.data_accesses 33891817 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20180 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10473 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 308266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 489820 # number of ReadReq hits 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of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 306104 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6423 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 169856 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 227750 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 59393 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 378835 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 595825 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2292802 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1548383 # number of Writeback hits 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# number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6781 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 172994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 266251 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 57791 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13812 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 666194 # number of demand (read+write) hits -system.l2c.demand_hits::total 2449192 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20180 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10475 # number of overall hits -system.l2c.overall_hits::cpu0.inst 308266 # number of overall hits -system.l2c.overall_hits::cpu0.data 543723 # number of overall hits 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# average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61090.618747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59851.829331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency 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+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157432500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 321524500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 377524500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 667618251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1526670750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3450773 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4577444 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 8028217 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1690819298 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2050981877 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3741801175 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 157432500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2012343798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 377524500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2718600128 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5268471925 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 157432500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2012343798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 377524500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2718600128 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5268471925 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27931457000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30246385500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58177842500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 534826000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 653150000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1187976000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28466283000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30899535500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59365818500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.016889 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010133 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800562 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.815356 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.451792 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375063 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.222861 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033686 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033686 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63492.199842 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65222.572392 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64359.459972 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12107.975439 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10263.327354 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10982.512996 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56050.497182 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58959.980366 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57608.713742 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1758,70 +1735,70 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5122016 # Transaction distribution -system.membus.trans_dist::ReadResp 5122015 # Transaction distribution -system.membus.trans_dist::WriteReq 13950 # Transaction distribution -system.membus.trans_dist::WriteResp 13950 # Transaction distribution -system.membus.trans_dist::Writeback 143315 # Transaction distribution +system.membus.trans_dist::ReadReq 5122083 # Transaction distribution +system.membus.trans_dist::ReadResp 5122081 # Transaction distribution +system.membus.trans_dist::WriteReq 13936 # Transaction distribution +system.membus.trans_dist::WriteResp 13936 # Transaction distribution +system.membus.trans_dist::Writeback 143392 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1630 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1630 # Transaction distribution -system.membus.trans_dist::ReadExReq 130173 # Transaction distribution -system.membus.trans_dist::ReadExResp 130173 # Transaction distribution -system.membus.trans_dist::MessageReq 1688 # Transaction distribution -system.membus.trans_dist::MessageResp 1688 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3376 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3376 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10630044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10775147 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089593 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17566400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27226843 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6022656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6022656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33256251 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoop_fanout::samples 370715 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 1613 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1613 # Transaction distribution +system.membus.trans_dist::ReadExReq 129914 # Transaction distribution +system.membus.trans_dist::ReadExResp 129914 # Transaction distribution +system.membus.trans_dist::MessageReq 1681 # Transaction distribution +system.membus.trans_dist::MessageResp 1681 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10629668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10774644 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570873 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17560128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27220486 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33242762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 642 # Total snoops (count) +system.membus.snoop_fanout::samples 370612 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370715 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 370612 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370715 # Request fanout histogram -system.membus.reqLayer0.occupancy 161293000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 370612 # Request fanout histogram +system.membus.reqLayer0.occupancy 162893500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314500500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314579500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2088000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2176000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1165884999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1055146498 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1044000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1088000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1714039312 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1708813357 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 30187998 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 29666247 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1831,52 +1808,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7445356 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7445355 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13952 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13952 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548383 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28512 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1653 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1653 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291909 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 211316 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17022848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55474752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213691163 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 265608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 747576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270179099 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 79089 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4261601 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011175 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105119 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7441673 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7441143 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13938 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13938 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548363 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 23008 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291446 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291446 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004999 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17025096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55679680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213700038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 269360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 773664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270422742 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 67345 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4256875 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011187 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105175 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4213978 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47623 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4209254 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4261601 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5362619847 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4256875 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5306720328 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 837000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2486663092 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2510055059 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4974743955 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4923615960 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27294890 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 25531897 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 94899067 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 85751327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index c3e1a1978..75b239bd4 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -161,6 +161,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -518,6 +519,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -584,6 +586,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -633,6 +636,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -641,6 +645,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -714,6 +719,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index fbecda938..519142696 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 1e2ff91f9..3b3cbc058 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 9577cfdf6..4683e5b55 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -161,6 +161,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -518,6 +519,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -584,6 +586,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -633,6 +636,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -641,6 +645,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -714,6 +719,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 156b7eda7..ef4c5e885 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index d1dba8bc2..8766e929e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 36079bdaf..48f81d429 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 1cf904013..50782f925 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index bfaee19bf..fce25a10a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -161,6 +161,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -518,6 +519,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -584,6 +586,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -633,6 +636,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -641,6 +645,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -714,6 +719,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 26fe45507..994d45013 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 4909b25e3..1228cbb9c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 34b146a05..e85225b4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112152 # Number of seconds simulated -sim_ticks 5112152263500 # Number of ticks simulated -final_tick 5112152263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112152301500 # Number of ticks simulated +final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1496341 # Simulator instruction rate (inst/s) -host_op_rate 3063337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38234881791 # Simulator tick rate (ticks/s) -host_mem_usage 596704 # Number of bytes of host memory used -host_seconds 133.70 # Real time elapsed on the host -sim_insts 200066624 # Number of instructions simulated -sim_ops 409580050 # Number of ops (including micro ops) simulated +host_inst_rate 1049184 # Simulator instruction rate (inst/s) +host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26808985343 # Simulator tick rate (ticks/s) +host_mem_usage 640900 # Number of bytes of host memory used +host_seconds 190.69 # Real time elapsed on the host +sim_insts 200066731 # Number of instructions simulated +sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory @@ -50,38 +50,38 @@ system.physmem.bw_total::pc.south_bridge.ide 5546 system.physmem.bw_total::total 4061951 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224308491 # number of cpu cycles simulated +system.cpu.numCycles 10224308568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 200066624 # Number of instructions committed -system.cpu.committedOps 409580050 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374583182 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2308871 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 40001057 # number of instructions that are conditional controls -system.cpu.num_int_insts 374583182 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682688853 # number of times the integer registers were read -system.cpu.num_int_register_writes 323557399 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.committedInsts 200066731 # Number of instructions committed +system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 2308877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls +system.cpu.num_int_insts 374583495 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 682689563 # number of times the integer registers were read +system.cpu.num_int_register_writes 323557658 # number of times the integer registers were written +system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233837170 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157316360 # number of times the CC registers were written -system.cpu.num_mem_refs 35666925 # number of memory refs -system.cpu.num_load_insts 27243229 # Number of load instructions -system.cpu.num_store_insts 8423696 # Number of store instructions -system.cpu.num_idle_cycles 9770324986.701103 # Number of idle cycles -system.cpu.num_busy_cycles 453983504.298896 # Number of busy cycles +system.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written +system.cpu.num_mem_refs 35667022 # number of memory refs +system.cpu.num_load_insts 27243255 # Number of load instructions +system.cpu.num_store_insts 8423767 # Number of store instructions +system.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles +system.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955598 # Percentage of idle cycles -system.cpu.Branches 43152131 # Number of branches fetched -system.cpu.op_class::No_OpClass 172748 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373476362 91.18% 91.23% # Class of executed instruction +system.cpu.Branches 43152159 # Number of branches fetched +system.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 123058 0.03% 91.29% # Class of executed instruction +system.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction @@ -105,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27240640 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8423696 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409581081 # Class of executed instruction +system.cpu.op_class::total 409581402 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1621913 # number of replacements +system.cpu.dcache.tags.replacements 1621902 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20181070 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622425 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.438831 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88836495 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88836495 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12023306 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12023306 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8096585 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8096585 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58898 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58898 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20119891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20119891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20178789 # number of overall hits -system.cpu.dcache.overall_hits::total 20178789 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905254 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905254 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316711 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316711 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402759 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402759 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1221965 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1221965 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624724 # number of overall misses -system.cpu.dcache.overall_misses::total 1624724 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12928560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12928560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8413296 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8413296 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits +system.cpu.dcache.overall_hits::total 20178901 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses +system.cpu.dcache.overall_misses::total 1624713 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21341856 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21341856 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803513 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803513 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037644 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037644 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872420 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872420 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057257 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057257 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074517 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074517 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -176,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535795 # number of writebacks -system.cpu.dcache.writebacks::total 1535795 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535783 # number of writebacks +system.cpu.dcache.writebacks::total 1535783 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7755 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014024 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12942 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7769 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.665851 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454103000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014024 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313376 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313376 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52772 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52772 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12943 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12943 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12943 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12943 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12943 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12943 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8962 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8962 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8962 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8962 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8962 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8962 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21905 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21905 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21905 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21905 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21905 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21905 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409130 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409130 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409130 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409130 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409130 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409130 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2457 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2457 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792213 # number of replacements -system.cpu.icache.tags.tagsinuse 510.662957 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243675024 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 792725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.389100 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148913080500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.662957 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 792216 # number of replacements +system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 130 system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245260488 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245260488 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243675024 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243675024 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243675024 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243675024 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243675024 # number of overall hits -system.cpu.icache.overall_hits::total 243675024 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792732 # number of overall misses -system.cpu.icache.overall_misses::total 792732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244467756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244467756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244467756 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244467756 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244467756 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244467756 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245260620 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits +system.cpu.icache.overall_hits::total 243675150 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses +system.cpu.icache.overall_misses::total 792735 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses @@ -285,7 +285,7 @@ system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102144858000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy @@ -336,16 +336,16 @@ system.cpu.itb_walker_cache.writebacks::writebacks 545 system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106219 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64823.931621 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3459892 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3459867 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170177 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.331138 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.330991 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792375 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -359,29 +359,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32213022 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32213022 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6661 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 32212786 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32212786 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6656 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2896 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779364 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2064127 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538797 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538797 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779367 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179775 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179775 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6661 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779364 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454981 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2243902 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6661 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 779367 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454970 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2243889 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779364 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454981 # number of overall hits -system.cpu.l2cache.overall_hits::total 2243902 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779367 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454970 # number of overall hits +system.cpu.l2cache.overall_hits::total 2243889 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses @@ -401,27 +401,27 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_misses::cpu.inst 13355 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 166813 # number of overall misses system.cpu.l2cache.overall_misses::total 180174 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6662 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6657 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2901 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792719 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109651 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538797 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538797 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314425 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314425 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6662 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792719 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621794 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2424076 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6662 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792719 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621794 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2424076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses @@ -429,17 +429,17 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428242 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016847 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102858 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.074327 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016847 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102858 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.074327 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -452,39 +452,39 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98110 # number of writebacks system.cpu.l2cache.writebacks::total 98110 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15971499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15971499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 15971490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1538797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1538781 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314430 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527769 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20381 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34143103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50734848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20367 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34143061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550521 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279337657 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 48002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4017293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3969670 98.81% 98.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4017293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -545,7 +545,7 @@ system.iocache.tags.tagsinuse 0.042441 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994875215009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 852b32ebc..b290fab5a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.188454 # Number of seconds simulated -sim_ticks 5188454477000 # Number of ticks simulated -final_tick 5188454477000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.188464 # Number of seconds simulated +sim_ticks 5188464227000 # Number of ticks simulated +final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1005236 # Simulator instruction rate (inst/s) -host_op_rate 1937641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40503850527 # Simulator tick rate (ticks/s) -host_mem_usage 596712 # Number of bytes of host memory used -host_seconds 128.10 # Real time elapsed on the host -sim_insts 128768549 # Number of instructions simulated -sim_ops 248207575 # Number of ops (including micro ops) simulated +host_inst_rate 671592 # Simulator instruction rate (inst/s) +host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27056983658 # Simulator tick rate (ticks/s) +host_mem_usage 641928 # Number of bytes of host memory used +host_seconds 191.76 # Real time elapsed on the host +sim_insts 128784844 # Number of instructions simulated +sim_ops 248241672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9035840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9893312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8124416 # Number of bytes written to this memory -system.physmem.bytes_written::total 8124416 # Number of bytes written to this memory +system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory +system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154583 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126944 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126944 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1741528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1906794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1741528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3472658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154583 # Number of read requests accepted -system.physmem.writeReqs 173664 # Number of write requests accepted -system.physmem.readBursts 154583 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173664 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9885440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 10960768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9893312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11114496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2370 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1582 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10392 # Per bank write bursts -system.physmem.perBankRdBursts::1 9723 # Per bank write bursts -system.physmem.perBankRdBursts::2 9455 # Per bank write bursts -system.physmem.perBankRdBursts::3 9480 # Per bank write bursts -system.physmem.perBankRdBursts::4 9901 # Per bank write bursts -system.physmem.perBankRdBursts::5 9535 # Per bank write bursts -system.physmem.perBankRdBursts::6 9436 # Per bank write bursts -system.physmem.perBankRdBursts::7 9264 # Per bank write bursts -system.physmem.perBankRdBursts::8 9069 # Per bank write bursts -system.physmem.perBankRdBursts::9 9032 # Per bank write bursts -system.physmem.perBankRdBursts::10 9333 # Per bank write bursts -system.physmem.perBankRdBursts::11 9426 # Per bank write bursts -system.physmem.perBankRdBursts::12 9943 # Per bank write bursts -system.physmem.perBankRdBursts::13 10317 # Per bank write bursts -system.physmem.perBankRdBursts::14 10185 # Per bank write bursts -system.physmem.perBankRdBursts::15 9969 # Per bank write bursts -system.physmem.perBankWrBursts::0 11290 # Per bank write bursts -system.physmem.perBankWrBursts::1 10662 # Per bank write bursts -system.physmem.perBankWrBursts::2 11268 # Per bank write bursts -system.physmem.perBankWrBursts::3 10649 # Per bank write bursts -system.physmem.perBankWrBursts::4 10537 # Per bank write bursts -system.physmem.perBankWrBursts::5 10374 # Per bank write bursts -system.physmem.perBankWrBursts::6 10316 # Per bank write bursts -system.physmem.perBankWrBursts::7 10238 # Per bank write bursts -system.physmem.perBankWrBursts::8 10391 # Per bank write bursts -system.physmem.perBankWrBursts::9 10158 # Per bank write bursts -system.physmem.perBankWrBursts::10 10967 # Per bank write bursts -system.physmem.perBankWrBursts::11 11299 # Per bank write bursts -system.physmem.perBankWrBursts::12 11272 # Per bank write bursts -system.physmem.perBankWrBursts::13 11296 # Per bank write bursts -system.physmem.perBankWrBursts::14 10371 # Per bank write bursts -system.physmem.perBankWrBursts::15 10174 # Per bank write bursts +system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154683 # Number of read requests accepted +system.physmem.writeReqs 173682 # Number of write requests accepted +system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10173 # Per bank write bursts +system.physmem.perBankRdBursts::1 9740 # Per bank write bursts +system.physmem.perBankRdBursts::2 9593 # Per bank write bursts +system.physmem.perBankRdBursts::3 9430 # Per bank write bursts +system.physmem.perBankRdBursts::4 10001 # Per bank write bursts +system.physmem.perBankRdBursts::5 9691 # Per bank write bursts +system.physmem.perBankRdBursts::6 9399 # Per bank write bursts +system.physmem.perBankRdBursts::7 9276 # Per bank write bursts +system.physmem.perBankRdBursts::8 9154 # Per bank write bursts +system.physmem.perBankRdBursts::9 9223 # Per bank write bursts +system.physmem.perBankRdBursts::10 9471 # Per bank write bursts +system.physmem.perBankRdBursts::11 9338 # Per bank write bursts +system.physmem.perBankRdBursts::12 9899 # Per bank write bursts +system.physmem.perBankRdBursts::13 10266 # Per bank write bursts +system.physmem.perBankRdBursts::14 9992 # Per bank write bursts +system.physmem.perBankRdBursts::15 9940 # Per bank write bursts +system.physmem.perBankWrBursts::0 11451 # Per bank write bursts +system.physmem.perBankWrBursts::1 10885 # Per bank write bursts +system.physmem.perBankWrBursts::2 11361 # Per bank write bursts +system.physmem.perBankWrBursts::3 10717 # Per bank write bursts +system.physmem.perBankWrBursts::4 11001 # Per bank write bursts +system.physmem.perBankWrBursts::5 10578 # Per bank write bursts +system.physmem.perBankWrBursts::6 10603 # Per bank write bursts +system.physmem.perBankWrBursts::7 9872 # Per bank write bursts +system.physmem.perBankWrBursts::8 10400 # Per bank write bursts +system.physmem.perBankWrBursts::9 10659 # Per bank write bursts +system.physmem.perBankWrBursts::10 10851 # Per bank write bursts +system.physmem.perBankWrBursts::11 10912 # Per bank write bursts +system.physmem.perBankWrBursts::12 10837 # Per bank write bursts +system.physmem.perBankWrBursts::13 10879 # Per bank write bursts +system.physmem.perBankWrBursts::14 9964 # Per bank write bursts +system.physmem.perBankWrBursts::15 10199 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5188454413500 # Total gap between requests +system.physmem.totGap 5188464163500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154583 # Read request sizes (log2) +system.physmem.readPktSize::6 154683 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173682 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see @@ -156,137 +156,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.761560 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.245927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.668619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19719 33.56% 33.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13641 23.21% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5790 9.85% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3461 5.89% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2363 4.02% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1647 2.80% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1118 1.90% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1023 1.74% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9999 17.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58761 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.321575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 600.921026 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6349 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.970394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.564885 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.510023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4926 77.57% 77.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 38 0.60% 78.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.31% 78.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 294 4.63% 83.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 158 2.49% 85.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 56 0.88% 86.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.66% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 42 0.66% 87.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 172 2.71% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.19% 90.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.28% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.20% 91.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 29 0.46% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 15 0.24% 91.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.16% 92.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.80% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 104 1.64% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.17% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 15 0.24% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 146 2.30% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 14 0.22% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 26 0.41% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.09% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.46% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.14% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 18 0.28% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.16% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.08% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 7 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6350 # Writes before turning the bus around for reads -system.physmem.totQLat 1440123750 # Total ticks spent queuing -system.physmem.totMemAccLat 4336248750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9323.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads +system.physmem.totQLat 1439298500 # Total ticks spent queuing +system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28073.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s @@ -297,240 +294,241 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 126965 # Number of row buffer hits during reads -system.physmem.writeRowHits 139995 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes -system.physmem.avgGap 15806555.47 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 220290840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 120198375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 602050800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 552964320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134005273470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2995523664000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3469908991965 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.775183 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4983224613500 # Time in different power states -system.physmem_0.memoryStateTime::REF 173253860000 # Time in different power states +system.physmem.readRowHits 127137 # Number of row buffer hits during reads +system.physmem.writeRowHits 140055 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes +system.physmem.avgGap 15800904.98 # Average gap between requests +system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773100 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states +system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31975122750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223942320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122190750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 602729400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 556813440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134550538605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995045361250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3469986125925 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.790049 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4982425910500 # Time in different power states -system.physmem_1.memoryStateTime::REF 173253860000 # Time in different power states +system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.787680 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states +system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32774591500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10376908954 # number of cpu cycles simulated +system.cpu.numCycles 10376928454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128768549 # Number of instructions committed -system.cpu.committedOps 248207575 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232776792 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2318393 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23210237 # number of instructions that are conditional controls -system.cpu.num_int_insts 232776792 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 436093789 # number of times the integer registers were read -system.cpu.num_int_register_writes 198513181 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.committedInsts 128784844 # Number of instructions committed +system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 2318021 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls +system.cpu.num_int_insts 232811079 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read +system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written +system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133234655 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95751573 # number of times the CC registers were written -system.cpu.num_mem_refs 22383387 # number of memory refs -system.cpu.num_load_insts 13964107 # Number of load instructions -system.cpu.num_store_insts 8419280 # Number of store instructions -system.cpu.num_idle_cycles 9778785583.998116 # Number of idle cycles -system.cpu.num_busy_cycles 598123370.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057640 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942360 # Percentage of idle cycles -system.cpu.Branches 26388104 # Number of branches fetched -system.cpu.op_class::No_OpClass 172612 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225394100 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140617 0.06% 90.93% # Class of executed instruction -system.cpu.op_class::IntDiv 123416 0.05% 90.98% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::MemRead 13959118 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8419280 3.39% 100.00% # Class of executed instruction +system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written +system.cpu.num_mem_refs 22376754 # number of memory refs +system.cpu.num_load_insts 13962110 # Number of load instructions +system.cpu.num_store_insts 8414644 # Number of store instructions +system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles +system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942354 # Percentage of idle cycles +system.cpu.Branches 26395735 # Number of branches fetched +system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248209143 # Class of executed instruction +system.cpu.op_class::total 248243229 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1623444 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20166944 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623956 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.418405 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1624253 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88826058 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88826058 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12020150 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12020150 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8085355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8085355 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59272 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59272 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20105505 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20105505 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20164777 # number of overall hits -system.cpu.dcache.overall_hits::total 20164777 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907010 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325954 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325954 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402776 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402776 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635740 # number of overall misses -system.cpu.dcache.overall_misses::total 1635740 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12729308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12729308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11333106054 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11333106054 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24062414554 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24062414554 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24062414554 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24062414554 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12927160 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12927160 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411309 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411309 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 462048 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 462048 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21338469 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21338469 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21800517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21800517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070163 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070163 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038752 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038752 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871719 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871719 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057781 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057781 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075032 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075032 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14034.364009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14034.364009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34769.035060 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34769.035060 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19515.910078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19515.910078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14710.415197 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14710.415197 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9503 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits +system.cpu.dcache.overall_hits::total 20157297 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses +system.cpu.dcache.overall_misses::total 1636579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.293478 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539984 # number of writebacks -system.cpu.dcache.writebacks::total 1539984 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks +system.cpu.dcache.writebacks::total 1540563 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9549 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9549 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9549 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9549 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316695 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316695 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402742 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402742 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223415 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223415 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626157 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626157 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10908565500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10908565500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10195656140 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10195656140 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5345944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5345944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21104221640 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21104221640 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26450165640 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26450165640 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568414500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568414500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815939500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815939500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070141 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070141 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037651 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037651 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871645 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871645 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057334 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.798372 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.798372 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32193.928354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32193.928354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13273.867637 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13273.867637 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17250.255751 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17250.255751 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16265.444013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16265.444013 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -538,59 +536,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8115 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.053285 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13021 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8129 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.601796 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5157393413000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053285 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315830 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315830 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 54039 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 54039 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13023 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13023 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13023 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13023 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13023 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13023 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9331 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9331 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9331 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9331 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9331 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9331 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97236000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97236000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97236000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97236000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97236000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97236000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22354 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22354 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22354 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22354 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22354 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.417420 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.417420 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.417420 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.417420 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.417420 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.417420 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10420.748044 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10420.748044 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10420.748044 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,86 +596,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9331 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9331 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9331 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9331 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9331 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9331 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78573500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78573500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78573500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.417420 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.417420 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.417420 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8420.694459 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles 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for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 793710 # number of replacements -system.cpu.icache.tags.tagsinuse 510.347195 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145088955 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794222 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.680604 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 794079 # number of replacements +system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.347195 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146677413 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146677413 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145088955 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145088955 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145088955 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145088955 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145088955 # number of overall hits -system.cpu.icache.overall_hits::total 145088955 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794229 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794229 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794229 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794229 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794229 # number of overall misses -system.cpu.icache.overall_misses::total 794229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11146745615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11146745615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11146745615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11146745615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11146745615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11146745615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145883184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145883184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145883184 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145883184 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145883184 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145883184 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.674653 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14034.674653 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14034.674653 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14034.674653 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits 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+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,88 +684,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794229 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794229 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794229 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794229 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794229 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794229 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9553400385 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9553400385 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9553400385 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9553400385 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9553400385 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9553400385 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12028.521226 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12028.521226 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 4028 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.070596 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7432 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 4039 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.840059 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161717779000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.070596 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191912 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191912 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use 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-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4897 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4897 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48969750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48969750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48969750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48969750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48969750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48969750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12332 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12332 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12334 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12334 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12334 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12334 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.397097 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.397097 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.397033 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.397033 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.397033 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.397033 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9999.948948 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9999.948948 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9999.948948 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,177 +774,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4897 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4897 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4897 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4897 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4897 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4897 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39174250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39174250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39174250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39174250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39174250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39174250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.397097 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.397097 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.397033 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.397033 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7999.642638 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks 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+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87241 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64748.665455 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3494859 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151936 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.002179 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87360 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50323.834449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006391 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.989333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11199.693995 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64695 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3016 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56538 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987167 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32251607 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32251607 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6647 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3226 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 781266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280034 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2071173 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543797 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543797 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 201020 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 201020 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6647 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3226 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 781266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481054 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2272193 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6647 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3226 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 781266 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481054 # number of overall hits -system.cpu.l2cache.overall_hits::total 2272193 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy 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+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number 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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8200092280 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8984602030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784145750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8200092280 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8984602030 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088094500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088094500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021865 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807834 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807834 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063888 # mshr miss rate for overall accesses +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.795367 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62403.854891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.631625 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.122727 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.122727 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56514.195924 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56514.195924 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1047,54 +1044,54 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2700360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2699834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314528 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1588445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5982302 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7598667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50829824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204129411 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 258112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 618176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255835523 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53618 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4025992 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011815 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108054 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53190 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3978424 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4025992 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3837723500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1193787115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3055897582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7346250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13996750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230300 # Transaction distribution -system.iobus.trans_dist::ReadResp 230300 # Transaction distribution +system.iobus.trans_dist::ReadReq 230298 # Transaction distribution +system.iobus.trans_dist::ReadResp 230298 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1119,11 +1116,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95136 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1143,11 +1140,11 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) @@ -1184,54 +1181,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448381627 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52236750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47513 # number of replacements -system.iocache.tags.tagsinuse 0.108235 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47529 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045848693000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108235 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006765 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006765 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428112 # Number of tag accesses -system.iocache.tags.data_accesses 428112 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 848 # number of ReadReq misses -system.iocache.ReadReq_misses::total 848 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 848 # number of demand (read+write) misses -system.iocache.demand_misses::total 848 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 848 # number of overall misses -system.iocache.overall_misses::total 848 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144284936 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144284936 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12370106941 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12370106941 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144284936 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144284936 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144284936 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144284936 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 848 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 848 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 848 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 848 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 848 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 848 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1240,40 +1237,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170147.330189 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264771.124593 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264771.124593 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170147.330189 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170147.330189 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70958 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9208 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.706125 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 848 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 848 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 848 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 848 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 848 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100162436 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9940666941 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9940666941 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100162436 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100162436 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1282,71 +1279,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118116.080189 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212771.124593 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212771.124593 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624010 # Transaction distribution -system.membus.trans_dist::ReadResp 624010 # Transaction distribution +system.membus.trans_dist::ReadReq 624018 # Transaction distribution +system.membus.trans_dist::ReadResp 624018 # Transaction distribution system.membus.trans_dist::WriteReq 13918 # Transaction distribution system.membus.trans_dist::WriteResp 13918 # Transaction distribution -system.membus.trans_dist::Writeback 126944 # Transaction distribution +system.membus.trans_dist::Writeback 126962 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1600 # Transaction distribution -system.membus.trans_dist::ReadExReq 113223 # Transaction distribution -system.membus.trans_dist::ReadExResp 113223 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution +system.membus.trans_dist::ReadExReq 113313 # Transaction distribution +system.membus.trans_dist::ReadExResp 113313 # Transaction distribution system.membus.trans_dist::MessageReq 1653 # Transaction distribution system.membus.trans_dist::MessageResp 1653 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15002688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16669635 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22681367 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1621 # Total snoops (count) -system.membus.snoop_fanout::samples 331450 # Request fanout histogram +system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1602 # Total snoops (count) +system.membus.snoop_fanout::samples 331576 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331450 # Request fanout histogram -system.membus.reqLayer0.occupancy 257308500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331576 # Request fanout histogram +system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358085000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1729709500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618865668 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54365250 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 960bf1b41..9ee52b54f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 8331b5d9d..9bc617783 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -144,6 +144,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -152,6 +153,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -311,7 +313,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl0.sequencer system=system transitions_per_cycle=4 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 5b07510f0..916d9b36b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 |