diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:05 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:05 -0500 |
| commit | 726f626e87dbe601b4c608d78d53907b15986681 (patch) | |
| tree | 6d990cb6d4084c98e1f4f2cf3f7f36ddef72a4e6 /tests | |
| parent | 9649395f853616b337992ca01d3474c214a7f718 (diff) | |
| download | gem5-726f626e87dbe601b4c608d78d53907b15986681.tar.xz | |
stats: Bump stats for o3 LSQ changes
Diffstat (limited to 'tests')
4 files changed, 2121 insertions, 2121 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7598617b8..4efdefebb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,20 +4,20 @@ sim_seconds 1.905068 # Nu sim_ticks 1905067807000 # Number of ticks simulated final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163944 # Simulator instruction rate (inst/s) -host_op_rate 163944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5458738398 # Simulator tick rate (ticks/s) -host_mem_usage 318552 # Number of bytes of host memory used -host_seconds 348.99 # Real time elapsed on the host +host_inst_rate 154638 # Simulator instruction rate (inst/s) +host_op_rate 154638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5148903745 # Simulator tick rate (ticks/s) +host_mem_usage 378896 # Number of bytes of host memory used +host_seconds 369.99 # Real time elapsed on the host sim_insts 57215334 # Number of instructions simulated sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory @@ -27,18 +27,18 @@ system.physmem.bytes_written::tsunami.ide 2659328 # N system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s) @@ -49,9 +49,9 @@ system.physmem.bw_write::total 4103279 # Wr system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 410001 # Number of read requests accepted system.physmem.writeReqs 122141 # Number of write requests accepted @@ -317,467 +317,6 @@ system.physmem.totalEnergy::0 1276835299230 # T system.physmem.totalEnergy::1 1276845922050 # Total energy per rank (pJ) system.physmem.averagePower::0 670.232898 # Core power per rank (mW) system.physmem.averagePower::1 670.238474 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 296853 # Transaction distribution -system.membus.trans_dist::ReadResp 296773 # Transaction distribution -system.membus.trans_dist::WriteReq 13665 # Transaction distribution -system.membus.trans_dist::WriteResp 13665 # Transaction distribution -system.membus.trans_dist::Writeback 80589 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution -system.membus.trans_dist::ReadExReq 121274 # Transaction distribution -system.membus.trans_dist::ReadExResp 120582 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 18692 # Total snoops (count) -system.membus.snoop_fanout::samples 557285 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 557285 # Request fanout histogram -system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 344236 # number of replacements -system.l2c.tags.tagsinuse 65255.823465 # Cycle average of tags in use -system.l2c.tags.total_refs 2587778 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409374 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.321305 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53392.763161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5322.213179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6227.888257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 220.740542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 92.218326 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.814709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.095030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003368 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65138 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3694 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4255 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52162 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993927 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27098951 # Number of tag accesses -system.l2c.tags.data_accesses 27098951 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 802459 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 311437 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 94339 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1904312 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 804733 # number of Writeback hits -system.l2c.Writeback_hits::total 804733 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 597 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 138280 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34809 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173089 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 802459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 834357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 311437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 129148 # number of demand (read+write) hits -system.l2c.demand_hits::total 2077401 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 802459 # number of overall hits -system.l2c.overall_hits::cpu0.data 834357 # number of overall hits -system.l2c.overall_hits::cpu1.inst 311437 # number of overall hits -system.l2c.overall_hits::cpu1.data 129148 # number of overall hits -system.l2c.overall_hits::total 2077401 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13534 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273199 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1862 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 907 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289502 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1562 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4432 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 745 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1481 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113374 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7659 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121033 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13534 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386573 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1862 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8566 # number of demand (read+write) misses -system.l2c.demand_misses::total 410535 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13534 # number of overall misses -system.l2c.overall_misses::cpu0.data 386573 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1862 # number of overall misses -system.l2c.overall_misses::cpu1.data 8566 # number of overall misses -system.l2c.overall_misses::total 410535 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1040639500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17951579250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 147621500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 80108498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19219948748 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1096455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 8459610 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9556065 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1292445 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1455438 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9386780343 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 797590458 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10184370801 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1040639500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27338359593 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 147621500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 877698956 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29404319549 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1040639500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27338359593 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 147621500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 877698956 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29404319549 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 815993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 969276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 313299 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 95246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2193814 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 804733 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 804733 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3036 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1993 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5029 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 788 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 771 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1559 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 251654 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 42468 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294122 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 815993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1220930 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 313299 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 137714 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2487936 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 815993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1220930 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 313299 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 137714 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2487936 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.281859 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.009523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.131963 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945323 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783743 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.881289 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934010 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.966278 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.949968 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.450515 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.180348 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.411506 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016586 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316622 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005943 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.062201 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165010 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016586 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316622 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005943 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.062201 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165010 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76890.756613 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65708.802924 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79281.149302 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88322.489526 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66389.692465 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.040070 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5415.883483 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2156.151850 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1756.039402 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.782550 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 982.740041 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82794.823707 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 104137.675676 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84145.404980 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71624.391462 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71624.391462 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80589 # number of writebacks -system.l2c.writebacks::total 80589 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13521 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273198 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1858 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289484 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2870 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1562 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4432 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 736 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 745 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1481 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 113374 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7659 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121033 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13521 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386572 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1858 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8566 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410517 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13521 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386572 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1858 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8566 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410517 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 869263000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14546768250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 123935250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 68927498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15608893998 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28724364 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15649033 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 44373397 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7383232 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7461237 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 14844469 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8003168657 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 703372040 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8706540697 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 869263000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22549936907 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 123935250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 772299538 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24315434695 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 869263000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22549936907 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 123935250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 772299538 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24315434695 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1361646000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27086000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1388732000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2074085500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 667819500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2741905000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3435731500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 694905500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4130637000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281858 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.009523 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.131955 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945323 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783743 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.881289 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934010 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966278 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.949968 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.450515 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.180348 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.411506 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165003 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165003 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53246.247227 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75995.036384 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53919.712309 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.489199 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.587068 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.048060 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.565217 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.083221 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10023.274139 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70590.864369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91836.015146 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71935.263085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41697 # number of replacements -system.iocache.tags.tagsinuse 0.496947 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336805000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.496947 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031059 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031059 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375577 # Number of tag accesses -system.iocache.tags.data_accesses 375577 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 2 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 2 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses -system.iocache.demand_misses::total 177 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 177 # number of overall misses -system.iocache.overall_misses::total 177 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21586383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21586383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21586383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21586383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21586383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21586383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41554 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41554 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000048 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000048 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.branchPred.lookups 14962614 # Number of BP lookups system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect @@ -787,6 +326,7 @@ system.cpu0.branchPred.BTBCorrect 0 # Nu system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -1118,243 +658,6 @@ system.cpu0.fp_regfile_reads 113752 # nu system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 92075 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 55215 # Transaction distribution -system.iobus.trans_dist::WriteResp 55217 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 815495 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits -system.cpu0.icache.overall_hits::total 6922237 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses -system.cpu0.icache.overall_misses::total 855710 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39566 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 39566 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 39566 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 39566 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 39566 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 39566 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 816144 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 816144 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 816144 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 816144 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 816144 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 816144 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10088624022 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10088624022 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10088624022 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10088624022 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10088624022 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10088624022 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104931 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.104931 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.104931 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 1223787 # number of replacements system.cpu0.dcache.tags.tagsinuse 505.953471 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 9930066 # Total number of references to valid blocks. @@ -1524,6 +827,97 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 815495 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits +system.cpu0.icache.overall_hits::total 6922237 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses +system.cpu0.icache.overall_misses::total 855710 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39566 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 39566 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 39566 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 39566 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 39566 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 816144 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 816144 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 816144 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 816144 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 816144 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10088624022 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10088624022 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10088624022 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104931 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104931 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104931 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 4639832 # Number of BP lookups system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect @@ -1860,97 +1254,8 @@ system.cpu1.int_regfile_reads 15169687 # nu system.cpu1.int_regfile_writes 8276758 # number of integer regfile writes system.cpu1.fp_regfile_reads 77475 # number of floating regfile reads system.cpu1.fp_regfile_writes 77542 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1124646 # number of misc regfile reads +system.cpu1.misc_regfile_reads 1124650 # number of misc regfile reads system.cpu1.misc_regfile_writes 280447 # number of misc regfile writes -system.cpu1.icache.tags.replacements 312757 # number of replacements -system.cpu1.icache.tags.tagsinuse 471.042243 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1644085 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 313269 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.248157 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879134143250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.042243 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920004 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.920004 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2280436 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2280436 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1644085 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1644085 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1644085 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1644085 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1644085 # number of overall hits -system.cpu1.icache.overall_hits::total 1644085 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 323026 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 323026 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 323026 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 323026 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 323026 # number of overall misses -system.cpu1.icache.overall_misses::total 323026 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4370273976 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4370273976 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4370273976 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4370273976 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4370273976 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4370273976 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1967111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1967111 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1967111 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1967111 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1967111 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1967111 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164213 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.164213 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164213 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.164213 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164213 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.164213 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.170952 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.170952 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13529.170952 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13529.170952 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9701 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9701 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9701 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9701 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9701 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9701 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 313325 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 313325 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 313325 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 313325 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 313325 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 313325 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3639863451 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3639863451 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3639863451 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3639863451 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3639863451 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3639863451 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.159282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 140166 # number of replacements system.cpu1.dcache.tags.tagsinuse 492.227589 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks. @@ -2118,6 +1423,701 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 312757 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.042243 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1644085 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 313269 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.248157 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879134143250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.042243 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920004 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920004 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 2280436 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2280436 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1644085 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1644085 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1644085 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1644085 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1644085 # number of overall hits +system.cpu1.icache.overall_hits::total 1644085 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 323026 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 323026 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 323026 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 323026 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 323026 # number of overall misses +system.cpu1.icache.overall_misses::total 323026 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4370273976 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4370273976 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4370273976 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4370273976 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4370273976 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4370273976 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1967111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1967111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1967111 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1967111 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1967111 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1967111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.164213 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164213 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.164213 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164213 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.164213 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.170952 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.170952 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.170952 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9701 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9701 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9701 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9701 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9701 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 313325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 313325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 313325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 313325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 313325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3639863451 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3639863451 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3639863451 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.159282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 55215 # Transaction distribution +system.iobus.trans_dist::WriteResp 55217 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41697 # number of replacements +system.iocache.tags.tagsinuse 0.496947 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1710336805000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.496947 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031059 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031059 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375577 # Number of tag accesses +system.iocache.tags.data_accesses 375577 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 2 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 2 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21586383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21586383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21586383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21586383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21586383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21586383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000048 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000048 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 41552 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 344236 # number of replacements +system.l2c.tags.tagsinuse 65255.823465 # Cycle average of tags in use +system.l2c.tags.total_refs 2587778 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409374 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.321305 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53392.763161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5322.213179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6227.888257 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 220.740542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 92.218326 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.814709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.095030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003368 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65138 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3694 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4797 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4255 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52162 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993927 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27098951 # Number of tag accesses +system.l2c.tags.data_accesses 27098951 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 802459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696077 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 311437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 94339 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1904312 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 804733 # number of Writeback hits +system.l2c.Writeback_hits::total 804733 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 597 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 138280 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 34809 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173089 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 802459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 834357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 311437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 129148 # number of demand (read+write) hits +system.l2c.demand_hits::total 2077401 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 802459 # number of overall hits +system.l2c.overall_hits::cpu0.data 834357 # number of overall hits +system.l2c.overall_hits::cpu1.inst 311437 # number of overall hits +system.l2c.overall_hits::cpu1.data 129148 # number of overall hits +system.l2c.overall_hits::total 2077401 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13534 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273199 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1862 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 907 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289502 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4432 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 745 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1481 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113374 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7659 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121033 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13534 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 386573 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8566 # number of demand (read+write) misses +system.l2c.demand_misses::total 410535 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13534 # number of overall misses +system.l2c.overall_misses::cpu0.data 386573 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1862 # number of overall misses +system.l2c.overall_misses::cpu1.data 8566 # number of overall misses +system.l2c.overall_misses::total 410535 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1040639500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17951579250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 147621500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 80108498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19219948748 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1096455 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 8459610 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9556065 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1292445 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1455438 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9386780343 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 797590458 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10184370801 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1040639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 27338359593 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 147621500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 877698956 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29404319549 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1040639500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 27338359593 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 147621500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 877698956 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29404319549 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 815993 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 969276 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 313299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 95246 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2193814 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 804733 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 804733 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3036 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1993 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5029 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 788 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 771 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1559 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 251654 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 42468 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 294122 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 815993 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1220930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 313299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 137714 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2487936 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 815993 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1220930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 313299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 137714 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2487936 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016586 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.281859 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.009523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.131963 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945323 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783743 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881289 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934010 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.966278 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.949968 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450515 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.180348 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.411506 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016586 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316622 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005943 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.062201 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165010 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016586 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316622 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005943 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.062201 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165010 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76890.756613 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65708.802924 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79281.149302 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88322.489526 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 66389.692465 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.040070 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5415.883483 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2156.151850 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1756.039402 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.782550 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 982.740041 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82794.823707 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 104137.675676 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84145.404980 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71624.391462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76890.756613 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70719.785378 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 79281.149302 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 102463.104833 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71624.391462 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 80589 # number of writebacks +system.l2c.writebacks::total 80589 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 13521 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1858 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 907 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289484 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2870 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1562 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4432 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 736 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 745 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1481 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113374 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7659 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121033 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13521 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 386572 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8566 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410517 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13521 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 386572 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8566 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410517 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 869263000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14546768250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 123935250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 68927498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15608893998 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28724364 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15649033 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 44373397 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7383232 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7461237 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 14844469 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8003168657 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 703372040 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8706540697 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 869263000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22549936907 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 123935250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 772299538 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24315434695 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 869263000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22549936907 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 123935250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 772299538 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24315434695 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1361646000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27086000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388732000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2074085500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 667819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2741905000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3435731500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 694905500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4130637000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.009523 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131955 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945323 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783743 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881289 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934010 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966278 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.949968 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.450515 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.180348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.411506 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.062201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165003 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53246.247227 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75995.036384 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53919.712309 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.489199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.587068 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.048060 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.565217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.083221 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10023.274139 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70590.864369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91836.015146 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71935.263085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64289.845426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58333.083894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66703.579117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 90158.713285 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59231.249120 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 296853 # Transaction distribution +system.membus.trans_dist::ReadResp 296773 # Transaction distribution +system.membus.trans_dist::WriteReq 13665 # Transaction distribution +system.membus.trans_dist::WriteResp 13665 # Transaction distribution +system.membus.trans_dist::Writeback 80589 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution +system.membus.trans_dist::ReadExReq 121274 # Transaction distribution +system.membus.trans_dist::ReadExResp 120582 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 18692 # Total snoops (count) +system.membus.snoop_fanout::samples 557285 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557285 # Request fanout histogram +system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 92075 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3b1cffd2f..b13980f34 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.824366 # Nu sim_ticks 2824365837500 # Number of ticks simulated final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90810 # Simulator instruction rate (inst/s) -host_op_rate 110172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2134851185 # Simulator tick rate (ticks/s) -host_mem_usage 669748 # Number of bytes of host memory used -host_seconds 1322.98 # Real time elapsed on the host +host_inst_rate 93434 # Simulator instruction rate (inst/s) +host_op_rate 113356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2196532158 # Simulator tick rate (ticks/s) +host_mem_usage 669668 # Number of bytes of host memory used +host_seconds 1285.83 # Real time elapsed on the host sim_insts 120140086 # Number of instructions simulated sim_ops 145755972 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -750,7 +750,7 @@ system.cpu0.fp_regfile_reads 8164 # nu system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes -system.cpu0.misc_regfile_reads 245816593 # number of misc regfile reads +system.cpu0.misc_regfile_reads 245816614 # number of misc regfile reads system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes system.cpu0.dcache.tags.replacements 712837 # number of replacements system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use @@ -1815,7 +1815,7 @@ system.cpu1.fp_regfile_reads 1413 # nu system.cpu1.fp_regfile_writes 520 # number of floating regfile writes system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes -system.cpu1.misc_regfile_reads 205875636 # number of misc regfile reads +system.cpu1.misc_regfile_reads 205875708 # number of misc regfile reads system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes system.cpu1.dcache.tags.replacements 191071 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index caba31176..b052ee538 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.804324 # Nu sim_ticks 2804324203000 # Number of ticks simulated final_tick 2804324203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115850 # Simulator instruction rate (inst/s) -host_op_rate 140611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2777671240 # Simulator tick rate (ticks/s) -host_mem_usage 569464 # Number of bytes of host memory used -host_seconds 1009.60 # Real time elapsed on the host +host_inst_rate 110825 # Simulator instruction rate (inst/s) +host_op_rate 134512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2657187313 # Simulator tick rate (ticks/s) +host_mem_usage 623780 # Number of bytes of host memory used +host_seconds 1055.37 # Real time elapsed on the host sim_insts 116961789 # Number of instructions simulated sim_ops 141959973 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -635,9 +635,9 @@ system.cpu0.iew.iewDispNonSpecInsts 550941 # Nu system.cpu0.iew.iewIQFullEvents 44144 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 2103435 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 52158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 253800 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 253796 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 219690 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 473490 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 473486 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 76500063 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 14443562 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 547275 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index a72ace5ed..6eaff03eb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -4,42 +4,15 @@ sim_seconds 47.379675 # Nu sim_ticks 47379674621500 # Number of ticks simulated final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109387 # Simulator instruction rate (inst/s) -host_op_rate 128661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5550125892 # Simulator tick rate (ticks/s) -host_mem_usage 850512 # Number of bytes of host memory used -host_seconds 8536.68 # Real time elapsed on the host +host_inst_rate 105231 # Simulator instruction rate (inst/s) +host_op_rate 123773 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5339286706 # Simulator tick rate (ticks/s) +host_mem_usage 910192 # Number of bytes of host memory used +host_seconds 8873.78 # Real time elapsed on the host sim_insts 933798389 # Number of instructions simulated sim_ops 1098335322 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory @@ -50,16 +23,16 @@ system.physmem.bytes_read::cpu1.itb.walker 462784 # system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory @@ -70,13 +43,13 @@ system.physmem.num_reads::cpu1.itb.walker 7231 # N system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s) @@ -87,17 +60,17 @@ system.physmem.bw_read::cpu1.itb.walker 9768 # To system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s) @@ -108,6 +81,7 @@ system.physmem.bw_total::cpu1.itb.walker 9768 # To system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1619423 # Number of read requests accepted system.physmem.writeReqs 2568188 # Number of write requests accepted @@ -370,772 +344,38 @@ system.physmem.totalEnergy::0 31692457458225 # system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ) system.physmem.averagePower::0 668.904083 # Core power per rank (mW) system.physmem.averagePower::1 668.836485 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1503713 # Transaction distribution -system.membus.trans_dist::ReadResp 1503713 # Transaction distribution -system.membus.trans_dist::WriteReq 38586 # Transaction distribution -system.membus.trans_dist::WriteResp 38586 # Transaction distribution -system.membus.trans_dist::Writeback 882638 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution -system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution -system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution -system.membus.trans_dist::ReadExReq 170539 # Transaction distribution -system.membus.trans_dist::ReadExResp 155861 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 618323 # Total snoops (count) -system.membus.snoop_fanout::samples 4885385 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4885385 # Request fanout histogram -system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1387044 # number of replacements -system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use -system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 91165244 # Number of tag accesses -system.l2c.tags.data_accesses 91165244 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits -system.l2c.Writeback_hits::total 2284318 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits -system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits -system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits -system.l2c.overall_hits::cpu0.data 749454 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits -system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits -system.l2c.overall_hits::cpu1.data 744950 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits -system.l2c.overall_hits::total 5495748 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77928 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 11922 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9604 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21526 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 91592 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67962 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 159554 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5517 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8182 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 12718 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 288655 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 598730 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 7231 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8328 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 204511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 456002 # number of demand (read+write) misses -system.l2c.demand_misses::total 1595159 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5517 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8182 # number of overall misses -system.l2c.overall_misses::cpu0.inst 12718 # number of overall misses -system.l2c.overall_misses::cpu0.data 288655 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 598730 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5285 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 7231 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8328 # number of overall misses -system.l2c.overall_misses::cpu1.data 204511 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 456002 # number of overall misses -system.l2c.overall_misses::total 1595159 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 458859494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 660185236 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1228334988 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 18297393453 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 440607992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 598540979 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 788794491 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12800911061 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 163963230205 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 163981726 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 172729371 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 336711097 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59985022 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 52908784 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 112893806 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7434747873 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5448950117 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12883697990 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 458859494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 660185236 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1228334988 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25732141326 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 440607992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 598540979 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 788794491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 18249861178 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 176846928195 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 458859494 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 660185236 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1228334988 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 25732141326 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 440607992 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 598540979 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 788794491 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 18249861178 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of overall miss cycles -system.l2c.overall_miss_latency::total 176846928195 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 13070 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 12483 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 183412 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 893155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2424665 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 13508 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 12388 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 171273 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 827749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2272538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 6824241 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2284318 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2284318 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 67318 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 70602 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 137920 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 20866 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 17044 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 37910 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 144954 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 121712 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 266666 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 13070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 12483 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 183412 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1038109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2424665 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 13508 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 12388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 171273 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 949461 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2272538 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 7090907 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 13070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 12483 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 183412 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1038109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2424665 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 13508 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 12388 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 171273 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 949461 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2272538 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 7090907 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.655451 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.069341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.220637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.583710 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.048624 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.164964 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.210368 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.575641 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.554899 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.565023 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571360 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563483 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.567819 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.631869 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.558384 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.598329 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.655451 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.069341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.278058 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.583710 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.048624 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.215397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.224958 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.655451 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.069341 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.278058 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.583710 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.048624 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.215397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.224958 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80687.513566 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 96582.401950 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 92850.476513 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82774.302171 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 94715.957133 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 93745.915832 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 114211.938663 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4231.677273 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4408.948388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4320.797364 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5031.456299 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5509.036235 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5244.532472 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81172.459090 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80176.423840 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 80748.198040 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 110864.765327 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 110864.765327 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 23951 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 978 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 24.489775 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 882638 # number of writebacks -system.l2c.writebacks::total 882638 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 314 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 29 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 342 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 787 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 314 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 342 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 787 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 314 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 29 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 342 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 787 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5517 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 8182 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 12695 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 197019 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5285 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 7231 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 8299 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 136514 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 1434818 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 38751 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 39177 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 77928 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11922 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9604 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 21526 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 91592 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 67962 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 159554 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 5517 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 8182 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12695 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 288611 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 5285 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 7231 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8299 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 204476 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1594372 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 5517 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 8182 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12695 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 288611 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 5285 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 7231 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8299 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 204476 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1594372 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 558414736 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1068365744 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 15850467855 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 508508979 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 683514241 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11106706811 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 146316086137 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 30535463126 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15845549899 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 46381013025 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 399321668 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 406522254 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 805843922 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 123605642 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 99686358 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 223292000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6293776443 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4602629757 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10896406200 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 558414736 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1068365744 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22144244298 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 508508979 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 683514241 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 15709336568 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 157212492337 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 558414736 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1068365744 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22144244298 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 508508979 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 683514241 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 15709336568 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 157212492337 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4952355997 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4307750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 415818753 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6475689500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4782466503 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 497465997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5279932500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9734822500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4307750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 913284750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11755622000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.220588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.164922 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.210253 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575641 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.554899 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.565023 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571360 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563483 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.567819 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631869 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558384 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.598329 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.224847 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.224847 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1633796 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40417 # Transaction distribution -system.iobus.trans_dist::ReadResp 40417 # Transaction distribution -system.iobus.trans_dist::WriteReq 136643 # Transaction distribution -system.iobus.trans_dist::WriteResp 136782 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu0.branchPred.lookups 146587108 # Number of BP lookups system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect @@ -1145,6 +385,7 @@ system.cpu0.branchPred.BTBCorrect 0 # Nu system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1525,62 +766,209 @@ system.cpu0.fp_regfile_reads 697220 # nu system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes -system.cpu0.misc_regfile_reads 3071585466 # number of misc regfile reads +system.cpu0.misc_regfile_reads 3071586051 # number of misc regfile reads system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.dcache.tags.replacements 6421778 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits +system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses +system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks +system.cpu0.dcache.writebacks::total 3548346 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 6503720 # number of replacements system.cpu0.icache.tags.tagsinuse 511.971418 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 223511778 # Total number of references to valid blocks. @@ -2031,207 +1419,60 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 6421778 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits -system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses -system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks -system.cpu0.dcache.writebacks::total 3548346 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 126883394 # Number of BP lookups system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect @@ -2621,62 +1862,209 @@ system.cpu1.fp_regfile_reads 775313 # nu system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2680324006 # number of misc regfile reads +system.cpu1.misc_regfile_reads 2680324661 # number of misc regfile reads system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dcache.tags.replacements 5270583 # number of replacements +system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits +system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses +system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 535551 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks +system.cpu1.dcache.writebacks::total 3043634 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2993097 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1369794 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1369794 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 690691 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 690691 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116127 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116127 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 206288 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4362891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4362891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 5515063 # number of replacements system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks. @@ -3126,207 +2514,145 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 5270583 # number of replacements -system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits -system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses -system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 535551 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks -system.cpu1.dcache.writebacks::total 3043634 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2993097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1369794 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1369794 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 690691 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 690691 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116127 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116127 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 206288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4362891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4362891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40417 # Transaction distribution +system.iobus.trans_dist::ReadResp 40417 # Transaction distribution +system.iobus.trans_dist::WriteReq 136643 # Transaction distribution +system.iobus.trans_dist::WriteResp 136782 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115615 # number of replacements system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -3463,6 +2789,680 @@ system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1387044 # number of replacements +system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use +system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 91165244 # Number of tag accesses +system.l2c.tags.data_accesses 91165244 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits +system.l2c.Writeback_hits::total 2284318 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits +system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits +system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits +system.l2c.overall_hits::cpu0.data 749454 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits +system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits +system.l2c.overall_hits::cpu1.data 744950 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits +system.l2c.overall_hits::total 5495748 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses +system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77928 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 11922 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9604 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 21526 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 91592 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 67962 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 159554 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 5517 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 8182 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 12718 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 288655 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 598730 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 5285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 7231 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8328 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 204511 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 456002 # number of demand (read+write) misses +system.l2c.demand_misses::total 1595159 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 5517 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 8182 # number of overall misses +system.l2c.overall_misses::cpu0.inst 12718 # number of overall misses +system.l2c.overall_misses::cpu0.data 288655 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 598730 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 5285 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 7231 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8328 # number of overall misses +system.l2c.overall_misses::cpu1.data 204511 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 456002 # number of overall misses +system.l2c.overall_misses::total 1595159 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 458859494 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 660185236 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1228334988 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 18297393453 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 440607992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 598540979 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 788794491 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 12800911061 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 163963230205 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 163981726 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 172729371 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 336711097 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59985022 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 52908784 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 112893806 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7434747873 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5448950117 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12883697990 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 458859494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 660185236 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1228334988 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25732141326 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 440607992 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 598540979 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 788794491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 18249861178 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 176846928195 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 458859494 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 660185236 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1228334988 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 25732141326 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 440607992 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 598540979 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 788794491 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 18249861178 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of overall miss cycles +system.l2c.overall_miss_latency::total 176846928195 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 13070 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 12483 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 183412 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 893155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2424665 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 13508 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 12388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 171273 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 827749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2272538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 6824241 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2284318 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2284318 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 67318 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 70602 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 137920 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 20866 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 17044 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 37910 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 144954 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 121712 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 266666 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 13070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 12483 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 183412 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1038109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2424665 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 13508 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 12388 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 171273 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 949461 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2272538 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 7090907 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 13070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 12483 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 183412 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1038109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2424665 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 13508 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 12388 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 171273 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 949461 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2272538 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 7090907 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.655451 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.069341 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.220637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.583710 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.048624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.164964 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.210368 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.575641 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.554899 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.565023 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571360 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563483 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.567819 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.631869 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.558384 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.598329 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.655451 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.069341 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.278058 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.583710 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.048624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.215397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.224958 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.655451 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.069341 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.278058 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.583710 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.048624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.215397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.224958 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80687.513566 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 96582.401950 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 92850.476513 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82774.302171 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 94715.957133 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 93745.915832 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 114211.938663 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4231.677273 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4408.948388 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4320.797364 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5031.456299 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5509.036235 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5244.532472 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81172.459090 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80176.423840 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 80748.198040 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 110864.765327 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 110864.765327 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 23951 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 978 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 24.489775 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 882638 # number of writebacks +system.l2c.writebacks::total 882638 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 314 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 29 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 342 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 787 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 314 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 342 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 787 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 314 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 342 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 787 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5517 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 8182 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 12695 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 197019 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5285 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 7231 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 8299 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 136514 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 1434818 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 38751 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 39177 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 77928 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11922 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9604 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 21526 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 91592 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 67962 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 159554 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 5517 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 8182 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12695 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 288611 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 5285 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 7231 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8299 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 204476 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1594372 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 5517 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 8182 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12695 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 288611 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 598416 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 5285 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 7231 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 8299 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 204476 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 455660 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1594372 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 558414736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1068365744 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 15850467855 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 508508979 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 683514241 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11106706811 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 146316086137 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 30535463126 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15845549899 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 46381013025 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 399321668 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 406522254 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 805843922 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 123605642 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 99686358 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 223292000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6293776443 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4602629757 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10896406200 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 558414736 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1068365744 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22144244298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 508508979 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 683514241 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 15709336568 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 157212492337 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 558414736 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1068365744 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22144244298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 508508979 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 683514241 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 15709336568 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 157212492337 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4952355997 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4307750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 415818753 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6475689500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4782466503 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 497465997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5279932500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9734822500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4307750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 913284750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11755622000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.220588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.164922 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.210253 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575641 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.554899 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.565023 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571360 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563483 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.567819 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631869 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558384 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.598329 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.224847 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.224847 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1503713 # Transaction distribution +system.membus.trans_dist::ReadResp 1503713 # Transaction distribution +system.membus.trans_dist::WriteReq 38586 # Transaction distribution +system.membus.trans_dist::WriteResp 38586 # Transaction distribution +system.membus.trans_dist::Writeback 882638 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution +system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution +system.membus.trans_dist::ReadExReq 170539 # Transaction distribution +system.membus.trans_dist::ReadExResp 155861 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 618323 # Total snoops (count) +system.membus.snoop_fanout::samples 4885385 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4885385 # Request fanout histogram +system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1633796 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed |