diff options
| author | Steve Reinhardt <stever@gmail.com> | 2013-06-08 10:28:33 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2013-06-08 10:28:33 -0400 |
| commit | bd39adfa98a3032410008a8921346bc9c83b8d82 (patch) | |
| tree | 665db7241f57edd3b4a4e7cad03e45527791f669 /tests | |
| parent | 2b582ad9bbe262729b5eb48881b56614f084d707 (diff) | |
| download | gem5-bd39adfa98a3032410008a8921346bc9c83b8d82.tar.xz | |
Updating EIO regression reference outputs for new stats.
Diffstat (limited to 'tests')
14 files changed, 773 insertions, 660 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 3fc579691..1686f16ad 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer workload +children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,17 +44,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -67,6 +74,9 @@ size=64 [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -89,6 +99,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -96,13 +107,13 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout index 3fdf9580f..e5b133727 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 20:21:46 -gem5 started Jul 23 2012 00:28:55 +gem5 compiled Jun 8 2013 10:00:13 +gem5 started Jun 8 2013 10:00:28 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 32e1aa3e7..6b92e1420 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1870393 # Simulator instruction rate (inst/s) -host_op_rate 1870272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 935134836 # Simulator tick rate (ticks/s) -host_mem_usage 212756 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 2804892 # Simulator instruction rate (inst/s) +host_op_rate 2804630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1402273759 # Simulator tick rate (ticks/s) +host_mem_usage 217844 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1670144451 # Wr system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13160136072 # Throughput (bytes/s) +system.membus.data_through_bus 3290238 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini index b45e06437..dc819fce5 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -41,15 +43,17 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_start_insts= +switched_out=false system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -61,21 +65,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=262144 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -90,21 +91,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=131072 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -113,6 +111,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -120,23 +121,20 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=20 size=2097152 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -145,10 +143,11 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 +system=system use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -170,6 +169,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -177,13 +177,13 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout index a532af78a..a4d5a6332 100755 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 20:21:46 -gem5 started Jul 23 2012 00:28:55 +gem5 compiled Jun 8 2013 10:00:13 +gem5 started Jun 8 2013 10:00:28 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries 49508 bytes wasted ->Exiting @ tick 729729000 because a thread reached the max instruction count +>Exiting @ tick 727072000 because a thread reached the max instruction count diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 9caac7258..21486e70f 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu sim_ticks 727072000 # Number of ticks simulated final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1240024 # Simulator instruction rate (inst/s) -host_op_rate 1239964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1802997891 # Simulator tick rate (ticks/s) -host_mem_usage 256648 # Number of bytes of host memory used -host_seconds 0.40 # Real time elapsed on the host +host_inst_rate 1476552 # Simulator instruction rate (inst/s) +host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2146892777 # Simulator tick rate (ticks/s) +host_mem_usage 226332 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 35473791 # In system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 75436821 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 718 # Transaction distribution +system.membus.trans_dist::ReadResp 718 # Transaction distribution +system.membus.trans_dist::ReadExReq 139 # Transaction distribution +system.membus.trans_dist::ReadExResp 139 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 54848 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -160,104 +175,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use -system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits -system.cpu.dcache.overall_hits::total 180321 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses -system.cpu.dcache.overall_misses::total 454 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. @@ -377,5 +294,122 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use +system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits +system.cpu.dcache.overall_hits::total 180321 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses +system.cpu.dcache.overall_misses::total 454 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 75436821 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 0853f81cf..85ac3f7de 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[1] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,17 +44,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu0.tracer width=1 @@ -65,21 +72,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -94,21 +98,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -117,6 +118,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -136,11 +140,11 @@ system=system [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -149,17 +153,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu1.tracer width=1 @@ -172,21 +181,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -201,21 +207,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -224,6 +227,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -243,11 +249,11 @@ system=system [system.cpu2] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=2 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -256,17 +262,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu2.tracer width=1 @@ -279,21 +290,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -308,21 +316,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -331,6 +336,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=AlphaInterrupts +[system.cpu2.isa] +type=AlphaISA + [system.cpu2.itb] type=AlphaTLB size=48 @@ -350,11 +358,11 @@ system=system [system.cpu3] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer workload +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=3 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -363,17 +371,22 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu3.tracer width=1 @@ -386,21 +399,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -415,21 +425,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -438,6 +445,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=AlphaInterrupts +[system.cpu3.isa] +type=AlphaISA + [system.cpu3.itb] type=AlphaTLB size=48 @@ -460,21 +470,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] @@ -485,6 +492,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -492,21 +500,22 @@ slave=system.l2c.mem_side system.system_port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 null=false range=0:1073741823 -zero=false port=system.membus.master[0] [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 8b296506e..b26c03cc4 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -6,5 +6,3 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 93473d0a5..6f7f12863 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 20:21:46 -gem5 started Jul 23 2012 00:28:55 +gem5 compiled Jun 8 2013 10:00:13 +gem5 started Jun 8 2013 10:00:28 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 84894234a..8803a901a 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2922206 # Simulator instruction rate (inst/s) -host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 365280152 # Simulator tick rate (ticks/s) -host_mem_usage 1149344 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host +host_inst_rate 3032804 # Simulator instruction rate (inst/s) +host_op_rate 3032728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379104441 # Simulator tick rate (ticks/s) +host_mem_usage 1154504 # Number of bytes of host memory used +host_seconds 0.66 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory @@ -57,6 +57,12 @@ system.physmem.bw_total::cpu2.data 116216795 # To system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 877513594 # Throughput (bytes/s) +system.membus.data_through_bus 219392 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.throughput 977859373 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 244480 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 6a2952c7b..e7ce04e2d 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -52,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -124,7 +125,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -153,6 +154,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu1.tracer @@ -225,7 +227,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -254,6 +256,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu2.tracer @@ -326,7 +329,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -355,6 +358,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu3.tracer @@ -427,7 +431,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -476,7 +480,6 @@ latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 4399b76d5..8b296506e 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -8,5 +8,3 @@ gzip: stdout: Broken pipe gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 2900cfcc7..de7797416 100755 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout -Redirecting stderr to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:19:43 -gem5 started Mar 28 2013 09:22:33 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp +gem5 compiled Jun 8 2013 10:00:13 +gem5 started Jun 8 2013 10:00:28 +gem5 executing on zizzer +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries @@ -17,4 +15,4 @@ main dictionary has 1245 entries 49508 bytes wasted 49508 bytes wasted 49508 bytes wasted ->>>>Exiting @ tick 729071000 because a thread reached the max instruction count +>>>>Exiting @ tick 729024000 because a thread reached the max instruction count diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 0ede4e331..e6052b6f1 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000729 # Number of seconds simulated -sim_ticks 729071000 # Number of ticks simulated -final_tick 729071000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 729024000 # Number of ticks simulated +final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1157540 # Simulator instruction rate (inst/s) -host_op_rate 1157526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 421963637 # Simulator tick rate (ticks/s) -host_mem_usage 274580 # Number of bytes of host memory used -host_seconds 1.73 # Real time elapsed on the host +host_inst_rate 1420709 # Simulator instruction rate (inst/s) +host_op_rate 1420692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 517863701 # Simulator tick rate (ticks/s) +host_mem_usage 236964 # Number of bytes of host memory used +host_seconds 1.41 # Real time elapsed on the host sim_insts 1999959 # Number of instructions simulated sim_ops 1999959 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory @@ -34,29 +34,88 @@ system.physmem.num_reads::cpu2.data 454 # Nu system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35376527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39853457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35376527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39853457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35376527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39853457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35376527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39853457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 300919938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35376527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141506108 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35376527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39853457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35376527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39853457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35376527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39853457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35376527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39853457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 300919938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 35378808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39856027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35378808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 39856027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 35378808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 39856027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 35378808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 39856027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 300939338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 35378808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35378808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 35378808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 35378808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141515231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 35378808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39856027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35378808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 39856027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 35378808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 39856027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 35378808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 39856027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300939338 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 300939338 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2872 # Transaction distribution +system.membus.trans_dist::ReadResp 2872 # Transaction distribution +system.membus.trans_dist::ReadExReq 556 # Transaction distribution +system.membus.trans_dist::ReadExResp 556 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 6856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 6856 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 219392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 219392 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 219392 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 31051500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 4.3 # Layer utilization (%) +system.toL2Bus.throughput 335352471 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 29632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 244480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 244480 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 2083500 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -90,7 +149,7 @@ system.cpu0.itb.data_misses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1458142 # number of cpu cycles simulated +system.cpu0.numCycles 1458048 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 500001 # Number of instructions committed @@ -109,18 +168,18 @@ system.cpu0.num_mem_refs 180793 # nu system.cpu0.num_load_insts 124443 # Number of load instructions system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1458142 # Number of busy cycles +system.cpu0.num_busy_cycles 1458048 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 216.378486 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 216.376897 # Cycle average of tags in use system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 216.378486 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.422614 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.422614 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.422611 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -133,12 +192,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 463 # system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23142000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23142000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 23142000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23142000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 23142000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23142000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23096000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23096000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 23096000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23096000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 23096000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23096000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses @@ -151,12 +210,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49982.721382 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 49982.721382 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 49982.721382 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 49982.721382 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49883.369330 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 49883.369330 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 49883.369330 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 49883.369330 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,34 +230,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22216000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22216000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22216000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22216000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22216000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22216000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22170000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22170000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22170000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22170000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22170000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22170000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47982.721382 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47883.369330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 273.500836 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 273.500146 # Cycle average of tags in use system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 273.500836 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.534181 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.534181 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.534180 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -215,14 +274,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 # system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17475500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17475500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17474500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 25145000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25145000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 25145000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25145000 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 25144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 25144000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) @@ -239,14 +298,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53936.728395 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 53936.728395 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53933.641975 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 54308.855292 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 54308.855292 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -265,14 +324,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16827500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16827500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16826500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24219000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24219000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24219000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24219000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses @@ -281,14 +340,14 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51936.728395 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51936.728395 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51933.641975 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -323,7 +382,7 @@ system.cpu1.itb.data_misses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1458142 # number of cpu cycles simulated +system.cpu1.numCycles 1458048 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 499993 # Number of instructions committed @@ -342,18 +401,18 @@ system.cpu1.num_mem_refs 180792 # nu system.cpu1.num_load_insts 124443 # Number of load instructions system.cpu1.num_store_insts 56349 # Number of store instructions system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1458142 # Number of busy cycles +system.cpu1.num_busy_cycles 1458048 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 216.374608 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 216.373058 # Cycle average of tags in use system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 216.374608 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.422607 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.422607 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.422604 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits @@ -366,12 +425,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 463 # system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23145500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 23145500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 23145500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 23145500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 23145500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 23145500 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23105000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 23105000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 23105000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 23105000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 23105000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 23105000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses @@ -384,12 +443,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49990.280778 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 49990.280778 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 49990.280778 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 49990.280778 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49902.807775 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 49902.807775 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 49902.807775 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 49902.807775 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,34 +463,34 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22219500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 22219500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22219500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 22219500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22219500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 22219500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22179000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22179000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47990.280778 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47902.807775 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 273.495853 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 273.495183 # Cycle average of tags in use system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 273.495853 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.534172 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.534172 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.534170 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits @@ -448,14 +507,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 # system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17480000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7670500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7670500 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 25150500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 25150500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 25150500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 25150500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17474500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7669500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 25144000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 25144000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) @@ -472,14 +531,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53950.617284 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55183.453237 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 55183.453237 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 54320.734341 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 54320.734341 # average overall miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53933.641975 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55176.258993 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,14 +557,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16832000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7392500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7392500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24224500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 24224500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24224500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 24224500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16826500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7391500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24218000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses @@ -514,14 +573,14 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51950.617284 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51950.617284 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53183.453237 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53183.453237 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51933.641975 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53176.258993 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses @@ -556,7 +615,7 @@ system.cpu2.itb.data_misses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1458142 # number of cpu cycles simulated +system.cpu2.numCycles 1458048 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 499986 # Number of instructions committed @@ -575,18 +634,18 @@ system.cpu2.num_mem_refs 180790 # nu system.cpu2.num_load_insts 124441 # Number of load instructions system.cpu2.num_store_insts 56349 # Number of store instructions system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1458142 # Number of busy cycles +system.cpu2.num_busy_cycles 1458048 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 216.370489 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 216.369218 # Cycle average of tags in use system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 216.370489 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.422599 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.422599 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.422596 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits @@ -599,12 +658,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 463 # system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23141000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 23141000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 23141000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 23141000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 23141000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 23141000 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23114000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 23114000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 23114000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 23114000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 23114000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 23114000 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses @@ -617,12 +676,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49980.561555 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 49980.561555 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 49980.561555 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 49980.561555 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49922.246220 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 49922.246220 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 49922.246220 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 49922.246220 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,34 +696,34 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22215000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 22215000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22215000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 22215000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22215000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 22215000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22188000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 22188000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22188000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 22188000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22188000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 22188000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47980.561555 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47922.246220 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 273.490811 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 273.490220 # Cycle average of tags in use system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 273.490811 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.534162 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.534162 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.534161 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits @@ -681,14 +740,14 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 # system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17485000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 17485000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7679000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 7679000 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 25164000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 25164000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 25164000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 25164000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17474500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7669500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 25144000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 25144000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) @@ -705,14 +764,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53966.049383 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 53966.049383 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55244.604317 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 55244.604317 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 54349.892009 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 54349.892009 # average overall miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53933.641975 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55176.258993 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -731,14 +790,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16837000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16837000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7401000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7401000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24238000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 24238000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24238000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 24238000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16826500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7391500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24218000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses @@ -747,14 +806,14 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51966.049383 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51966.049383 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53244.604317 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53244.604317 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51933.641975 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53176.258993 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses @@ -789,7 +848,7 @@ system.cpu3.itb.data_misses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1458142 # number of cpu cycles simulated +system.cpu3.numCycles 1458048 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.committedInsts 499979 # Number of instructions committed @@ -808,18 +867,18 @@ system.cpu3.num_mem_refs 180788 # nu system.cpu3.num_load_insts 124439 # Number of load instructions system.cpu3.num_store_insts 56349 # Number of store instructions system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1458142 # Number of busy cycles +system.cpu3.num_busy_cycles 1458048 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 216.366465 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 216.365379 # Cycle average of tags in use system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 216.366465 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.422591 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.422591 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.422589 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits @@ -832,12 +891,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 463 # system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23153500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 23153500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 23153500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 23153500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 23153500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 23153500 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23123000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 23123000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 23123000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 23123000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 23123000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 23123000 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses @@ -850,12 +909,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50007.559395 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 50007.559395 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 50007.559395 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 50007.559395 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 49941.684665 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 49941.684665 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,34 +929,34 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22227500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 22227500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22227500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 22227500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22227500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 22227500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22197000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 22197000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22197000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 22197000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22197000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 22197000 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48007.559395 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 273.485807 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 273.485257 # Cycle average of tags in use system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 273.485807 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.534152 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.534152 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.534151 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits @@ -914,14 +973,14 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 # system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17480000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7680500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 7680500 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 25160500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 25160500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 25160500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 25160500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17474500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7669500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 25144000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 25144000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) @@ -938,14 +997,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53950.617284 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55255.395683 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 55255.395683 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 54342.332613 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 54342.332613 # average overall miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53933.641975 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55176.258993 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -964,14 +1023,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16832000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7402500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7402500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24234500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 24234500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24234500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 24234500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16826500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7391500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24218000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses @@ -980,30 +1039,30 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 264.998020 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 216.478029 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy @@ -1013,7 +1072,7 @@ system.l2c.occ_percent::cpu2.inst 0.004044 # Av system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029651 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.029650 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits @@ -1075,38 +1134,38 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # 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mshr miss rate for ReadReq accesses @@ -1311,36 +1370,36 @@ system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40344.913151 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40321.339950 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40401.985112 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |