diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests')
88 files changed, 22752 insertions, 22162 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 70213a160..da3261384 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:49 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:11:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897464893500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107002000 +Exiting @ tick 1899401490000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 89ae1dc03..af2074343 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,179 +1,179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897464893500 # Number of ticks simulated -final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899401 # Number of seconds simulated +sim_ticks 1899401490000 # Number of ticks simulated +final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189830 # Simulator instruction rate (inst/s) -host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6418636186 # Simulator tick rate (ticks/s) -host_mem_usage 296280 # Number of bytes of host memory used -host_seconds 295.62 # Real time elapsed on the host -sim_insts 56117221 # Number of instructions simulated -sim_ops 56117221 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30408512 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10470144 # Number of bytes written to this memory -system.physmem.num_reads 475133 # Number of read requests responded to by this memory -system.physmem.num_writes 163596 # Number of write requests responded to by this memory +host_inst_rate 189434 # Simulator instruction rate (inst/s) +host_op_rate 189434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6363739723 # Simulator tick rate (ticks/s) +host_mem_usage 296196 # Number of bytes of host memory used +host_seconds 298.47 # Real time elapsed on the host +sim_insts 56540749 # Number of instructions simulated +sim_ops 56540749 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10508736 # Number of bytes written to this memory +system.physmem.num_reads 475339 # Number of read requests responded to by this memory +system.physmem.num_writes 164199 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397850 # number of replacements -system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use -system.l2c.total_refs 2482376 # Total number of references to valid blocks. -system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.062074 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 109195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 38109 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits -system.l2c.Writeback_hits::total 827202 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits -system.l2c.overall_hits::cpu0.data 932654 # number of overall hits -system.l2c.overall_hits::cpu1.inst 109195 # number of overall hits -system.l2c.overall_hits::cpu1.data 49204 # number of overall hits -system.l2c.overall_hits::total 2046785 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 15234 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 290346 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1960 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2086 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 562 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 45 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 84 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113888 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 10746 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 15234 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 404234 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1960 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12832 # number of demand (read+write) misses -system.l2c.demand_misses::total 434260 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 15234 # number of overall misses -system.l2c.overall_misses::cpu0.data 404234 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1960 # number of overall misses -system.l2c.overall_misses::cpu1.data 12832 # number of overall misses -system.l2c.overall_misses::total 434260 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 796850500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15107982000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 102548000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 110604500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16117985000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2465000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1619000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4084000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 420000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 629500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5974507500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 563694000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6538201500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 796850500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 21082489500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 102548000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 674298500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22656186500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 796850500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 21082489500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 102548000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 674298500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22656186500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 970966 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1054820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 111155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 40195 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 827202 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2622 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 111 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 282068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21841 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 970966 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1336888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 111155 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 62036 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 970966 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1336888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 111155 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 62036 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015690 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.275256 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.017633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.051897 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.925865 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.608108 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756757 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.403761 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.492010 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015690 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.302369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206848 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.302369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206848 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52034.407224 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52320.408163 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53022.291467 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1007.355946 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2880.782918 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9333.333333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2494.047619 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52459.499684 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52456.169738 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency +system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 397771 # number of replacements +system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use +system.l2c.total_refs 2469954 # Total number of references to valid blocks. +system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits +system.l2c.Writeback_hits::total 806294 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits +system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits +system.l2c.overall_hits::cpu0.data 822730 # number of overall hits +system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits +system.l2c.overall_hits::cpu1.data 135531 # number of overall hits +system.l2c.overall_hits::total 2042553 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses +system.l2c.demand_misses::total 434620 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses +system.l2c.overall_misses::cpu0.data 397745 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses +system.l2c.overall_misses::cpu1.data 19147 # number of overall misses +system.l2c.overall_misses::total 434620 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 707237500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20745010000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 220139500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 998215500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22670602500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 707237500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20745010000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 220139500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 998215500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22670602500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 924232 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 957077 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 177788 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 121001 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2180098 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 806294 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 806294 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 824 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3932 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 286 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 324 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 610 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 263398 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 33677 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 297075 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 924232 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1220475 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 177788 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 154678 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2477173 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 924232 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1220475 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 177788 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 154678 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2477173 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,110 +182,110 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 122076 # number of writebacks -system.l2c.writebacks::total 122076 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 2 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 122679 # number of writebacks +system.l2c.writebacks::total 122679 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 15234 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 290346 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1944 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2084 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 309608 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2447 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 562 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 45 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 84 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 129 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 113888 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 10746 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 124634 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 15234 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 404234 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1944 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 12830 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 434242 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 15234 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 404234 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1944 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 12830 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 434242 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 610356500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11621105000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 77934000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 85027000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12394422500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97946500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22482000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 120428500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1801500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3360000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 5161500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4590092500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 432485500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5022578000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 610356500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 16211197500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 77934000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 517512500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17417000500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 610356500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 16211197500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 77934000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 517512500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17417000500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 821008500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17113500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 838122000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1130592498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 289769000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1420361498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1951600998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 306882500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2258483498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275256 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051847 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933257 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.925865 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.608108 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756757 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.403761 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.492010 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40025.021870 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40799.904031 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40027.176134 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.558719 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40033.333333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40303.565784 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40246.184627 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13520 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 288493 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4190 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3184 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 309387 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2939 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 698 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3637 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 248 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 292 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 540 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 109252 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 15963 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 125215 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13520 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 397745 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4190 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 19147 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 434602 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13520 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 397745 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4190 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 19147 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 434602 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 541689500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11548328000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 167980000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 125604000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12383601500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117566000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27923000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 145489000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9921000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11680500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21601500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4402693000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 641940500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5044633500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 541689500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15951021000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 167980000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 767544500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17428235000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 541689500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15951021000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 167980000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 767544500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17428235000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 568678500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269407000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 838085500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 961824498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 507055500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1468879998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1530502998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 776462500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2306965498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -293,81 +293,81 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.463236 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.205020 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.463236 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.028952 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.028952 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.warmup_cycle 1708344834000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.205020 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.012814 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012814 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20391998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20391998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5720293806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5720293806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5740685804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5740685804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5740685804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5740685804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20513998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20513998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5720296806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5720296806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5740810804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5740810804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5740810804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5740810804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115209.028249 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.907923 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11187998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11187998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559436992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559436992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570624990 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570624990 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570624990 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570624990 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11257998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11257998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559437998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559437998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570695996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570695996 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -385,22 +385,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9525013 # DTB read hits -system.cpu0.dtb.read_misses 35809 # DTB read misses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_accesses 640960 # DTB read accesses -system.cpu0.dtb.write_hits 6193277 # DTB write hits -system.cpu0.dtb.write_misses 8191 # DTB write misses -system.cpu0.dtb.write_acv 352 # DTB write access violations -system.cpu0.dtb.write_accesses 218947 # DTB write accesses -system.cpu0.dtb.data_hits 15718290 # DTB hits -system.cpu0.dtb.data_misses 44000 # DTB misses -system.cpu0.dtb.data_acv 948 # DTB access violations -system.cpu0.dtb.data_accesses 859907 # DTB accesses -system.cpu0.itb.fetch_hits 1059968 # ITB hits -system.cpu0.itb.fetch_misses 28334 # ITB misses -system.cpu0.itb.fetch_acv 968 # ITB acv -system.cpu0.itb.fetch_accesses 1088302 # ITB accesses +system.cpu0.dtb.read_hits 8814586 # DTB read hits +system.cpu0.dtb.read_misses 32972 # DTB read misses +system.cpu0.dtb.read_acv 518 # DTB read access violations +system.cpu0.dtb.read_accesses 619797 # DTB read accesses +system.cpu0.dtb.write_hits 5858085 # DTB write hits +system.cpu0.dtb.write_misses 6892 # DTB write misses +system.cpu0.dtb.write_acv 315 # DTB write access violations +system.cpu0.dtb.write_accesses 207416 # DTB write accesses +system.cpu0.dtb.data_hits 14672671 # DTB hits +system.cpu0.dtb.data_misses 39864 # DTB misses +system.cpu0.dtb.data_acv 833 # DTB access violations +system.cpu0.dtb.data_accesses 827213 # DTB accesses +system.cpu0.itb.fetch_hits 1034325 # ITB hits +system.cpu0.itb.fetch_misses 27665 # ITB misses +system.cpu0.itb.fetch_acv 1025 # ITB acv +system.cpu0.itb.fetch_accesses 1061990 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -413,279 +413,279 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112143855 # number of cpu cycles simulated +system.cpu0.numCycles 105407779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued -system.cpu0.iq.rate 0.489688 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued +system.cpu0.iq.rate 0.482387 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3514446 # number of nop insts executed -system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8658040 # Number of branches executed -system.cpu0.iew.exec_stores 6215854 # Number of stores executed -system.cpu0.iew.exec_rate 0.483991 # Inst execution rate -system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26555285 # num instructions producing a value -system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value +system.cpu0.iew.exec_nop 3218084 # number of nop insts executed +system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7980527 # Number of branches executed +system.cpu0.iew.exec_stores 5879131 # Number of stores executed +system.cpu0.iew.exec_rate 0.477396 # Inst execution rate +system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24623982 # num instructions producing a value +system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 53643051 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53643051 # Number of instructions committed -system.cpu0.commit.committedOps 53643051 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50284711 # Number of instructions committed +system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14593748 # Number of memory references committed -system.cpu0.commit.loads 8594447 # Number of loads committed -system.cpu0.commit.membars 217509 # Number of memory barriers committed -system.cpu0.commit.branches 8090596 # Number of branches committed -system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. -system.cpu0.commit.function_calls 704226 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13762834 # Number of memory references committed +system.cpu0.commit.loads 8083571 # Number of loads committed +system.cpu0.commit.membars 205088 # Number of memory barriers committed +system.cpu0.commit.branches 7564309 # Number of branches committed +system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. +system.cpu0.commit.function_calls 644133 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 136894487 # The number of ROB reads -system.cpu0.rob.rob_writes 125011331 # The number of ROB writes -system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50529139 # Number of Instructions Simulated -system.cpu0.committedOps 50529139 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated -system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads -system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes -system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads -system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes +system.cpu0.rob.rob_reads 126892294 # The number of ROB reads +system.cpu0.rob.rob_writes 115369853 # The number of ROB writes +system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47376653 # Number of Instructions Simulated +system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated +system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads +system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes +system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads +system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -717,211 +717,211 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 970410 # number of replacements -system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use -system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.008513 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 7511566 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7511566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7511566 # number of overall hits -system.cpu0.icache.overall_hits::total 7511566 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1025306 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1025306 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1025306 # number of overall misses -system.cpu0.icache.overall_misses::total 1025306 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15323045497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15323045497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8536872 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8536872 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120103 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120103 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120103 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked +system.cpu0.icache.replacements 923652 # number of replacements +system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use +system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits +system.cpu0.icache.overall_hits::total 6902434 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses +system.cpu0.icache.overall_misses::total 973969 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 220 # number of writebacks -system.cpu0.icache.writebacks::total 220 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54249 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54249 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 971057 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 971057 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 971057 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 971057 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 196 # number of writebacks +system.cpu0.icache.writebacks::total 196 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1340651 # number of replacements -system.cpu0.dcache.tagsinuse 504.872538 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 19222000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.872538 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6993872 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3966970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 182544 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208490 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10960842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10960842 # number of overall hits -system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1697480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1808304 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21693 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 688 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3505784 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3505784 # number of overall misses -system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92214768853 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92214768853 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195307 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.313111 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106215 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003289 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.242336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.242336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9218.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked +system.cpu0.dcache.replacements 1225027 # number of replacements +system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits +system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses +system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 791009 # number of writebacks -system.cpu0.dcache.writebacks::total 791009 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2175152 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2175152 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330632 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1330632 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049268 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.082399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003289 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6205.668605 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks +system.cpu0.dcache.writebacks::total 689568 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency @@ -930,22 +930,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1327892 # DTB read hits -system.cpu1.dtb.read_misses 10318 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 331425 # DTB read accesses -system.cpu1.dtb.write_hits 775217 # DTB write hits -system.cpu1.dtb.write_misses 3380 # DTB write misses -system.cpu1.dtb.write_acv 51 # DTB write access violations -system.cpu1.dtb.write_accesses 128049 # DTB write accesses -system.cpu1.dtb.data_hits 2103109 # DTB hits -system.cpu1.dtb.data_misses 13698 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 459474 # DTB accesses -system.cpu1.itb.fetch_hits 367800 # ITB hits -system.cpu1.itb.fetch_misses 7781 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 375581 # ITB accesses +system.cpu1.dtb.read_hits 1967803 # DTB read hits +system.cpu1.dtb.read_misses 13979 # DTB read misses +system.cpu1.dtb.read_acv 50 # DTB read access violations +system.cpu1.dtb.read_accesses 344857 # DTB read accesses +system.cpu1.dtb.write_hits 1156959 # DTB write hits +system.cpu1.dtb.write_misses 3426 # DTB write misses +system.cpu1.dtb.write_acv 86 # DTB write access violations +system.cpu1.dtb.write_accesses 133134 # DTB write accesses +system.cpu1.dtb.data_hits 3124762 # DTB hits +system.cpu1.dtb.data_misses 17405 # DTB misses +system.cpu1.dtb.data_acv 136 # DTB access violations +system.cpu1.dtb.data_accesses 477991 # DTB accesses +system.cpu1.itb.fetch_hits 421916 # ITB hits +system.cpu1.itb.fetch_misses 9109 # ITB misses +system.cpu1.itb.fetch_acv 356 # ITB acv +system.cpu1.itb.fetch_accesses 431025 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -958,643 +958,647 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9964881 # number of cpu cycles simulated +system.cpu1.numCycles 16642884 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits +system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued -system.cpu1.iq.rate 0.630911 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued +system.cpu1.iq.rate 0.613946 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 264808 # number of nop insts executed -system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed -system.cpu1.iew.exec_branches 906293 # Number of branches executed -system.cpu1.iew.exec_stores 781951 # Number of stores executed -system.cpu1.iew.exec_rate 0.623044 # Inst execution rate -system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2959215 # num instructions producing a value -system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value +system.cpu1.iew.exec_nop 532071 # number of nop insts executed +system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1559516 # Number of branches executed +system.cpu1.iew.exec_stores 1165063 # Number of stores executed +system.cpu1.iew.exec_rate 0.606457 # Inst execution rate +system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4916782 # num instructions producing a value +system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 5811574 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 5811574 # Number of instructions committed -system.cpu1.commit.committedOps 5811574 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9615778 # Number of instructions committed +system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1881487 # Number of memory references committed -system.cpu1.commit.loads 1153406 # Number of loads committed -system.cpu1.commit.membars 20496 # Number of memory barriers committed -system.cpu1.commit.branches 821024 # Number of branches committed -system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. -system.cpu1.commit.function_calls 89377 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2823987 # Number of memory references committed +system.cpu1.commit.loads 1739300 # Number of loads committed +system.cpu1.commit.membars 35653 # Number of memory barriers committed +system.cpu1.commit.branches 1422938 # Number of branches committed +system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. +system.cpu1.commit.function_calls 153476 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15919643 # The number of ROB reads -system.cpu1.rob.rob_writes 14461697 # The number of ROB writes -system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5588082 # Number of Instructions Simulated -system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated -system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads -system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes -system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads -system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes -system.cpu1.icache.replacements 110606 # number of replacements -system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use -system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 453.435417 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 936898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 936898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 936898 # number of overall hits -system.cpu1.icache.overall_hits::total 936898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 116421 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 116421 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 116421 # number of overall misses -system.cpu1.icache.overall_misses::total 116421 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1750783999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1750783999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1053319 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1053319 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110528 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 25542136 # The number of ROB reads +system.cpu1.rob.rob_writes 23473924 # The number of ROB writes +system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9164096 # Number of Instructions Simulated +system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated +system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads +system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes +system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads +system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes +system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads +system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes +system.cpu1.icache.replacements 177236 # number of replacements +system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use +system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits +system.cpu1.icache.overall_hits::total 1491482 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses +system.cpu1.icache.overall_misses::total 188398 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 37 # number of writebacks -system.cpu1.icache.writebacks::total 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5236 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 5236 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 5236 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 5236 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 111185 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 111185 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 111185 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 111185 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 52 # number of writebacks +system.cpu1.icache.writebacks::total 52 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62388 # number of replacements -system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 392.324021 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1127254 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 549515 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16791 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14923 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1676769 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1676769 # number of overall hits -system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 106582 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 157839 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1481 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 695 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 264421 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 264421 # number of overall misses -system.cpu1.dcache.overall_misses::total 264421 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6969056280 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6969056280 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked +system.cpu1.dcache.replacements 156190 # number of replacements +system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 22430 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2413851 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2413851 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2413851 # number of overall hits +system.cpu1.dcache.overall_hits::total 2413851 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 229184 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 229184 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 231703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 231703 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 3831 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 3831 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 1979 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 1979 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses +system.cpu1.dcache.overall_misses::total 460887 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks -system.cpu1.dcache.writebacks::total 35937 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks +system.cpu1.dcache.writebacks::total 116478 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.88% 28.37% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 28.84% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.72% 32.56% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.65% 37.21% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.79% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 40.47% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.40% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.79% 44.65% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 45.58% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.35% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.40% 62.33% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.65% 66.98% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.65% 71.63% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 72.09% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.79% 74.88% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.70% 85.58% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 86.98% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.79% 89.77% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 90.23% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.40% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.19% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.14% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed +system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed +system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed +system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184665 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches +system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed +system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 175342 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1248 -system.cpu0.kern.mode_good::user 1249 +system.cpu0.kern.mode_good::kernel 1161 +system.cpu0.kern.mode_good::user 1162 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3841 # number of times the context was actually changed +system.cpu0.kern.swap_context 3714 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.90% 21.62% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.31% 27.93% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.70% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.70% 33.33% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.50% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::45 21 18.92% 56.76% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.70% 59.46% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.90% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::71 31 27.93% 88.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.01% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed +system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed +system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed -system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed +system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed +system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed +system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed +system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31730 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches -system.cpu1.kern.mode_switch::user 491 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 491 -system.cpu1.kern.mode_good::idle 30 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 42196 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 747 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 169 +system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 394 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 735 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index c3587ff5d..52235dbd6 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:47 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:10:30 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1859850554500 because m5_exit instruction encountered +Exiting @ tick 1858684403000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3b4a45a9b..da1fed07c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,115 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859851 # Number of seconds simulated -sim_ticks 1859850554500 # Number of ticks simulated -final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.858684 # Number of seconds simulated +sim_ticks 1858684403000 # Number of ticks simulated +final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188989 # Simulator instruction rate (inst/s) -host_op_rate 188989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6621174751 # Simulator tick rate (ticks/s) -host_mem_usage 292896 # Number of bytes of host memory used -host_seconds 280.89 # Real time elapsed on the host -sim_insts 53085804 # Number of instructions simulated -sim_ops 53085804 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29820864 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10193536 # Number of bytes written to this memory -system.physmem.num_reads 465951 # Number of read requests responded to by this memory -system.physmem.num_writes 159274 # Number of write requests responded to by this memory +host_inst_rate 192280 # Simulator instruction rate (inst/s) +host_op_rate 192280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6731751609 # Simulator tick rate (ticks/s) +host_mem_usage 292636 # Number of bytes of host memory used +host_seconds 276.11 # Real time elapsed on the host +sim_insts 53089851 # Number of instructions simulated +sim_ops 53089851 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 29847552 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10195968 # Number of bytes written to this memory +system.physmem.num_reads 466368 # Number of read requests responded to by this memory +system.physmem.num_writes 159312 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 391353 # number of replacements -system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use -system.l2c.total_refs 2406767 # Total number of references to valid blocks. -system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits -system.l2c.Writeback_hits::total 835189 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 391653 # number of replacements +system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use +system.l2c.total_refs 2427420 # Total number of references to valid blocks. +system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits +system.l2c.Writeback_hits::total 834721 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 988583 # number of overall hits -system.l2c.overall_hits::cpu.data 995422 # number of overall hits -system.l2c.overall_hits::total 1984005 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses -system.l2c.demand_misses::total 425026 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 16626 # number of overall misses -system.l2c.overall_misses::cpu.data 408400 # number of overall misses -system.l2c.overall_misses::total 425026 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits +system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits +system.l2c.overall_hits::cpu.data 994510 # number of overall hits +system.l2c.overall_hits::total 2003843 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses +system.l2c.demand_misses::total 425412 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 16915 # number of overall misses +system.l2c.overall_misses::cpu.data 408497 # number of overall misses +system.l2c.overall_misses::total 425412 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 884741000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 15168191000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16052932000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 425500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 425500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6138440500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6138440500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 884741000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21306631500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22191372500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,69 +121,81 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117762 # number of writebacks -system.l2c.writebacks::total 117762 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.writebacks::writebacks 117800 # number of writebacks +system.l2c.writebacks::total 117800 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1343000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1343000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4714582500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4714582500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 677644000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 16382770000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17060414000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 677644000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.276011 # Cycle average of tags in use +system.iocache.tagsinuse 1.266745 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -191,12 +206,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -210,14 +225,14 @@ system.iocache.WriteReq_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -233,20 +248,20 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -264,22 +279,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10136178 # DTB read hits -system.cpu.dtb.read_misses 46729 # DTB read misses -system.cpu.dtb.read_acv 584 # DTB read access violations -system.cpu.dtb.read_accesses 970980 # DTB read accesses -system.cpu.dtb.write_hits 6626287 # DTB write hits -system.cpu.dtb.write_misses 12218 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 347267 # DTB write accesses -system.cpu.dtb.data_hits 16762465 # DTB hits -system.cpu.dtb.data_misses 58947 # DTB misses -system.cpu.dtb.data_acv 1003 # DTB access violations -system.cpu.dtb.data_accesses 1318247 # DTB accesses -system.cpu.itb.fetch_hits 1326719 # ITB hits -system.cpu.itb.fetch_misses 39613 # ITB misses -system.cpu.itb.fetch_acv 1063 # ITB acv -system.cpu.itb.fetch_accesses 1366332 # ITB accesses +system.cpu.dtb.read_hits 10017178 # DTB read hits +system.cpu.dtb.read_misses 45828 # DTB read misses +system.cpu.dtb.read_acv 561 # DTB read access violations +system.cpu.dtb.read_accesses 954843 # DTB read accesses +system.cpu.dtb.write_hits 6639084 # DTB write hits +system.cpu.dtb.write_misses 10800 # DTB write misses +system.cpu.dtb.write_acv 415 # DTB write access violations +system.cpu.dtb.write_accesses 340295 # DTB write accesses +system.cpu.dtb.data_hits 16656262 # DTB hits +system.cpu.dtb.data_misses 56628 # DTB misses +system.cpu.dtb.data_acv 976 # DTB access violations +system.cpu.dtb.data_accesses 1295138 # DTB accesses +system.cpu.itb.fetch_hits 1345400 # ITB hits +system.cpu.itb.fetch_misses 36691 # ITB misses +system.cpu.itb.fetch_acv 1385 # ITB acv +system.cpu.itb.fetch_accesses 1382091 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,279 +307,279 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116271514 # number of cpu cycles simulated +system.cpu.numCycles 115937106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits +system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued -system.cpu.iq.rate 0.498544 # Inst issue rate -system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued +system.cpu.iq.rate 0.495930 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3625473 # number of nop insts executed -system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed -system.cpu.iew.exec_branches 9097936 # Number of branches executed -system.cpu.iew.exec_stores 6653902 # Number of stores executed -system.cpu.iew.exec_rate 0.492563 # Inst execution rate -system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28030988 # num instructions producing a value -system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value +system.cpu.iew.exec_nop 3587167 # number of nop insts executed +system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed +system.cpu.iew.exec_branches 9006504 # Number of branches executed +system.cpu.iew.exec_stores 6665235 # Number of stores executed +system.cpu.iew.exec_rate 0.490534 # Inst execution rate +system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27888094 # num instructions producing a value +system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back +system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56280196 # Number of instructions committed -system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56284358 # Number of instructions committed +system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15504446 # Number of memory references committed -system.cpu.commit.loads 9112319 # Number of loads committed -system.cpu.commit.membars 227818 # Number of memory barriers committed -system.cpu.commit.branches 8461284 # Number of branches committed +system.cpu.commit.refs 15505080 # Number of memory references committed +system.cpu.commit.loads 9112848 # Number of loads committed +system.cpu.commit.membars 227858 # Number of memory barriers committed +system.cpu.commit.branches 8462387 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52119152 # Number of committed integer instructions. -system.cpu.commit.function_calls 744404 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. +system.cpu.commit.function_calls 744427 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 143937484 # The number of ROB reads -system.cpu.rob.rob_writes 132136289 # The number of ROB writes -system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53085804 # Number of Instructions Simulated -system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated -system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75080091 # number of integer regfile reads -system.cpu.int_regfile_writes 40965330 # number of integer regfile writes -system.cpu.fp_regfile_reads 166532 # number of floating regfile reads -system.cpu.fp_regfile_writes 167403 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads -system.cpu.misc_regfile_writes 949674 # number of misc regfile writes +system.cpu.rob.rob_reads 142888950 # The number of ROB reads +system.cpu.rob.rob_writes 130907900 # The number of ROB writes +system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53089851 # Number of Instructions Simulated +system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated +system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads +system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74514493 # number of integer regfile reads +system.cpu.int_regfile_writes 40703979 # number of integer regfile writes +system.cpu.fp_regfile_reads 166152 # number of floating regfile reads +system.cpu.fp_regfile_writes 167434 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads +system.cpu.misc_regfile_writes 949957 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -596,237 +611,237 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004588 # number of replacements -system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use -system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits -system.cpu.icache.overall_hits::total 7985770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses -system.cpu.icache.overall_misses::total 1065446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked +system.cpu.icache.replacements 1025621 # number of replacements +system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use +system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits +system.cpu.icache.overall_hits::total 7915590 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1086093 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1086093 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1086093 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1086093 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1086093 # number of overall misses +system.cpu.icache.overall_misses::total 1086093 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16268467995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16268467995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16268467995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16268467995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16268467995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16268467995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 234 # number of writebacks -system.cpu.icache.writebacks::total 234 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 238 # number of writebacks +system.cpu.icache.writebacks::total 238 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403406 # number of replacements -system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use -system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1402627 # number of replacements +system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use +system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits -system.cpu.dcache.overall_hits::total 11674234 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses -system.cpu.dcache.overall_misses::total 3745657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits +system.cpu.dcache.overall_hits::total 11537532 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses +system.cpu.dcache.overall_misses::total 3747076 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 83500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97015665026 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97015665026 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97015665026 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97015665026 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9127640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9127640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156968 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156968 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 216878 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 216878 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220105 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220105 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15284608 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15284608 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks -system.cpu.dcache.writebacks::total 834955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834483 # number of writebacks +system.cpu.dcache.writebacks::total 834483 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718769 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718769 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643008 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643008 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5385 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5385 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299852 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299852 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17992 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17992 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1385299 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1385299 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1385299 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1385299 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24777383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24777383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8529644820 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8529644820 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212567500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212567500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 74000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 74000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307028320 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33307028320 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33307028320 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33307028320 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904080500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904080500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1233731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -865,29 +880,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192344 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 192407 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 6921c92e4..aac888352 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:40:16 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 21:03:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582494330500 because m5_exit instruction encountered +Exiting @ tick 2572328372500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6605c6d1b..68d9a148e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582494 # Number of seconds simulated -sim_ticks 2582494330500 # Number of ticks simulated -final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.572328 # Number of seconds simulated +sim_ticks 2572328372500 # Number of ticks simulated +final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80373 # Simulator instruction rate (inst/s) -host_op_rate 103823 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3357432165 # Simulator tick rate (ticks/s) -host_mem_usage 383300 # Number of bytes of host memory used -host_seconds 769.19 # Real time elapsed on the host -sim_insts 61822124 # Number of instructions simulated -sim_ops 79859495 # Number of ops (including micro ops) simulated +host_inst_rate 81734 # Simulator instruction rate (inst/s) +host_op_rate 105574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3400147622 # Simulator tick rate (ticks/s) +host_mem_usage 384052 # Number of bytes of host memory used +host_seconds 756.53 # Real time elapsed on the host +sim_insts 61834256 # Number of instructions simulated +sim_ops 79870174 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,249 +20,249 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131499364 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10236688 # Number of bytes written to this memory -system.physmem.num_reads 15129208 # Number of read requests responded to by this memory -system.physmem.num_writes 869902 # Number of write requests responded to by this memory +system.physmem.bytes_read 131402148 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10205776 # Number of bytes written to this memory +system.physmem.num_reads 15127689 # Number of read requests responded to by this memory +system.physmem.num_writes 869419 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 132156 # number of replacements -system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use -system.l2c.total_refs 1820044 # Total number of references to valid blocks. -system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. +system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 130931 # number of replacements +system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use +system.l2c.total_refs 1850900 # Total number of references to valid blocks. +system.l2c.sampled_refs 160584 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.526055 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15356.692298 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 22.670587 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.636552 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3410.170856 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1587.790766 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 18.616033 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 3.576285 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2636.430831 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4539.259596 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.234325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000346 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.052035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.024228 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000284 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000055 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.040229 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.069264 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420789 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 89183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 17213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 526448 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 212618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 73946 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 477126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 150598 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 599046 # number of Writeback hits -system.l2c.Writeback_hits::total 599046 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 443 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 38925 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 89183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 17213 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 526448 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 73946 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 477126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 189523 # number of demand (read+write) hits -system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 89183 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 17213 # number of overall hits -system.l2c.overall_hits::cpu0.inst 526448 # number of overall hits -system.l2c.overall_hits::cpu0.data 271221 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 73946 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3915 # number of overall hits -system.l2c.overall_hits::cpu1.inst 477126 # number of overall hits -system.l2c.overall_hits::cpu1.data 189523 # number of overall hits -system.l2c.overall_hits::total 1648575 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10849 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 78 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7504 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 13059 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3816 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 849 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 97885 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 106823 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 78 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7504 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 63453 # number of demand (read+write) misses -system.l2c.demand_misses::total 188799 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 70 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses -system.l2c.overall_misses::cpu0.data 106823 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 78 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7504 # number of overall misses -system.l2c.overall_misses::cpu1.data 63453 # number of overall misses -system.l2c.overall_misses::total 188799 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3650500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 521000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 567333500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 466408000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 4067500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 625000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 392575500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 681928000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2117109000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 27539500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 32790500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 60330000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1772000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5901500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7673500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5139681999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2639420000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7779101999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 3650500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 521000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 567333500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5606089999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 4067500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 625000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 392575500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3321348000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9896210999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 3650500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 567333500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5606089999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 4067500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 625000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 392575500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3321348000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9896210999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 89253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 17223 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 537297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 221556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 74024 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3927 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 484630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 163657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 599046 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 8343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4816 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1024 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 891 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 156488 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 89319 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 89253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 17223 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 537297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 378044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 74024 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3927 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 484630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 252976 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 89253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 17223 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 537297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 378044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 74024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3927 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 484630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 252976 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000581 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.020192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.040342 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.003056 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015484 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.079795 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.881098 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792359 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.829102 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.502806 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.625511 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564202 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000581 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.020192 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282568 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.003056 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015484 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.250826 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000581 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.020192 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282568 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.003056 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015484 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.250826 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52100 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.048154 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2916.118065 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1448.517664 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 24.954124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.021877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3298.971983 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4641.797632 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.231473 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.044496 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.022103 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000381 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.050338 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.070828 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.419921 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 55824 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 353946 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 138985 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 116300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6415 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 686444 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 224154 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1587428 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 602817 # number of Writeback hits +system.l2c.Writeback_hits::total 602817 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 916 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 896 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1812 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 349 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 559 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 36704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 64640 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 101344 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 55824 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5360 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 353946 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 175689 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 116300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 686444 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 288794 # number of demand (read+write) hits +system.l2c.demand_hits::total 1688772 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 55824 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5360 # number of overall hits +system.l2c.overall_hits::cpu0.inst 353946 # number of overall hits +system.l2c.overall_hits::cpu0.data 175689 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 116300 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6415 # number of overall hits +system.l2c.overall_hits::cpu1.inst 686444 # number of overall hits +system.l2c.overall_hits::cpu1.data 288794 # number of overall hits +system.l2c.overall_hits::total 1688772 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 9410 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9224 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 52 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 6 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 8908 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 12134 # number of ReadReq misses +system.l2c.ReadReq_misses::total 39813 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5335 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5536 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10871 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 765 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 529 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1294 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 66271 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 81270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 75 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9410 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 75495 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 52 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 93404 # number of demand (read+write) misses +system.l2c.demand_misses::total 187354 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 75 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9410 # number of overall misses +system.l2c.overall_misses::cpu0.data 75495 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 52 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 6 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8908 # number of overall misses +system.l2c.overall_misses::cpu1.data 93404 # number of overall misses +system.l2c.overall_misses::total 187354 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3910000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 210000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 492070500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 481346500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2708500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 312500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 465974500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 633905500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2080438000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 18240000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 37260500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 55500500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2038000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5120000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7158000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3474892499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4269418500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7744310999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 3910000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 210000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 492070500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3956238999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 2708500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 312500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 465974500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4903324000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9824748999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 3910000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 210000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 492070500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3956238999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 2708500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 312500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 465974500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4903324000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9824748999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 55899 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 363356 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 148209 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 116352 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 695352 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 236288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1627241 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 602817 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 602817 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6251 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 6432 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12683 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 878 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1853 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 102975 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 145910 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248885 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 55899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 363356 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 251184 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 116352 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6421 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 695352 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 382198 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1876126 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 55899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 363356 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 251184 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 116352 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6421 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 695352 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 382198 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1876126 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000746 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.025897 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.062236 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000934 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.051353 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.853463 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.860697 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.602506 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.643564 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.556987 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000746 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.025897 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.300557 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000934 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244386 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000746 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.025897 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.300557 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000934 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244386 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52292.295430 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.139202 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52315.498401 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52219.006049 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3746.361039 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8592.898323 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2087.161366 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13172.991071 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52507.350452 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52375.679644 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52309.665469 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52242.088347 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3418.931584 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6730.581647 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2664.052288 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9678.638941 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52434.586757 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52533.757844 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -271,168 +271,171 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112618 # number of writebacks -system.l2c.writebacks::total 112618 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 37 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 97 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 70 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 10841 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8896 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 78 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 7494 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 13022 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 40423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 7351 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3816 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11167 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 849 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 448 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1297 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 97885 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 50394 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 148279 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 70 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10841 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 106781 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 78 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 7494 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 63416 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 188702 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 70 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 10841 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 106781 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 78 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 7494 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 63416 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 188702 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 401000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 434490500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 356315000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 480000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300775500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 521480000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1619864500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 294259500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 152703500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 446963000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 33985000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17954000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 51939000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3922908499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2018431500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5941339999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 401000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 434490500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4279223499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 480000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 300775500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2539911500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7561204499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 401000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 434490500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4279223499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 480000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 300775500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2539911500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7561204499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4981000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 124405850500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1891000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 7552193500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131964916000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 881564880 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31653443800 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32535008680 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4981000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 125287415380 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1891000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39205637300 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164499924680 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.040152 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.079569 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.881098 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792359 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.829102 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.502806 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.625511 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564202 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40053.394784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average ReadReq mshr miss latency +system.l2c.writebacks::writebacks 112135 # number of writebacks +system.l2c.writebacks::total 112135 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 52 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 33 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 52 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 33 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 52 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 33 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 102 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 75 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 9408 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9172 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 51 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 8894 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 12101 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 39711 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5335 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5536 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10871 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 765 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 529 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1294 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 66271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 81270 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 147541 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 75 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 9408 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 75443 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 51 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8894 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 93371 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 187252 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 75 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 9408 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 75443 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 51 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 6 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 8894 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 93371 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 187252 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 162000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 377008500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 367415500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 240000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356843500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 484732500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1591450000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213651500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 221567500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 435219000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30631000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21186500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 51817500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2653011999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3258908000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5911919999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 162000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 377008500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3020427499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 240000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 356843500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3743640500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7503369999 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 162000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 377008500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3020427499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 356843500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3743640500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7503369999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468870500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -452,27 +455,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42410626 # DTB read hits -system.cpu0.dtb.read_misses 55840 # DTB read misses -system.cpu0.dtb.write_hits 6900244 # DTB write hits -system.cpu0.dtb.write_misses 11203 # DTB write misses +system.cpu0.dtb.read_hits 7800657 # DTB read hits +system.cpu0.dtb.read_misses 37871 # DTB read misses +system.cpu0.dtb.write_hits 4594363 # DTB write hits +system.cpu0.dtb.write_misses 6405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42466466 # DTB read accesses -system.cpu0.dtb.write_accesses 6911447 # DTB write accesses +system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7838528 # DTB read accesses +system.cpu0.dtb.write_accesses 4600768 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49310870 # DTB hits -system.cpu0.dtb.misses 67043 # DTB misses -system.cpu0.dtb.accesses 49377913 # DTB accesses -system.cpu0.itb.inst_hits 6428492 # ITB inst hits -system.cpu0.itb.inst_misses 17283 # ITB inst misses +system.cpu0.dtb.hits 12395020 # DTB hits +system.cpu0.dtb.misses 44276 # DTB misses +system.cpu0.dtb.accesses 12439296 # DTB accesses +system.cpu0.itb.inst_hits 4047811 # ITB inst hits +system.cpu0.itb.inst_misses 4513 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -481,534 +484,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses -system.cpu0.itb.hits 6428492 # DTB hits -system.cpu0.itb.misses 17283 # DTB misses -system.cpu0.itb.accesses 6445775 # DTB accesses -system.cpu0.numCycles 352483912 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses +system.cpu0.itb.hits 4047811 # DTB hits +system.cpu0.itb.misses 4513 # DTB misses +system.cpu0.itb.accesses 4052324 # DTB accesses +system.cpu0.numCycles 58217040 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued -system.cpu0.iq.rate 0.227743 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued +system.cpu0.iq.rate 0.564768 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 506933 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 642785 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 205792 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 324258 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 173953 # number of nop insts executed -system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6431362 # Number of branches executed -system.cpu0.iew.exec_stores 7171156 # Number of stores executed -system.cpu0.iew.exec_rate 0.225691 # Inst execution rate -system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24791862 # num instructions producing a value -system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value +system.cpu0.iew.exec_nop 54681 # number of nop insts executed +system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4282280 # Number of branches executed +system.cpu0.iew.exec_stores 4857867 # Number of stores executed +system.cpu0.iew.exec_rate 0.557341 # Inst execution rate +system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 16076835 # num instructions producing a value +system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 31935522 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 41923639 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31935522 # Number of instructions committed -system.cpu0.commit.committedOps 41923639 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 20629504 # Number of instructions committed +system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15936098 # Number of memory references committed -system.cpu0.commit.loads 9243307 # Number of loads committed -system.cpu0.commit.membars 288653 # Number of memory barriers committed -system.cpu0.commit.branches 5542289 # Number of branches committed -system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620184 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached +system.cpu0.commit.refs 10038315 # Number of memory references committed +system.cpu0.commit.loads 5430093 # Number of loads committed +system.cpu0.commit.membars 201113 # Number of memory barriers committed +system.cpu0.commit.branches 3777887 # Number of branches committed +system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions. +system.cpu0.commit.function_calls 441072 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157931724 # The number of ROB reads -system.cpu0.rob.rob_writes 106372981 # The number of ROB writes -system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31809695 # Number of Instructions Simulated -system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated -system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads -system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads -system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes -system.cpu0.icache.replacements 538787 # number of replacements -system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use -system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.612990 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5838964 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5838964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5838964 # number of overall hits -system.cpu0.icache.overall_hits::total 5838964 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 583385 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 583385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 583385 # number of overall misses -system.cpu0.icache.overall_misses::total 583385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8740145988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8740145988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6422349 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6422349 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090837 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090837 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090837 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked +system.cpu0.rob.rob_reads 68594693 # The number of ROB reads +system.cpu0.rob.rob_writes 67665332 # The number of ROB writes +system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 20604950 # Number of Instructions Simulated +system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated +system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads +system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads +system.cpu0.fp_regfile_writes 420 # number of floating regfile writes +system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes +system.cpu0.icache.replacements 364224 # number of replacements +system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use +system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits +system.cpu0.icache.overall_hits::total 3649617 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses +system.cpu0.icache.overall_misses::total 395923 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7411.116751 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 29665 # number of writebacks -system.cpu0.icache.writebacks::total 29665 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44065 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44065 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44065 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44065 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539320 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 539320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539320 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 18468 # number of writebacks +system.cpu0.icache.writebacks::total 18468 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 364861 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 364861 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 364861 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 364861 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 364861 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 364861 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4524888490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4524888490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4524888490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4524888490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4524888490 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4524888490 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 372182 # number of replacements -system.cpu0.dcache.tagsinuse 487.992960 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 487.992960 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7966835 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4346487 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 221211 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 199868 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12313322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12313322 # number of overall hits -system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 463412 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1864293 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10042 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7686 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2327705 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2327705 # number of overall misses -system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6478995500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6478995500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 70420524827 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 70420524827 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 122158000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 122158000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 76899520327 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 76899520327 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.054970 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.300171 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.043424 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 240566 # number of replacements +system.cpu0.dcache.tagsinuse 465.688994 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8072207 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 240949 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.501724 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49733000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 465.688994 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.909549 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.909549 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5008601 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5008601 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2710702 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2710702 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 158809 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158809 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 156314 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 156314 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7719303 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7719303 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7719303 # number of overall hits +system.cpu0.dcache.overall_hits::total 7719303 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 337108 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 337108 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1466456 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1466456 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8650 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8650 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1803564 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1803564 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1803564 # number of overall misses +system.cpu0.dcache.overall_misses::total 1803564 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4776619000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4776619000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60194469903 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60194469903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98955000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98955000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83321000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 83321000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64971088903 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64971088903 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64971088903 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64971088903 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5345709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5345709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4177158 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167459 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167459 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164050 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 164050 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9522867 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9522867 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9522867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9522867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063061 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351065 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051654 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189393 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 327766 # number of writebacks -system.cpu0.dcache.writebacks::total 327766 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1909869 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1909869 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 417836 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 417836 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 64109000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks +system.cpu0.dcache.writebacks::total 213312 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028413 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9047.202797 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10576968 # DTB read hits -system.cpu1.dtb.read_misses 41875 # DTB read misses -system.cpu1.dtb.write_hits 5530754 # DTB write hits -system.cpu1.dtb.write_misses 15302 # DTB write misses +system.cpu1.dtb.read_hits 44928224 # DTB read hits +system.cpu1.dtb.read_misses 73602 # DTB read misses +system.cpu1.dtb.write_hits 7780505 # DTB write hits +system.cpu1.dtb.write_misses 20150 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10618843 # DTB read accesses -system.cpu1.dtb.write_accesses 5546056 # DTB write accesses +system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45001826 # DTB read accesses +system.cpu1.dtb.write_accesses 7800655 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16107722 # DTB hits -system.cpu1.dtb.misses 57177 # DTB misses -system.cpu1.dtb.accesses 16164899 # DTB accesses -system.cpu1.itb.inst_hits 8214514 # ITB inst hits -system.cpu1.itb.inst_misses 3039 # ITB inst misses +system.cpu1.dtb.hits 52708729 # DTB hits +system.cpu1.dtb.misses 93752 # DTB misses +system.cpu1.dtb.accesses 52802481 # DTB accesses +system.cpu1.itb.inst_hits 10224529 # ITB inst hits +system.cpu1.itb.inst_misses 7346 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1017,504 +1020,507 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses -system.cpu1.itb.hits 8214514 # DTB hits -system.cpu1.itb.misses 3039 # DTB misses -system.cpu1.itb.accesses 8217553 # DTB accesses -system.cpu1.numCycles 69079827 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses +system.cpu1.itb.hits 10224529 # DTB hits +system.cpu1.itb.misses 7346 # DTB misses +system.cpu1.itb.accesses 10231875 # DTB accesses +system.cpu1.numCycles 361675233 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits +system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued -system.cpu1.iq.rate 0.728958 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued +system.cpu1.iq.rate 0.267369 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50586 # number of nop insts executed -system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5808702 # Number of branches executed -system.cpu1.iew.exec_stores 5821790 # Number of stores executed -system.cpu1.iew.exec_rate 0.688543 # Inst execution rate -system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24255669 # num instructions producing a value -system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value +system.cpu1.iew.exec_nop 169844 # number of nop insts executed +system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7814764 # Number of branches executed +system.cpu1.iew.exec_stores 8083565 # Number of stores executed +system.cpu1.iew.exec_rate 0.259338 # Inst execution rate +system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 32803499 # num instructions producing a value +system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 30036983 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 38086237 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30036983 # Number of instructions committed -system.cpu1.commit.committedOps 38086237 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41355133 # Number of instructions committed +system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12651383 # Number of memory references committed -system.cpu1.commit.loads 7112761 # Number of loads committed -system.cpu1.commit.membars 148646 # Number of memory barriers committed -system.cpu1.commit.branches 4805168 # Number of branches committed -system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433251 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached +system.cpu1.commit.refs 18556919 # Number of memory references committed +system.cpu1.commit.loads 10922280 # Number of loads committed +system.cpu1.commit.membars 235767 # Number of memory barriers committed +system.cpu1.commit.branches 6572492 # Number of branches committed +system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions. +system.cpu1.commit.function_calls 612387 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102142645 # The number of ROB reads -system.cpu1.rob.rob_writes 116493771 # The number of ROB writes -system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30012429 # Number of Instructions Simulated -system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated -system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads -system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes -system.cpu1.icache.replacements 485586 # number of replacements -system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use -system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.788681 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7684975 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7684975 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7684975 # number of overall hits -system.cpu1.icache.overall_hits::total 7684975 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527035 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527035 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527035 # number of overall misses -system.cpu1.icache.overall_misses::total 527035 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7752735997 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7752735997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8212010 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8212010 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.064179 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.064179 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.064179 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14710.097047 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked +system.cpu1.rob.rob_reads 188242511 # The number of ROB reads +system.cpu1.rob.rob_writes 151809339 # The number of ROB writes +system.cpu1.timesIdled 1543775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 240936392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4782922080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41229306 # Number of Instructions Simulated +system.cpu1.committedOps 52547337 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated +system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads +system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes +system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads +system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes +system.cpu1.icache.replacements 696666 # number of replacements +system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use +system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 697178 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.575185 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.774287 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974169 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974169 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9464320 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9464320 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9464320 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9464320 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9464320 # number of overall hits +system.cpu1.icache.overall_hits::total 9464320 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 754908 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 754908 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 754908 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 754908 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 754908 # number of overall misses +system.cpu1.icache.overall_misses::total 754908 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11029274493 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11029274493 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11029274493 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11029274493 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11029274493 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11029274493 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10219228 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10219228 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10219228 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10219228 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10219228 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10219228 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073871 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073871 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073871 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14610.090889 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 231 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6290.021645 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 18538 # number of writebacks -system.cpu1.icache.writebacks::total 18538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 40914 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 40914 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 40914 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 40914 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 40914 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 40914 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 486121 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 486121 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 486121 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 486121 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 486121 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 486121 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 33177 # number of writebacks +system.cpu1.icache.writebacks::total 33177 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57704 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 57704 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 57704 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 57704 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 57704 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 57704 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 697204 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 697204 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 697204 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 697204 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 697204 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 697204 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8247682495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8247682495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272200 # number of replacements -system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.953212 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 7085363 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3139669 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75360 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72622 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10225032 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10225032 # number of overall hits -system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 323287 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1273508 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12669 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11046 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1596795 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1596795 # number of overall misses -system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87512500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87512500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 51388392837 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 51388392837 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 51388392837 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 51388392837 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7408650 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4413177 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 88029 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83668 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.043636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.288569 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143918 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.132022 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135072 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.390217 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36390.581243 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11695.043018 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7922.551150 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 407468 # number of replacements +system.cpu1.dcache.tagsinuse 452.466365 # Cycle average of tags in use +system.cpu1.dcache.total_refs 14808453 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 407980 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.297007 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 72560362000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 452.466365 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.883723 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.883723 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9771721 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9771721 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4750886 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4750886 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123631 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 123631 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116540 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 116540 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14522607 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14522607 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14522607 # number of overall hits +system.cpu1.dcache.overall_hits::total 14522607 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 451897 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 451897 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1700738 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1700738 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14109 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14109 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10120 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10120 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2152635 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2152635 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2152635 # number of overall misses +system.cpu1.dcache.overall_misses::total 2152635 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6794357500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6794357500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56737247402 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 56737247402 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 169367000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 169367000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85782500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 85782500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 63531604902 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 63531604902 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 63531604902 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 63531604902 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10223618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10223618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6451624 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6451624 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137740 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 137740 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126660 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 126660 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16675242 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16675242 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16675242 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16675242 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044201 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263614 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102432 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079899 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129092 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129092 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15035.190541 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33360.369088 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12004.181728 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8476.531621 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 14045059 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5012000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3121 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 132 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4500.179109 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37969.696970 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks -system.cpu1.dcache.writebacks::total 223077 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1291206 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1291206 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 305589 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 305589 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025557 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132468 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.132022 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8505.231112 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4915.535035 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks +system.cpu1.dcache.writebacks::total 337861 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -1533,16 +1539,16 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 1c96dc767..a1c7f49b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:39:00 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 21:01:11 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503580880500 because m5_exit instruction encountered +Exiting @ tick 2503289265500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 1df010cb5..d8269d3fd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503581 # Number of seconds simulated -sim_ticks 2503580880500 # Number of ticks simulated -final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503289 # Number of seconds simulated +sim_ticks 2503289265500 # Number of ticks simulated +final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80550 # Simulator instruction rate (inst/s) -host_op_rate 104045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3392180683 # Simulator tick rate (ticks/s) -host_mem_usage 382816 # Number of bytes of host memory used -host_seconds 738.04 # Real time elapsed on the host -sim_insts 59449329 # Number of instructions simulated -sim_ops 76789886 # Number of ops (including micro ops) simulated +host_inst_rate 81468 # Simulator instruction rate (inst/s) +host_op_rate 105230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3430236303 # Simulator tick rate (ticks/s) +host_mem_usage 383240 # Number of bytes of host memory used +host_seconds 729.77 # Real time elapsed on the host +sim_insts 59452703 # Number of instructions simulated +sim_ops 76793713 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130729872 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1100224 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585224 # Number of bytes written to this memory -system.physmem.num_reads 15117120 # Number of read requests responded to by this memory -system.physmem.num_writes 856661 # Number of write requests responded to by this memory +system.physmem.bytes_read 130753040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9587720 # Number of bytes written to this memory +system.physmem.num_reads 15117482 # Number of read requests responded to by this memory +system.physmem.num_writes 856700 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52217155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 439460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3828606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56045761 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119505 # number of replacements -system.l2c.tagsinuse 25834.929390 # Cycle average of tags in use -system.l2c.total_refs 1795685 # Total number of references to valid blocks. -system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. +system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119784 # number of replacements +system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use +system.l2c.total_refs 1841990 # Total number of references to valid blocks. +system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits -system.l2c.Writeback_hits::total 630148 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 9582 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 973305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 143695 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 9582 # number of overall hits -system.l2c.overall_hits::cpu.inst 973305 # number of overall hits -system.l2c.overall_hits::cpu.data 482200 # number of overall hits -system.l2c.overall_hits::total 1608782 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 134 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17088 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 134 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17088 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159397 # number of demand (read+write) misses -system.l2c.demand_misses::total 176635 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 134 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu.inst 17088 # number of overall misses -system.l2c.overall_misses::cpu.data 159397 # number of overall misses -system.l2c.overall_misses::total 176635 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 843500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 993024500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1895542500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7383005500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7383005500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 7004000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 843500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 894670500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 7004000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 843500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 894670500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8376030000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 143829 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 9598 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990393 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 395230 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 143829 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 9598 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990393 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 641597 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 143829 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 9598 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990393 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 641597 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency +system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5509.483052 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218343 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.094447 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.084068 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.397859 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 152573 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11543 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 997778 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 377343 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1539237 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 633058 # number of Writeback hits +system.l2c.Writeback_hits::total 633058 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 105979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105979 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 152573 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 997778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 483322 # number of demand (read+write) hits +system.l2c.demand_hits::total 1645216 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 152573 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11543 # number of overall hits +system.l2c.overall_hits::cpu.inst 997778 # number of overall hits +system.l2c.overall_hits::cpu.data 483322 # number of overall hits +system.l2c.overall_hits::total 1645216 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17347 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36655 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3332 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3332 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 140332 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140332 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17347 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159478 # number of demand (read+write) misses +system.l2c.demand_misses::total 176987 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 150 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu.inst 17347 # number of overall misses +system.l2c.overall_misses::cpu.data 159478 # number of overall misses +system.l2c.overall_misses::total 176987 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7830000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 643000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 909187000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001254500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1918914500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1009500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1009500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7379766000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7379766000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 7830000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 643000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 909187000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8381020500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9298680500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 7830000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 643000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 909187000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8381020500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9298680500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 152723 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1015125 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 396489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1575892 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 633058 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 633058 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3381 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3381 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246311 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246311 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 152723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11555 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1015125 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 642800 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1822203 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 152723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11555 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1015125 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 642800 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1822203 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001039 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017089 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048289 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985507 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569735 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001039 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017089 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248099 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001039 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017089 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248099 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52200 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53583.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52411.771488 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52295.753682 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 302.971188 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52587.905823 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -170,97 +170,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102643 # number of writebacks -system.l2c.writebacks::total 102643 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 102682 # number of writebacks +system.l2c.writebacks::total 102682 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 134 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 16 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17074 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 18920 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 3252 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 140397 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176541 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159317 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176541 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 685402500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 759038500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1450468000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 131324500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 150 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17335 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 19066 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36562 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3332 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3332 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140332 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140332 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17335 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159398 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176894 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17335 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159398 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176894 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6012000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 462000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 696908500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765299500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1468682000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6012000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 462000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 696908500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6402004000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7105386500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6012000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 462000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 696908500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6402004000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7105386500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131761112000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131766619000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -275,27 +278,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52219999 # DTB read hits -system.cpu.dtb.read_misses 90279 # DTB read misses -system.cpu.dtb.write_hits 11976179 # DTB write hits -system.cpu.dtb.write_misses 25577 # DTB write misses +system.cpu.dtb.read_hits 51991464 # DTB read hits +system.cpu.dtb.read_misses 102104 # DTB read misses +system.cpu.dtb.write_hits 11910179 # DTB write hits +system.cpu.dtb.write_misses 24558 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4346 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 6089 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 654 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4433 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2193 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52310278 # DTB read accesses -system.cpu.dtb.write_accesses 12001756 # DTB write accesses +system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52093568 # DTB read accesses +system.cpu.dtb.write_accesses 11934737 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64196178 # DTB hits -system.cpu.dtb.misses 115856 # DTB misses -system.cpu.dtb.accesses 64312034 # DTB accesses -system.cpu.itb.inst_hits 14123674 # ITB inst hits -system.cpu.itb.inst_misses 9885 # ITB inst misses +system.cpu.dtb.hits 63901643 # DTB hits +system.cpu.dtb.misses 126662 # DTB misses +system.cpu.dtb.accesses 64028305 # DTB accesses +system.cpu.itb.inst_hits 13706914 # ITB inst hits +system.cpu.itb.inst_misses 11634 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -304,504 +307,504 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2599 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2596 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 7902 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14133559 # ITB inst accesses -system.cpu.itb.hits 14123674 # DTB hits -system.cpu.itb.misses 9885 # DTB misses -system.cpu.itb.accesses 14133559 # DTB accesses -system.cpu.numCycles 415943429 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13718548 # ITB inst accesses +system.cpu.itb.hits 13706914 # DTB hits +system.cpu.itb.misses 11634 # DTB misses +system.cpu.itb.accesses 13718548 # DTB accesses +system.cpu.numCycles 414369636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16201364 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12549421 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1109380 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13917593 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10243002 # Number of BTB hits +system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1423675 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 227604 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32912368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104836271 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16201364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11666677 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24487466 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7079059 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 131458 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92859775 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145565 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217503 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14115008 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1041610 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4861 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155569254 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838536 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184070 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131107551 84.28% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1739904 1.12% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2616632 1.68% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3657999 2.35% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2164577 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1434404 0.92% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2630326 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 851935 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9365926 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155569254 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038951 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.252045 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35134284 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92713878 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21991115 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092987 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4636990 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2313958 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177730 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122065816 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 573184 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4636990 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37283411 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36813700 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49928995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20929371 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5976787 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113968448 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 915244 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3983499 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42655 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118524115 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 524000264 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523903687 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 96577 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492548 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 41031566 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1204512 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098851 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12310506 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21988549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14164932 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1902928 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2266136 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102902284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1875395 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126904684 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 253228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27017748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 72978464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 375688 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155569254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505343 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108923700 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15131938 9.73% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7543329 4.85% 84.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6524442 4.19% 88.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12759852 8.20% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2730334 1.76% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1400610 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422368 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132681 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155569254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45526 0.51% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8417505 94.61% 95.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 433723 4.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60099266 47.36% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96421 0.08% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2248 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53941927 42.51% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12658279 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126904684 # Type of FU issued -system.cpu.iq.rate 0.305101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8896761 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070106 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418619840 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131813494 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87332577 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23940 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13540 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10418 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135682181 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12734 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614286 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued +system.cpu.iq.rate 0.304001 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6307786 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32675 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2385852 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061916 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151020 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4636990 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28345844 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 418518 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104992332 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 473238 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21988549 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14164932 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 597023 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 929866 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 214653 # number of nop insts executed -system.cpu.iew.exec_refs 65406640 # number of memory reference insts executed -system.cpu.iew.exec_branches 11708135 # Number of branches executed -system.cpu.iew.exec_stores 12489378 # Number of stores executed -system.cpu.iew.exec_rate 0.296843 # Inst execution rate -system.cpu.iew.wb_sent 121811310 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87342995 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47060292 # num instructions producing a value -system.cpu.iew.wb_consumers 86666260 # num instructions consuming a value +system.cpu.iew.exec_nop 216034 # number of nop insts executed +system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed +system.cpu.iew.exec_branches 11571925 # Number of branches executed +system.cpu.iew.exec_stores 12419635 # Number of stores executed +system.cpu.iew.exec_rate 0.296062 # Inst execution rate +system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46911516 # num instructions producing a value +system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151014616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509489 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459114 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122165210 80.90% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14833013 9.82% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4110348 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2186082 1.45% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788351 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1361296 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1264343 0.84% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 665414 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2640559 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59599710 # Number of instructions committed -system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59603084 # Number of instructions committed +system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459843 # Number of memory references committed -system.cpu.commit.loads 15680763 # Number of loads committed -system.cpu.commit.membars 413065 # Number of memory barriers committed -system.cpu.commit.branches 9891047 # Number of branches committed +system.cpu.commit.refs 27461448 # Number of memory references committed +system.cpu.commit.loads 15681836 # Number of loads committed +system.cpu.commit.membars 413071 # Number of memory barriers committed +system.cpu.commit.branches 9891470 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68493330 # Number of committed integer instructions. -system.cpu.commit.function_calls 995601 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2640559 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. +system.cpu.commit.function_calls 995631 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251393815 # The number of ROB reads -system.cpu.rob.rob_writes 214319630 # The number of ROB writes -system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59449329 # Number of Instructions Simulated -system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated -system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads -system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559798057 # number of integer regfile reads -system.cpu.int_regfile_writes 89741069 # number of integer regfile writes -system.cpu.fp_regfile_reads 8257 # number of floating regfile reads -system.cpu.fp_regfile_writes 2814 # number of floating regfile writes -system.cpu.misc_regfile_reads 137366935 # number of misc regfile reads -system.cpu.misc_regfile_writes 912292 # number of misc regfile writes -system.cpu.icache.replacements 991177 # number of replacements -system.cpu.icache.tagsinuse 511.615293 # Cycle average of tags in use -system.cpu.icache.total_refs 13035657 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13035657 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13035657 # number of overall hits -system.cpu.icache.overall_hits::total 13035657 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079227 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079227 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079227 # number of overall misses -system.cpu.icache.overall_misses::total 1079227 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15906225491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15906225491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked +system.cpu.rob.rob_reads 248361579 # The number of ROB reads +system.cpu.rob.rob_writes 211126300 # The number of ROB writes +system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59452703 # Number of Instructions Simulated +system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated +system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556236612 # number of integer regfile reads +system.cpu.int_regfile_writes 88987615 # number of integer regfile writes +system.cpu.fp_regfile_reads 8813 # number of floating regfile reads +system.cpu.fp_regfile_writes 2942 # number of floating regfile writes +system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads +system.cpu.misc_regfile_writes 912350 # number of misc regfile writes +system.cpu.icache.replacements 1015901 # number of replacements +system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use +system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits +system.cpu.icache.overall_hits::total 12592690 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses +system.cpu.icache.overall_misses::total 1106667 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 57255 # number of writebacks -system.cpu.icache.writebacks::total 57255 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87505 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87505 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87505 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87505 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87505 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87505 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 58562 # number of writebacks +system.cpu.icache.writebacks::total 58562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643728 # number of replacements -system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22270301 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645034 # number of replacements +system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use +system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits -system.cpu.dcache.overall_hits::total 21681508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses -system.cpu.dcache.overall_misses::total 3688917 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 14161876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14161876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7265482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7265482 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 286317 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 286317 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285516 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285516 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21427358 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21427358 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21427358 # number of overall hits +system.cpu.dcache.overall_hits::total 21427358 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 733645 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 733645 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966203 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966203 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13700 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13700 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699848 # number of overall misses +system.cpu.dcache.overall_misses::total 3699848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121460107261 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121460107261 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25127206 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25127206 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25127206 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25127206 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045664 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.147245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15060.913657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37222.922120 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16284.562044 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16049941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7647500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2833 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5665.351571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27910.583942 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks -system.cpu.dcache.writebacks::total 572893 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 574496 # number of writebacks +system.cpu.dcache.writebacks::total 574496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3063259 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3063259 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387019 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387019 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249570 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249570 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636589 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636589 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.242895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35766.179593 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13401.288597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -820,14 +823,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 7b718bc11..e4f17be50 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:31:16 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:53:18 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5163317092500 because m5_exit instruction encountered +Exiting @ tick 5155288336500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 477cac0b5..1c3be5421 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,151 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.163317 # Number of seconds simulated -sim_ticks 5163317092500 # Number of ticks simulated -final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.155288 # Number of seconds simulated +sim_ticks 5155288336500 # Number of ticks simulated +final_tick 5155288336500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184798 # Simulator instruction rate (inst/s) -host_op_rate 364169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2236864416 # Simulator tick rate (ticks/s) -host_mem_usage 361200 # Number of bytes of host memory used -host_seconds 2308.28 # Real time elapsed on the host -sim_insts 426565585 # Number of instructions simulated -sim_ops 840604148 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15861056 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12134976 # Number of bytes written to this memory -system.physmem.num_reads 247829 # Number of read requests responded to by this memory -system.physmem.num_writes 189609 # Number of write requests responded to by this memory +host_inst_rate 187724 # Simulator instruction rate (inst/s) +host_op_rate 369929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2268413480 # Simulator tick rate (ticks/s) +host_mem_usage 362380 # Number of bytes of host memory used +host_seconds 2272.64 # Real time elapsed on the host +sim_insts 426629675 # Number of instructions simulated +sim_ops 840716593 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15943680 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1259264 # Number of instructions bytes read from this memory +system.physmem.bytes_written 12043648 # Number of bytes written to this memory +system.physmem.num_reads 249120 # Number of read requests responded to by this memory +system.physmem.num_writes 188182 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3071873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 238879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2350229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5422102 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 168510 # number of replacements -system.l2c.tagsinuse 37865.450237 # Cycle average of tags in use -system.l2c.total_refs 3777661 # Total number of references to valid blocks. -system.l2c.sampled_refs 200841 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.809212 # Average number of references to valid blocks. +system.physmem.bw_read 3092684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 244266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2336174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 5428858 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 167456 # number of replacements +system.l2c.tagsinuse 37822.927931 # Cycle average of tags in use +system.l2c.total_refs 3846980 # Total number of references to valid blocks. +system.l2c.sampled_refs 202165 # Sample count of references to valid blocks. +system.l2c.avg_refs 19.028912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 26765.864627 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.948564 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.042262 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2364.419048 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8723.175736 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.408415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 26706.608582 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.179185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.034739 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2430.963092 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8674.142332 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.407511 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000171 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.036078 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.133105 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.577781 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 134155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 7302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1001370 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1325429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1603120 # number of Writeback hits -system.l2c.Writeback_hits::total 1603120 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.037094 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.132357 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.577132 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 117941 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9215 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1064505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1335031 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2526692 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1602581 # number of Writeback hits +system.l2c.Writeback_hits::total 1602581 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 150704 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150704 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 134155 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 7302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1001370 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1476133 # number of demand (read+write) hits -system.l2c.demand_hits::total 2618960 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 134155 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 7302 # number of overall hits -system.l2c.overall_hits::cpu.inst 1001370 # number of overall hits -system.l2c.overall_hits::cpu.data 1476133 # number of overall hits -system.l2c.overall_hits::total 2618960 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 82 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 19273 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 44950 # number of ReadReq misses -system.l2c.ReadReq_misses::total 64315 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 5079 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5079 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141389 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 82 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 19273 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 186339 # number of demand (read+write) misses -system.l2c.demand_misses::total 205704 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 82 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu.inst 19273 # number of overall misses -system.l2c.overall_misses::cpu.data 186339 # number of overall misses -system.l2c.overall_misses::total 205704 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 4278000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 521000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 1007154000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 2362722500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3374675500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 37477500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 37477500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7363267000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7363267000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 4278000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 1007154000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 9725989500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10737942500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 4278000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 521000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 1007154000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 9725989500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10737942500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 134237 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 7312 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1020643 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1370379 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2532571 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1603120 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 5401 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292093 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292093 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 134237 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 7312 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1020643 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1662472 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2824664 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 134237 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 7312 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1020643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1662472 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2824664 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000611 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.018883 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.032801 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.940381 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.484055 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000611 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001368 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.018883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.112085 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000611 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001368 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.018883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.112085 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52170.731707 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52100 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52257.251077 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52563.348165 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7378.913172 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52078.075381 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 151453 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151453 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 117941 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9215 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1064505 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1486484 # number of demand (read+write) hits +system.l2c.demand_hits::total 2678145 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 117941 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9215 # number of overall hits +system.l2c.overall_hits::cpu.inst 1064505 # number of overall hits +system.l2c.overall_hits::cpu.data 1486484 # number of overall hits +system.l2c.overall_hits::total 2678145 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 98 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 19677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 45243 # number of ReadReq misses +system.l2c.ReadReq_misses::total 65025 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2687 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2687 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 141494 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 141494 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 98 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 19677 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 186737 # number of demand (read+write) misses +system.l2c.demand_misses::total 206519 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 98 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu.inst 19677 # number of overall misses +system.l2c.overall_misses::cpu.data 186737 # number of overall misses +system.l2c.overall_misses::total 206519 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5116000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 1028234500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 2378237500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3411952000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 39192000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 39192000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7368603000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7368603000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 5116000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 1028234500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 9746840500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10780555000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 5116000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 1028234500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 9746840500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10780555000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 118039 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9222 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1084182 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1380274 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2591717 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1602581 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1602581 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3009 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3009 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292947 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292947 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 118039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9222 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1084182 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1673221 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2884664 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 118039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9222 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1084182 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1673221 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2884664 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000759 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.018149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.032778 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.892988 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.483002 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000830 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000759 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.018149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.111603 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000830 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000759 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.018149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.111603 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52204.081633 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52255.653809 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52565.866543 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 14585.783402 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.141080 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52204.081633 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52255.653809 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52195.550427 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -154,8 +154,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 142942 # number of writebacks -system.l2c.writebacks::total 142942 # number of writebacks +system.l2c.writebacks::writebacks 141515 # number of writebacks +system.l2c.writebacks::total 141515 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -165,157 +165,157 @@ system.l2c.demand_mshr_hits::total 2 # nu system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 82 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 19272 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 44949 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 64313 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 5079 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 5079 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 141389 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 141389 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 82 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 19272 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 186338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 205702 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 82 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 19272 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 186338 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 205702 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 3286000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 771698500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1813525000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2588909500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 203533000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 203533000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5656832000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5656832000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 3286000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 771698500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 7470357000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8245741500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 3286000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 771698500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 7470357000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8245741500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975483500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59975483500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1228994000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1228994000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204477500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61204477500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032800 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.940381 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.484055 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average ReadReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 98 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 19676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 45242 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 65023 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2687 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2687 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 141494 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 141494 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 98 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 19676 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 186736 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 206517 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 98 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 19676 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 186736 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 206517 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 3927500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 787879000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1825148000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2617234500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 107845000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 107845000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5661229500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5661229500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 3927500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 787879000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 7486377500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8278464000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 3927500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 787879000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 7486377500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8278464000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975987000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59975987000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1230144500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1230144500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206131500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61206131500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032778 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.892988 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.483002 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.470942 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40346.281341 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40073.439653 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.996457 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.640781 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40341.894700 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40135.839226 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.385599 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47580 # number of replacements -system.iocache.tagsinuse 0.183883 # Cycle average of tags in use +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.159321 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47596 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.183883 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.011493 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.011493 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 915 # number of ReadReq misses +system.iocache.warmup_cycle 4996368196000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.159321 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009958 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009958 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses -system.iocache.demand_misses::total 47635 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses -system.iocache.overall_misses::total 47635 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114575932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 114575932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6365614160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6365614160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6480190092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6480190092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6480190092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6480190092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114195932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 114195932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6370894160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6370894160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6485090092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6485090092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6485090092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6485090092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125219.597814 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136250.303082 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125352.285401 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136363.316781 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 68835510 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11261 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6112.735103 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66972982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66972982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3935855798 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3935855798 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4002828780 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4002828780 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66802976 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66802976 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3941136864 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3941136864 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4007939840 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4007939840 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73194.515847 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84243.488827 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73329.282108 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84356.525342 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -329,395 +329,395 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 462460674 # number of cpu cycles simulated +system.cpu.numCycles 461736319 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91001984 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91001984 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1246670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89740974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83587498 # Number of BTB hits +system.cpu.BPredUnit.lookups 90084371 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90084371 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1179546 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84316538 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81732802 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28956413 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449639850 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91001984 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83587498 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171222727 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5870168 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 127753 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 101915873 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 38952 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9672092 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 512695 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3312 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 306883426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.884320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.377751 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29640549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 447158079 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90084371 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81732802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169862026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5320379 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 145881 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102119338 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 39504 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9392758 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 524186 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5360 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 305948772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.876024 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.383488 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136151197 44.37% 44.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1833476 0.60% 44.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72801112 23.72% 68.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1413943 0.46% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1812929 0.59% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3984448 1.30% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1563806 0.51% 71.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1664583 0.54% 72.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85657932 27.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136524607 44.62% 44.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1781462 0.58% 45.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72780882 23.79% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 993009 0.32% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1639605 0.54% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3682017 1.20% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1148071 0.38% 71.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1456036 0.48% 71.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85943083 28.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 306883426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.196778 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.972277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34101035 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98103338 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165554285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4539875 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4584893 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881320225 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 609 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4584893 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38485909 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67729275 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11421097 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165177226 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19485026 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 876989303 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10814 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12483638 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3869558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 878639289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1719877661 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1719877141 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843209199 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35430083 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491480 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 496551 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46051608 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19446241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10506071 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1193626 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 915732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869497074 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1725725 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866404799 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123854 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29753009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42786279 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206033 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 306883426 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.823238 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.403588 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 305948772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195099 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.968427 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34742596 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98230101 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164036692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4836131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4103252 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876669813 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 827 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4103252 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39030266 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68185463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10584671 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 164072016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19973104 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872862955 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10194 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12946310 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3889382 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 874188806 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1710305089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1710304369 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 720 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843320455 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30868344 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 477917 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 485258 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46626951 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18944692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10483519 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1301190 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1038101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865973387 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1727922 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864611178 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114248 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26054957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37073399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 305948772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.826000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.403043 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 100067522 32.61% 32.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25349299 8.26% 40.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 13936726 4.54% 45.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9650933 3.14% 48.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79503599 25.91% 74.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4853866 1.58% 76.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72832557 23.73% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 561211 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127713 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99370843 32.48% 32.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25451279 8.32% 40.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14262788 4.66% 45.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9410835 3.08% 48.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79123808 25.86% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4863158 1.59% 75.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72802263 23.80% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533166 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130632 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 306883426 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 305948772 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 188296 8.84% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1773429 83.29% 92.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 167520 7.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 169581 8.02% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1777046 84.08% 92.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 166802 7.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304337 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831186392 95.94% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25424398 2.93% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9489672 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 304260 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829639344 95.96% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25194661 2.91% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472913 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866404799 # Type of FU issued -system.cpu.iq.rate 1.873467 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2129245 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2042097119 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 900986111 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855761606 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 229 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868229599 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1634850 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864611178 # Type of FU issued +system.cpu.iq.rate 1.872521 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2113429 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2037542293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893767044 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 854207329 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 316 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866420202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1589122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4122229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17231 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11383 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2082513 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3614563 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21772 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12029 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2051269 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821289 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4333 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821662 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2623 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4584893 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45441721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6142722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871222799 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 285751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19446241 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10506071 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 891740 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5368443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12385 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11383 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 896223 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525625 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1421848 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864338156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24982156 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2066642 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4103252 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45514835 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6136303 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867701309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 314417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18944692 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10483519 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 889203 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5413874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12817 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12029 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 702671 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628126 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1330797 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862708188 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24767979 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1902989 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34234409 # number of memory reference insts executed -system.cpu.iew.exec_branches 86668621 # Number of branches executed -system.cpu.iew.exec_stores 9252253 # Number of stores executed -system.cpu.iew.exec_rate 1.868998 # Inst execution rate -system.cpu.iew.wb_sent 863811947 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855761668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 670084242 # num instructions producing a value -system.cpu.iew.wb_consumers 1169301773 # num instructions consuming a value +system.cpu.iew.exec_refs 33996128 # number of memory reference insts executed +system.cpu.iew.exec_branches 86527576 # Number of branches executed +system.cpu.iew.exec_stores 9228149 # Number of stores executed +system.cpu.iew.exec_rate 1.868400 # Inst execution rate +system.cpu.iew.wb_sent 862244747 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 854207409 # cumulative count of insts written-back +system.cpu.iew.wb_producers 668533054 # num instructions producing a value +system.cpu.iew.wb_consumers 1167360089 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back +system.cpu.iew.wb_rate 1.849990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572688 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426565585 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840604148 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 302314482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.780562 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862970 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426629675 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840716593 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26871696 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1520650 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1183899 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 301861557 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.785107 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863294 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547491 40.21% 40.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14447999 4.78% 44.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4300765 1.42% 46.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76650469 25.35% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3947228 1.31% 73.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1803648 0.60% 73.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1077125 0.36% 74.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984746 23.81% 97.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6555011 2.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121093745 40.12% 40.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14426665 4.78% 44.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4304237 1.43% 46.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76676312 25.40% 71.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3920373 1.30% 73.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1782325 0.59% 73.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109784 0.37% 73.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71984231 23.85% 97.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6563885 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426565585 # Number of instructions committed -system.cpu.commit.committedOps 840604148 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 301861557 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426629675 # Number of instructions committed +system.cpu.commit.committedOps 840716593 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23747567 # Number of memory references committed -system.cpu.commit.loads 15324009 # Number of loads committed -system.cpu.commit.membars 781567 # Number of memory barriers committed -system.cpu.commit.branches 85515141 # Number of branches committed +system.cpu.commit.refs 23762376 # Number of memory references committed +system.cpu.commit.loads 15330126 # Number of loads committed +system.cpu.commit.membars 781563 # Number of memory barriers committed +system.cpu.commit.branches 85529575 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768433298 # Number of committed integer instructions. +system.cpu.commit.int_insts 768542107 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6555011 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6563885 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166791668 # The number of ROB reads -system.cpu.rob.rob_writes 1746826364 # The number of ROB writes -system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426565585 # Number of Instructions Simulated -system.cpu.committedOps 840604148 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426565585 # Number of Instructions Simulated -system.cpu.cpi 1.084149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.084149 # CPI: Total CPI of All Threads -system.cpu.ipc 0.922382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.922382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads -system.cpu.int_regfile_writes 857070459 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.misc_regfile_reads 281985005 # number of misc regfile reads -system.cpu.misc_regfile_writes 409504 # number of misc regfile writes -system.cpu.icache.replacements 1020153 # number of replacements -system.cpu.icache.tagsinuse 509.928344 # Cycle average of tags in use -system.cpu.icache.total_refs 8587640 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.928344 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995954 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995954 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8587640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8587640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8587640 # number of overall hits -system.cpu.icache.overall_hits::total 8587640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1084449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1084449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1084449 # number of overall misses -system.cpu.icache.overall_misses::total 1084449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16282601991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16282601991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16282601991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16282601991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16282601991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16282601991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9672089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9672089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9672089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.112121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.112121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15014.631385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1162802870 # The number of ROB reads +system.cpu.rob.rob_writes 1739294618 # The number of ROB writes +system.cpu.timesIdled 2882631 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155787547 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9848837790 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426629675 # Number of Instructions Simulated +system.cpu.committedOps 840716593 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426629675 # Number of Instructions Simulated +system.cpu.cpi 1.082288 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.082288 # CPI: Total CPI of All Threads +system.cpu.ipc 0.923968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.923968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1404705112 # number of integer regfile reads +system.cpu.int_regfile_writes 855482985 # number of integer regfile writes +system.cpu.fp_regfile_reads 80 # number of floating regfile reads +system.cpu.misc_regfile_reads 281196998 # number of misc regfile reads +system.cpu.misc_regfile_writes 410876 # number of misc regfile writes +system.cpu.icache.replacements 1083725 # number of replacements +system.cpu.icache.tagsinuse 510.022776 # Cycle average of tags in use +system.cpu.icache.total_refs 8238065 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1084236 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.598037 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56617488000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.022776 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996138 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8238065 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8238065 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8238065 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8238065 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8238065 # number of overall hits +system.cpu.icache.overall_hits::total 8238065 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154689 # number of overall misses +system.cpu.icache.overall_misses::total 1154689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17243109487 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17243109487 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17243109487 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17243109487 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17243109487 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17243109487 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9392754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9392754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9392754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9392754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9392754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9392754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122934 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122934 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122934 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14933.120076 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2884989 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9616.630000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1551 # number of writebacks -system.cpu.icache.writebacks::total 1551 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1024341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1024341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1024341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1024341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1024341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1024341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12392610492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12392610492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12392610492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12392610492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12392610492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12392610492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12098.129912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1570 # number of writebacks +system.cpu.icache.writebacks::total 1570 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1085525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1085525 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1085525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1085525 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1085525 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1085525 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13103385489 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13103385489 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13103385489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13103385489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13103385489 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13103385489 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12071.012173 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 8553 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26637 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.010935 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375683 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375683 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26742 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11375 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.006905 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28918 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11386 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.539786 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5142961834000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006905 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375432 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375432 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28987 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28987 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26745 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9424 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9424 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9424 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 120935500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 120935500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 120935500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 120935500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 120935500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 120935500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36166 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28990 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28990 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28990 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28990 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12232 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12232 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12232 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12232 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12232 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12232 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 154656000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 154656000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 154656000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 154656000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 154656000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 154656000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41219 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36169 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36169 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.260576 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.260555 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.260555 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12832.714346 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.296756 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.296735 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.296735 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12643.557881 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -726,66 +726,66 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9424 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9424 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9424 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9424 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9424 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9424 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 92324000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 92324000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 92324000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 92324000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 92324000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 92324000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.260576 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1402 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1402 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12232 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12232 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12232 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12232 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12232 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12232 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 117502000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 117502000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 117502000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 117502000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 117502000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 117502000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.296756 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 140574 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 148049 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.858803 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866175 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866175 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 148058 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 148058 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 148058 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 141571 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 141571 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 141571 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1989434500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1989434500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1989434500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1989434500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1989434500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1989434500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 289629 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 289629 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 289629 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.488801 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.488801 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.488801 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 14052.556668 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 125889 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.942075 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 147310 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 125903 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.170028 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108639465000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942075 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808880 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808880 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 147324 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 147324 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 147324 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 147324 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 147324 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 147324 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 126858 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 126858 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 126858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 126858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 126858 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 126858 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1765137000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1765137000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1765137000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1765137000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1765137000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1765137000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 274182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 274182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 274182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 274182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 274182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 274182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.462678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.462678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.462678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13914.274228 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,124 +794,124 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 49457 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 49457 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 141571 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 141571 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 141571 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 141571 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 141571 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 141571 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1560743500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1560743500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1560743500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 38155 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 38155 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 126858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 126858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 126858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 126858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 126858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 126858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1381422000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1381422000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1381422000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1662584 # number of replacements -system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use -system.cpu.dcache.total_refs 19274168 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995323 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11173849 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093995 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19267844 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19267844 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19267844 # number of overall hits -system.cpu.dcache.overall_hits::total 19267844 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2389581 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2389581 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 320205 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 320205 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2709786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2709786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2709786 # number of overall misses -system.cpu.dcache.overall_misses::total 2709786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35746262500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35746262500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10712131492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10712131492 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46458393992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46458393992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46458393992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46458393992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563430 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563430 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8414200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8414200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21977630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21977630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21977630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21977630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.176178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038055 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.123297 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.123297 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14959.217746 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33453.979457 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked +system.cpu.dcache.replacements 1673228 # number of replacements +system.cpu.dcache.tagsinuse 511.997037 # Cycle average of tags in use +system.cpu.dcache.total_refs 19088314 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673740 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.404587 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997037 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10979879 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10979879 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8104687 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8104687 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19084566 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19084566 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19084566 # number of overall hits +system.cpu.dcache.overall_hits::total 19084566 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2411794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2411794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318210 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318210 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2730004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2730004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2730004 # number of overall misses +system.cpu.dcache.overall_misses::total 2730004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36160191000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36160191000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10588613980 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10588613980 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46748804980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46748804980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46748804980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46748804980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13391673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13391673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8422897 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422897 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21814570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21814570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21814570 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21814570 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180097 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037779 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.125146 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.125146 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14993.067816 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33275.553817 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23292480 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3427 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.755179 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1550496 # number of writebacks -system.cpu.dcache.writebacks::total 1550496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018010 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1018010 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22803 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22803 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1040813 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1040813 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1040813 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1040813 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371571 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371571 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 297402 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 297402 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1668973 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1668973 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1668973 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1668973 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013626000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013626000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9484899492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9484899492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27498525492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27498525492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27498525492 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27498525492 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207760000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207760000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600268500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600268500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101123 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035345 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13133.571649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31892.520871 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561454 # number of writebacks +system.cpu.dcache.writebacks::total 1561454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030426 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1030426 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22364 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1052790 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1052790 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1052790 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1052790 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381368 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381368 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295846 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 295846 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1677214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1677214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1677214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1677214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18158276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18158276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9372225480 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9372225480 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27530501480 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27530501480 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27530501480 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27530501480 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208380500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208380500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393791500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393791500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602172000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602172000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035124 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13145.140180 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31679.405772 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 26d645fed..f0d94be3d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:21 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:26 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274500333500 because target called exit() +Exiting @ tick 274300226500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 1a8f04561..206fd9b5c 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274500 # Number of seconds simulated -sim_ticks 274500333500 # Number of ticks simulated -final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274300 # Number of seconds simulated +sim_ticks 274300226500 # Number of ticks simulated +final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160535 # Simulator instruction rate (inst/s) -host_op_rate 160535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73218214 # Simulator tick rate (ticks/s) +host_inst_rate 157937 # Simulator instruction rate (inst/s) +host_op_rate 157937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71980747 # Simulator tick rate (ticks/s) host_mem_usage 209892 # Number of bytes of host memory used -host_seconds 3749.07 # Real time elapsed on the host +host_seconds 3810.74 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894016 # Number of bytes read from this memory +system.physmem.bytes_read 5894080 # Number of bytes read from this memory system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798080 # Number of bytes written to this memory -system.physmem.num_reads 92094 # Number of read requests responded to by this memory -system.physmem.num_writes 59345 # Number of write requests responded to by this memory +system.physmem.bytes_written 3798144 # Number of bytes written to this memory +system.physmem.num_reads 92095 # Number of read requests responded to by this memory +system.physmem.num_writes 59346 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517577 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39666597 # DTB write hits +system.cpu.dtb.read_accesses 114520208 # DTB read accesses +system.cpu.dtb.write_hits 39666608 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668899 # DTB write accesses -system.cpu.dtb.data_hits 154184165 # DTB hits +system.cpu.dtb.write_accesses 39668910 # DTB write accesses +system.cpu.dtb.data_hits 154184185 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189098 # DTB accesses -system.cpu.itb.fetch_hits 27986226 # ITB hits +system.cpu.dtb.data_accesses 154189118 # DTB accesses +system.cpu.itb.fetch_hits 25020502 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 27986248 # ITB accesses +system.cpu.itb.fetch_accesses 25020524 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 549000668 # number of cpu cycles simulated +system.cpu.numCycles 548600454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. -system.cpu.activity 89.164571 # Percentage of cycles cpu is active +system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. +system.cpu.activity 89.165242 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads -system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits +system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154582342 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051949 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use -system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use +system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits -system.cpu.icache.overall_hits::total 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses -system.cpu.icache.overall_misses::total 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits +system.cpu.icache.overall_hits::total 25019479 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits -system.cpu.dcache.overall_hits::total 152394244 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits +system.cpu.dcache.overall_hits::total 152394215 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses -system.cpu.dcache.overall_misses::total 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses +system.cpu.dcache.overall_misses::total 1571148 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks -system.cpu.dcache.writebacks::total 408188 # number of writebacks +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -269,75 +269,75 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73797 # number of replacements -system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73798 # number of replacements +system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408188 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408188 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194105 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 364156 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 364156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 364156 # number of overall hits -system.cpu.l2cache.overall_hits::total 364156 # number of overall hits +system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 364155 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 364155 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits +system.cpu.l2cache.overall_hits::total 364155 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60075 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60076 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60076 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91239 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92094 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 92095 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91239 # number of overall misses -system.cpu.l2cache.overall_misses::total 92094 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44769000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630148000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1674917000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3134446000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44769000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses +system.cpu.l2cache.overall_misses::total 92095 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -345,65 +345,65 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks -system.cpu.l2cache.writebacks::total 59345 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks +system.cpu.l2cache.writebacks::total 59346 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index e473c70fd..2e14d6c64 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:26 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:40 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 144450185500 because target called exit() +Exiting @ tick 134621123500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 6a8942beb..001739477 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144450 # Number of seconds simulated -sim_ticks 144450185500 # Number of ticks simulated -final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134621 # Number of seconds simulated +sim_ticks 134621123500 # Number of ticks simulated +final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 270959 # Simulator instruction rate (inst/s) -host_op_rate 270959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69206896 # Simulator tick rate (ticks/s) -host_mem_usage 211048 # Number of bytes of host memory used -host_seconds 2087.22 # Real time elapsed on the host +host_inst_rate 282179 # Simulator instruction rate (inst/s) +host_op_rate 282179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67168296 # Simulator tick rate (ticks/s) +host_mem_usage 211096 # Number of bytes of host memory used +host_seconds 2004.24 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5936768 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797120 # Number of bytes written to this memory -system.physmem.num_reads 92762 # Number of read requests responded to by this memory -system.physmem.num_writes 59330 # Number of write requests responded to by this memory +system.physmem.bytes_read 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3797952 # Number of bytes written to this memory +system.physmem.num_reads 92775 # Number of read requests responded to by this memory +system.physmem.num_writes 59343 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125584378 # DTB read hits -system.cpu.dtb.read_misses 26780 # DTB read misses +system.cpu.dtb.read_hits 123836708 # DTB read hits +system.cpu.dtb.read_misses 23555 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125611158 # DTB read accesses -system.cpu.dtb.write_hits 41433696 # DTB write hits -system.cpu.dtb.write_misses 32002 # DTB write misses +system.cpu.dtb.read_accesses 123860263 # DTB read accesses +system.cpu.dtb.write_hits 40831838 # DTB write hits +system.cpu.dtb.write_misses 31545 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41465698 # DTB write accesses -system.cpu.dtb.data_hits 167018074 # DTB hits -system.cpu.dtb.data_misses 58782 # DTB misses +system.cpu.dtb.write_accesses 40863383 # DTB write accesses +system.cpu.dtb.data_hits 164668546 # DTB hits +system.cpu.dtb.data_misses 55100 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167076856 # DTB accesses -system.cpu.itb.fetch_hits 70952399 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 164723646 # DTB accesses +system.cpu.itb.fetch_hits 66483943 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 70952439 # ITB accesses +system.cpu.itb.fetch_accesses 66483980 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 288900372 # number of cpu cycles simulated +system.cpu.numCycles 269242248 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits +system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued -system.cpu.iq.rate 2.148217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued +system.cpu.iq.rate 2.259665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45034525 # number of nop insts executed -system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed -system.cpu.iew.exec_branches 68658345 # Number of branches executed -system.cpu.iew.exec_stores 41485194 # Number of stores executed -system.cpu.iew.exec_rate 2.122282 # Inst execution rate -system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420036286 # num instructions producing a value -system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value +system.cpu.iew.exec_nop 43926324 # number of nop insts executed +system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed +system.cpu.iew.exec_branches 67006670 # Number of branches executed +system.cpu.iew.exec_stores 40880471 # Number of stores executed +system.cpu.iew.exec_rate 2.238049 # Inst execution rate +system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417486240 # num instructions producing a value +system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back +system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 935932678 # The number of ROB reads -system.cpu.rob.rob_writes 1385724156 # The number of ROB writes -system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 898866221 # The number of ROB reads +system.cpu.rob.rob_writes 1350401622 # The number of ROB writes +system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads -system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 863490102 # number of integer regfile reads -system.cpu.int_regfile_writes 500818441 # number of integer regfile writes -system.cpu.fp_regfile_reads 272 # number of floating regfile reads +system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads +system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848641681 # number of integer regfile reads +system.cpu.int_regfile_writes 492726607 # number of integer regfile writes +system.cpu.fp_regfile_reads 387 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use -system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. +system.cpu.icache.replacements 49 # number of replacements +system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use +system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits -system.cpu.icache.overall_hits::total 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses -system.cpu.icache.overall_misses::total 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits +system.cpu.icache.overall_hits::total 66482496 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses +system.cpu.icache.overall_misses::total 1447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,245 +371,253 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470690 # number of replacements -system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use -system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits -system.cpu.dcache.overall_hits::total 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses -system.cpu.dcache.overall_misses::total 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460743 # number of replacements +system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use +system.cpu.dcache.total_refs 149091432 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464839 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 320.737787 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126301000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.783086 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 110940808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 110940808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38150562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits +system.cpu.dcache.overall_hits::total 149091370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses +system.cpu.dcache.overall_misses::total 2023111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31385446422 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31385446422 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111663160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111663160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 423044 # number of writebacks -system.cpu.dcache.writebacks::total 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 513277 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1560950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 218764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 256022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks +system.cpu.dcache.writebacks::total 415225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74463 # number of replacements -system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74480 # number of replacements +system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use +system.cpu.l2cache.total_refs 461925 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90375 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.111203 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15917.792095 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 36.116254 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1707.803688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.485772 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.538993 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 186750 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 186750 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 423044 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 423044 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 196218 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 196218 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 382968 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 382968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 382968 # number of overall hits -system.cpu.l2cache.overall_hits::total 382968 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 944 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32014 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32958 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 59804 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 59804 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 944 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91818 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92762 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 944 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91818 # number of overall misses -system.cpu.l2cache.overall_misses::total 92762 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32444500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101235500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1133680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2065878500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2065878500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32444500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3167114000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3199558500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32444500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3167114000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3199558500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 944 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 218764 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 219708 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 423044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 423044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 256022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 256022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 944 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 474786 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 475730 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 944 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 474786 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 475730 # number of overall (read+write) accesses +system.cpu.l2cache.occ_blocks::writebacks 15915.661195 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 39.497783 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1695.845621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.485707 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001205 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051753 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.538666 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 178382 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 178382 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 415225 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 415225 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 194684 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 194684 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 373066 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 373066 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 373066 # number of overall hits +system.cpu.l2cache.overall_hits::total 373066 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1002 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31935 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32937 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 59838 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 59838 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1002 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 91773 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 92775 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1002 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 91773 # number of overall misses +system.cpu.l2cache.overall_misses::total 92775 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34422500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1098528500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1132951000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066830500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2066830500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 34422500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3165359000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3199781500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 34422500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3165359000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3199781500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1002 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210317 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 415225 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 415225 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254522 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1002 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464839 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465841 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1002 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464839 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.146340 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.233589 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.193388 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.193388 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6928.571429 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59330 # number of writebacks -system.cpu.l2cache.writebacks::total 59330 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32014 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91818 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91818 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92762 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29409000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 992936000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1022345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1877543500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1877543500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29409000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2870479500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2899888500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29409000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2870479500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2899888500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 59343 # number of writebacks +system.cpu.l2cache.writebacks::total 59343 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31935 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59838 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 59838 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91773 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92775 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31203000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 990467000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1021670000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1878462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1878462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31203000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2868929500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2900132500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31203000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.146340 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index c2143f70c..4180d507c 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:39:44 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:00:24 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 177116942500 because target called exit() +Exiting @ tick 164280509500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e204ea2b2..65753c5e3 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.177117 # Number of seconds simulated -sim_ticks 177116942500 # Number of ticks simulated -final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164281 # Number of seconds simulated +sim_ticks 164280509500 # Number of ticks simulated +final_tick 164280509500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193712 # Simulator instruction rate (inst/s) -host_op_rate 204690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60186856 # Simulator tick rate (ticks/s) -host_mem_usage 223404 # Number of bytes of host memory used -host_seconds 2942.78 # Real time elapsed on the host -sim_insts 570051603 # Number of instructions simulated -sim_ops 602359810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5833792 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3720320 # Number of bytes written to this memory -system.physmem.num_reads 91153 # Number of read requests responded to by this memory -system.physmem.num_writes 58130 # Number of write requests responded to by this memory +host_inst_rate 203818 # Simulator instruction rate (inst/s) +host_op_rate 215370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58737354 # Simulator tick rate (ticks/s) +host_mem_usage 223536 # Number of bytes of host memory used +host_seconds 2796.87 # Real time elapsed on the host +sim_insts 570051663 # Number of instructions simulated +sim_ops 602359870 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5845888 # Number of bytes read from this memory +system.physmem.bytes_inst_read 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3721728 # Number of bytes written to this memory +system.physmem.num_reads 91342 # Number of read requests responded to by this memory +system.physmem.num_writes 58152 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 32937515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 265226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 21004879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 53942395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35584793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 300754 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22654714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58239508 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 354233886 # number of cpu cycles simulated +system.cpu.numCycles 328561020 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91144697 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 84232652 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4003225 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86347481 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80064419 # Number of BTB hits +system.cpu.BPredUnit.lookups 85502166 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80303538 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2364558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47128818 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46810492 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1704141 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1603 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 76798037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 703840817 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91144697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81768560 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 159197395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18458844 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 103018501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 74422546 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1338162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127927 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980484 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441322 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2014 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68931697 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669727391 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85502166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48251814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130042659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13473975 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117702916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67497554 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807456 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.177756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200257 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194196282 54.95% 54.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25625707 7.25% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19294200 5.46% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24432014 6.91% 74.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11774546 3.33% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13391437 3.79% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4604134 1.30% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7796226 2.21% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52278982 14.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197667987 60.32% 60.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955558 6.39% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944545 1.51% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317291 4.37% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8979833 2.74% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9404994 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4387469 1.34% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814392 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61238365 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257301 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 98941962 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83442113 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 137180071 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19452898 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14376484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6300700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2518 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 740147617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7037 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14376484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 111904204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9631562 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118839 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 143566748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73795691 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 727217623 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 278 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59684680 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10267337 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 752950298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3380504235 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3380504107 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260232 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038365 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93127005 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94874868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108614475 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20063382 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11030704 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784748 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1773 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706010986 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5362 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11030704 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107410901 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13982712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118932 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114322879 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80844306 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697216799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59255173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19368550 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 660 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723821711 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241352610 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241352482 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 125532896 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13135 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13128 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 131736703 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 179759563 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82851365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19142240 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24648771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 702464419 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9443 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 663065354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 737309 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 99563138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 237077273 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3096 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 353393528 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.733355 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417498 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96404213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11540 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169974240 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172906537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80619433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21532364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27969964 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681972253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9148 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646841509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79435960 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197814866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2789 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327710434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.973820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.737996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 85420653 24.17% 24.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90592891 25.64% 49.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76061550 21.52% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 42517322 12.03% 83.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 25489615 7.21% 90.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18140901 5.13% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7279964 2.06% 97.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6670408 1.89% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1220224 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68514298 20.91% 20.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84850419 25.89% 46.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75242172 22.96% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40564366 12.38% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28638763 8.74% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15215694 4.64% 95.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5886369 1.80% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6524912 1.99% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2273441 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 353393528 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327710434 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202199 4.87% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2984693 71.84% 76.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 967527 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205233 5.10% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2909479 72.37% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 905756 22.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412589272 62.22% 62.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172499638 26.02% 88.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 77969869 11.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403929410 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6579 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166116267 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76789250 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 663065354 # Type of FU issued -system.cpu.iq.rate 1.871829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4154419 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006265 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1684415928 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 802048612 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650214601 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646841509 # Type of FU issued +system.cpu.iq.rate 1.968710 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4020468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006216 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626837984 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761428768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638548229 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 667219753 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650861957 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29667951 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30419634 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30806967 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 225012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11842 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12630350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23953929 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 128648 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11649 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10398406 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13680 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12577 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12456 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14376484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 831826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 58719 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 702543187 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1852399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 179759563 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 82851365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 8113 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13094 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5271 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11842 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4161334 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494337 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4655671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656082264 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169130146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6983090 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11030704 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 854813 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 57677 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682047620 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 663984 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172906537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80619433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7812 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4667 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11649 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1314819 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1584401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2899220 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642689835 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163986431 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4151674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69325 # number of nop insts executed -system.cpu.iew.exec_refs 245820033 # number of memory reference insts executed -system.cpu.iew.exec_branches 76462484 # Number of branches executed -system.cpu.iew.exec_stores 76689887 # Number of stores executed -system.cpu.iew.exec_rate 1.852116 # Inst execution rate -system.cpu.iew.wb_sent 652222843 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650214617 # cumulative count of insts written-back -system.cpu.iew.wb_producers 423345319 # num instructions producing a value -system.cpu.iew.wb_consumers 657402766 # num instructions consuming a value +system.cpu.iew.exec_nop 66219 # number of nop insts executed +system.cpu.iew.exec_refs 239991845 # number of memory reference insts executed +system.cpu.iew.exec_branches 74670108 # Number of branches executed +system.cpu.iew.exec_stores 76005414 # Number of stores executed +system.cpu.iew.exec_rate 1.956075 # Inst execution rate +system.cpu.iew.wb_sent 640041427 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638548245 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420154647 # num instructions producing a value +system.cpu.iew.wb_consumers 654937446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943469 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641519 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 339017045 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.776783 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.152670 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570051714 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359921 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79697124 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6359 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2424958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316679731 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108187576 31.91% 31.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 106522126 31.42% 63.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49316522 14.55% 77.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9859363 2.91% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23336266 6.88% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14305882 4.22% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7916477 2.34% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1329398 0.39% 94.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18243435 5.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92723381 29.28% 29.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103992421 32.84% 62.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43071500 13.60% 75.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8912974 2.81% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25679598 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13104188 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7581196 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156714 0.37% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20457759 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051654 # Number of instructions committed -system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316679731 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051714 # Number of instructions committed +system.cpu.commit.committedOps 602359921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173611 # Number of memory references committed -system.cpu.commit.loads 148952596 # Number of loads committed +system.cpu.commit.refs 219173635 # Number of memory references committed +system.cpu.commit.loads 148952608 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828603 # Number of branches committed +system.cpu.commit.branches 70828615 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522695 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18243435 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20457759 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1023326216 # The number of ROB reads -system.cpu.rob.rob_writes 1419524916 # The number of ROB writes -system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051603 # Number of Instructions Simulated -system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated -system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads -system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads -system.cpu.int_regfile_writes 676006750 # number of integer regfile writes +system.cpu.rob.rob_reads 978278405 # The number of ROB reads +system.cpu.rob.rob_writes 1375177371 # The number of ROB writes +system.cpu.timesIdled 40898 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850586 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051663 # Number of Instructions Simulated +system.cpu.committedOps 602359870 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051663 # Number of Instructions Simulated +system.cpu.cpi 0.576371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576371 # CPI: Total CPI of All Threads +system.cpu.ipc 1.734995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.734995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210435772 # number of integer regfile reads +system.cpu.int_regfile_writes 664215714 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 943708295 # number of misc regfile reads -system.cpu.misc_regfile_writes 2660 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 657.275674 # Cycle average of tags in use -system.cpu.icache.total_refs 74421550 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905058829 # number of misc regfile reads +system.cpu.misc_regfile_writes 2684 # number of misc regfile writes +system.cpu.icache.replacements 57 # number of replacements +system.cpu.icache.tagsinuse 691.796995 # Cycle average of tags in use +system.cpu.icache.total_refs 67496461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 810 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83328.964198 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits -system.cpu.icache.overall_hits::total 74421550 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses -system.cpu.icache.overall_misses::total 996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 691.796995 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67496461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67496461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67496461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67496461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67496461 # number of overall hits +system.cpu.icache.overall_hits::total 67496461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1093 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1093 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1093 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.icache.overall_misses::total 1093 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37450500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37450500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37450500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37450500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67497554 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67497554 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67497554 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67497554 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34263.952425 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,269 +381,270 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26235000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34294.117647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 282 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 282 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 282 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 282 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 811 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 811 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 811 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 811 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 811 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27589000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27589000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34018.495684 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441200 # number of replacements -system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use -system.cpu.dcache.total_refs 205785268 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits -system.cpu.dcache.overall_hits::total 205782605 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1814234 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1814234 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1814234 # number of overall misses -system.cpu.dcache.overall_misses::total 1814234 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282822000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3282822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27026336525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27026336525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 201000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30309158525 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30309158525 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30309158525 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30309158525 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 138179308 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 138179308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 440437 # number of replacements +system.cpu.dcache.tagsinuse 4094.648264 # Cycle average of tags in use +system.cpu.dcache.total_refs 199949450 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444533 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 449.796641 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88384000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.648264 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132073030 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132073030 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67873619 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67873619 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1457 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1341 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1341 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 199946649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 199946649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 199946649 # number of overall hits +system.cpu.dcache.overall_hits::total 199946649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 249332 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 249332 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543912 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1793244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1793244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1793244 # number of overall misses +system.cpu.dcache.overall_misses::total 1793244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30310392962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30310392962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132322362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132322362 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1329 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1329 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 207596839 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 207596839 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 207596839 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 207596839 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001802 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.006701 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201739893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201739893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201739893 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201739893 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022241 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008889 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13182.513677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17503.310073 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9610962 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2243 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4284.869371 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks -system.cpu.dcache.writebacks::total 395250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1368938 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1368938 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197918 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197918 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247378 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247378 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 445296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 445296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 394903 # number of writebacks +system.cpu.dcache.writebacks::total 394903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51902 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1348710 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1348710 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1348710 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1348710 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197430 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197430 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247104 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247104 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444534 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444534 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444534 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444534 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1628736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1628736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2539917962 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2539917962 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4168653962 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4168653962 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4168653962 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4168653962 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8249.688497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10278.740781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9377.581832 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9377.581832 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72965 # number of replacements -system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421253 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73146 # number of replacements +system.cpu.l2cache.tagsinuse 17814.384262 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421358 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88668 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.752086 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15926.163884 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 35.771827 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1845.364487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.486028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001092 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.056316 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543436 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 165841 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 165871 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 395250 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 395250 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 189027 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 189027 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 354868 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 354898 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 354868 # number of overall hits -system.cpu.l2cache.overall_hits::total 354898 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32073 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32808 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 58355 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 58355 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 90428 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 91163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 90428 # number of overall misses -system.cpu.l2cache.overall_misses::total 91163 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25238000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101025500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1126263500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2003081500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2003081500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25238000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3104107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3129345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25238000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3104107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3129345000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 765 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 197914 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 198679 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 395250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 395250 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247382 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 765 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 445296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 446061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 765 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 445296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 446061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960784 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162055 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235890 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960784 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.203074 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960784 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.203074 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34337.414966 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.734450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 15926.079835 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 36.897354 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1851.407073 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.486025 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001126 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.056500 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543652 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 38 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 165149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 165187 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 394903 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 394903 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 188804 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 188804 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 38 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 353953 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 353991 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 38 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 353953 # number of overall hits +system.cpu.l2cache.overall_hits::total 353991 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33051 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58301 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58301 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 90580 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 91352 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 90580 # number of overall misses +system.cpu.l2cache.overall_misses::total 91352 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26527000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1107986000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1134513000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2000582000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2000582000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26527000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3108568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3135095000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3108568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3135095000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 810 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197428 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 810 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444533 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445343 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 810 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444533 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445343 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.953086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163498 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.953086 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.203764 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.953086 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.203764 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34361.398964 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34325.288888 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.711583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1658000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 329 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5039.513678 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks -system.cpu.l2cache.writebacks::total 58130 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 58152 # number of writebacks +system.cpu.l2cache.writebacks::total 58152 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33041 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91342 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24032500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027503500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24032500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2847590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24032500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2847590000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31130.181347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31097.059097 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.786985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 337dcecf7..709a4d648 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:18:25 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 408816360000 because target called exit() +Exiting @ tick 388554296500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 3c7a99cbd..dd253efff 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,266 +1,266 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408816 # Number of seconds simulated -sim_ticks 408816360000 # Number of ticks simulated -final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.388554 # Number of seconds simulated +sim_ticks 388554296500 # Number of ticks simulated +final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218783 # Simulator instruction rate (inst/s) -host_op_rate 219472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63832966 # Simulator tick rate (ticks/s) -host_mem_usage 214000 # Number of bytes of host memory used -host_seconds 6404.47 # Real time elapsed on the host +host_inst_rate 229375 # Simulator instruction rate (inst/s) +host_op_rate 230098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63606554 # Simulator tick rate (ticks/s) +host_mem_usage 214136 # Number of bytes of host memory used +host_seconds 6108.71 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 6021376 # Number of bytes read from this memory -system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3792448 # Number of bytes written to this memory -system.physmem.num_reads 94084 # Number of read requests responded to by this memory -system.physmem.num_writes 59257 # Number of write requests responded to by this memory +system.physmem.bytes_read 5987456 # Number of bytes read from this memory +system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3788160 # Number of bytes written to this memory +system.physmem.num_reads 93554 # Number of read requests responded to by this memory +system.physmem.num_writes 59190 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 817632721 # number of cpu cycles simulated +system.cpu.numCycles 777108594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103174324 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92051331 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5438120 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 100325127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 99277633 # Number of BTB hits +system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 220 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 175005792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1720391035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103174324 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99278863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 370286255 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31094297 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 246539947 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1680 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 170773896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 991956 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.110623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.012258 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446988679 54.69% 54.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82419688 10.08% 64.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45028734 5.51% 70.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23714407 2.90% 73.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33177153 4.06% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33877408 4.15% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14961867 1.83% 83.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7384305 0.90% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 129722693 15.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126187 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.104112 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 224321388 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 200349407 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 337624010 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 29538890 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 25441239 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1710162106 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 25441239 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255728945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34334751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55175561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334633255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111961183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1694040603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27905496 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 64677715 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3154928 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1413596061 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2861791975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2827818793 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973182 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 168825609 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3228150 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3270628 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 258968806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 454536844 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 185491805 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 260927641 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90896258 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1566773345 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3062819 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1493172729 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111198 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 163655037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 180232812 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 819148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 817274934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.827014 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.412188 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168134039 20.57% 20.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190992211 23.37% 43.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210117454 25.71% 69.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 154482053 18.90% 88.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 65263213 7.99% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16377311 2.00% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7979086 0.98% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3751008 0.46% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178559 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 817274934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154618 7.33% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 176227 8.36% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1421289 67.40% 83.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 356622 16.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 886609078 59.38% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623677 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 430399729 28.82% 88.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173540245 11.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1493172729 # Type of FU issued -system.cpu.iq.rate 1.826214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2108756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3787980335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1724526520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1473498966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17860011 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9206634 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8523998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1486074999 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9206486 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 205830187 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued +system.cpu.iq.rate 1.879873 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 52024000 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213849 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 253991 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18643663 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 681 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45180 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 25441239 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2526766 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 145081 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1668881823 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4258646 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 454536844 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 185491805 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2961001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 253991 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5294422 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 459505 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5753927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1485801812 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427360543 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7370917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99045659 # number of nop insts executed -system.cpu.iew.exec_refs 599531836 # number of memory reference insts executed -system.cpu.iew.exec_branches 90620288 # Number of branches executed -system.cpu.iew.exec_stores 172171293 # Number of stores executed -system.cpu.iew.exec_rate 1.817200 # Inst execution rate -system.cpu.iew.wb_sent 1483493878 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1482022964 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1178273779 # num instructions producing a value -system.cpu.iew.wb_consumers 1228157747 # num instructions consuming a value +system.cpu.iew.exec_nop 94187571 # number of nop insts executed +system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed +system.cpu.iew.exec_branches 89112581 # Number of branches executed +system.cpu.iew.exec_stores 170576694 # Number of stores executed +system.cpu.iew.exec_rate 1.872734 # Inst execution rate +system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154378236 # num instructions producing a value +system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back +system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 791834306 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.881105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.451655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 260467018 32.89% 32.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288028220 36.37% 69.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 45072234 5.69% 74.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56206737 7.10% 82.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24021941 3.03% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8787658 1.11% 86.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30300633 3.83% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10698376 1.35% 91.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68251489 8.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -271,64 +271,64 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68251489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2392297077 # The number of ROB reads -system.cpu.rob.rob_writes 3363039880 # The number of ROB writes -system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2302721032 # The number of ROB reads +system.cpu.rob.rob_writes 3245242057 # The number of ROB writes +system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads -system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes -system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads -system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes -system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads +system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads +system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads +system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes +system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads +system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes +system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 166 # number of replacements -system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use -system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use +system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits -system.cpu.icache.overall_hits::total 170772098 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses -system.cpu.icache.overall_misses::total 1798 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits +system.cpu.icache.overall_hits::total 162821549 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses +system.cpu.icache.overall_misses::total 1976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -337,214 +337,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475353 # number of replacements -system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use -system.cpu.dcache.total_refs 385593109 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits +system.cpu.dcache.replacements 458031 # number of replacements +system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use +system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits -system.cpu.dcache.overall_hits::total 385591790 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits +system.cpu.dcache.overall_hits::total 365777354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses -system.cpu.dcache.overall_misses::total 2725798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses +system.cpu.dcache.overall_misses::total 2675956 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks -system.cpu.dcache.writebacks::total 426654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 267257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks +system.cpu.dcache.writebacks::total 413195 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75859 # number of replacements -system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464590 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75325 # number of replacements +system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 179822 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 426654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 426654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 206842 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 206842 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 386643 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 386664 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 386643 # number of overall hits -system.cpu.l2cache.overall_hits::total 386664 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32384 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33662 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60422 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60422 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 92806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 94084 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 92806 # number of overall misses -system.cpu.l2cache.overall_misses::total 94084 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 43747500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101983500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1145731000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079178500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2079178500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 43747500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3181162000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3224909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 43747500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3181162000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3224909500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 212185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 213484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 426654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 426654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 267264 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 267264 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 479449 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 480748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 479449 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 480748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983834 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.152622 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.226076 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983834 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.193568 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983834 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.193568 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15764.439855 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 99.157433 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1969.677084 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.481093 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003026 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.060110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.544228 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 167881 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 167904 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 413195 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 413195 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 202021 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 202021 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 369902 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 369925 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 369902 # number of overall hits +system.cpu.l2cache.overall_hits::total 369925 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1329 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32167 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33496 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60058 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60058 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1329 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 92225 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 93554 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1329 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 92225 # number of overall misses +system.cpu.l2cache.overall_misses::total 93554 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094618000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1140120500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2066673500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45502500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3161291500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3206794000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45502500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3161291500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3206794000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1352 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 201400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 413195 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 413195 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1352 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 462127 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1352 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 462127 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,44 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks -system.cpu.l2cache.writebacks::total 59257 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 92806 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 94084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 92806 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 94084 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39610000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1004076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1892150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1892150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39610000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2896226500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2935836500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39610000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2896226500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2935836500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.152622 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.226076 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks +system.cpu.l2cache.writebacks::total 59190 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dd2c66002..0aefca8ea 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:08:06 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:30:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -19,9 +19,9 @@ info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 -info: Increasing stack size by one page. Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 586834596000 because target called exit() +Exiting @ tick 637054100000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index db3272b03..b9dc005fb 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,265 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.586835 # Number of seconds simulated -sim_ticks 586834596000 # Number of ticks simulated -final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.637054 # Number of seconds simulated +sim_ticks 637054100000 # Number of ticks simulated +final_tick 637054100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106927 # Simulator instruction rate (inst/s) -host_op_rate 197018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71302744 # Simulator tick rate (ticks/s) -host_mem_usage 220908 # Number of bytes of host memory used -host_seconds 8230.18 # Real time elapsed on the host +host_inst_rate 99624 # Simulator instruction rate (inst/s) +host_op_rate 183562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72118142 # Simulator tick rate (ticks/s) +host_mem_usage 221144 # Number of bytes of host memory used +host_seconds 8833.48 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5879616 # Number of bytes read from this memory -system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3743488 # Number of bytes written to this memory -system.physmem.num_reads 91869 # Number of read requests responded to by this memory -system.physmem.num_writes 58492 # Number of write requests responded to by this memory +system.physmem.bytes_read 5835840 # Number of bytes read from this memory +system.physmem.bytes_inst_read 58688 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3733184 # Number of bytes written to this memory +system.physmem.num_reads 91185 # Number of read requests responded to by this memory +system.physmem.num_writes 58331 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 9160666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 92124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5860074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 15020740 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1173669193 # number of cpu cycles simulated +system.cpu.numCycles 1274108201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits +system.cpu.BPredUnit.lookups 154805091 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154805091 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26670333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76796607 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76433583 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180707581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491843077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154805091 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76433583 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402290589 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93779674 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 624095429 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1350 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186629859 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9332096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.001845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.237422 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878972627 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24230578 1.90% 70.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15474142 1.21% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17847771 1.40% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26734269 2.10% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18266815 1.43% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28459666 2.23% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39787641 3.12% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224272222 17.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121501 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.170892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300115536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537090427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281718880 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88170292 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66950596 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2369584116 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66950596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352574967 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124103280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302559797 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427854412 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2273931919 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293394028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103133099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2267658104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5579907383 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5579899199 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8184 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 649663454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 100 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745849512 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 546580267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222259773 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352635383 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146994929 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027928806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 590 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785553597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119193 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 406267408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 856006289 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1274045731 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.401483 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.311552 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347008054 27.24% 27.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447518543 35.13% 62.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243291159 19.10% 81.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151236902 11.87% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40950901 3.21% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32374953 2.54% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9944821 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1368449 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351949 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1274045731 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 236653 9.21% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2158500 84.00% 93.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 174415 6.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1098315644 61.83% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46809774 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1066762754 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479507335 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192473734 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued -system.cpu.iq.rate 1.513445 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785553597 # Type of FU issued +system.cpu.iq.rate 1.401414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2569568 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001439 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4847841100 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2434377268 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1726804996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2320 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741313206 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208932159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 127538142 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36788 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189688 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34073716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2016 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66950596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 381980 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88146 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027929396 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63814072 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 546580267 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222259773 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48025 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189688 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2136326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24658477 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26794803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767571508 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473890078 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17982089 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed -system.cpu.iew.exec_branches 111935144 # Number of branches executed -system.cpu.iew.exec_stores 193879140 # Number of stores executed -system.cpu.iew.exec_rate 1.501333 # Inst execution rate -system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1327558450 # num instructions producing a value -system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value +system.cpu.iew.exec_refs 665732549 # number of memory reference insts executed +system.cpu.iew.exec_branches 109682584 # Number of branches executed +system.cpu.iew.exec_stores 191842471 # Number of stores executed +system.cpu.iew.exec_rate 1.387301 # Inst execution rate +system.cpu.iew.wb_sent 1728142176 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1726805056 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262100818 # num instructions producing a value +system.cpu.iew.wb_consumers 1868205499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back +system.cpu.iew.wb_rate 1.355305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675569 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 406439731 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26670511 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207095135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.660532 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 343524257 30.53% 30.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 441933791 39.27% 69.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 99674686 8.86% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 136523006 12.13% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31731928 2.82% 93.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26136643 2.32% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22505633 2.00% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8189692 0.73% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15083654 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437349851 36.23% 36.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432546759 35.83% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93488393 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134921626 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35737028 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23235805 1.92% 95.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25789335 2.14% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8868292 0.73% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15158046 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1207095135 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,62 +270,62 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15083654 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15158046 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082456564 # The number of ROB reads -system.cpu.rob.rob_writes 3992764754 # The number of ROB writes -system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3219870802 # The number of ROB reads +system.cpu.rob.rob_writes 4122835024 # The number of ROB writes +system.cpu.timesIdled 1341 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 62470 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads -system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads -system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 905288155 # number of misc regfile reads -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 807.278486 # Cycle average of tags in use -system.cpu.icache.total_refs 136532946 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. +system.cpu.cpi 1.447809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447809 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690699 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690699 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3282350370 # number of integer regfile reads +system.cpu.int_regfile_writes 1699874197 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.misc_regfile_reads 911417902 # number of misc regfile reads +system.cpu.icache.replacements 15 # number of replacements +system.cpu.icache.tagsinuse 828.919506 # Cycle average of tags in use +system.cpu.icache.total_refs 186628505 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 202857.070652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits -system.cpu.icache.overall_hits::total 136532946 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses -system.cpu.icache.overall_misses::total 1228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 828.919506 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186628507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186628507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186628507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186628507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186628507 # number of overall hits +system.cpu.icache.overall_hits::total 186628507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses +system.cpu.icache.overall_misses::total 1352 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45933500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45933500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45933500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45933500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186629859 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186629859 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186629859 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186629859 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33974.482249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,80 +334,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 894 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 894 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 894 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 894 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 894 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 894 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31569000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31569000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31569000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31569000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35312.080537 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 428 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 428 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 428 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 428 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 924 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 924 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 924 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 924 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 924 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32509500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32509500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35183.441558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459037 # number of replacements -system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use -system.cpu.dcache.total_refs 430357004 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 430357004 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 430357004 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 430357004 # number of overall hits -system.cpu.dcache.overall_hits::total 430357004 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 217102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 217102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 249556 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 249556 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 466658 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 466658 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 466658 # number of overall misses -system.cpu.dcache.overall_misses::total 466658 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2192767500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2192767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3219007000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3219007000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5411774500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5411774500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5411774500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5411774500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242637605 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242637605 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445461 # number of replacements +system.cpu.dcache.tagsinuse 4093.514188 # Cycle average of tags in use +system.cpu.dcache.total_refs 452687573 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449557 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1006.963684 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 723787000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.514188 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264747763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264747763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939802 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939802 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452687565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452687565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452687565 # number of overall hits +system.cpu.dcache.overall_hits::total 452687565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 206758 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 206758 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246255 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 453013 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 453013 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 453013 # number of overall misses +system.cpu.dcache.overall_misses::total 453013 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2151695000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2151695000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3209973000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3209973000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5361668000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5361668000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5361668000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5361668000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264954521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264954521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 430823662 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 430823662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 430823662 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 430823662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000895 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001326 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001083 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10100.171809 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12898.936511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 453140578 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453140578 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453140578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453140578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10406.828273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13035.158677 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11835.572048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11835.572048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,116 +416,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks -system.cpu.dcache.writebacks::total 409999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3523 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3523 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3523 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 213614 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 213614 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249521 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249521 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1523998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1523998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2469759000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2469759000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3993757500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3993757500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3993757500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3993757500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 400737 # number of writebacks +system.cpu.dcache.writebacks::total 400737 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3450 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3450 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3450 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3450 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203334 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203334 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246229 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246229 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449563 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449563 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449563 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449563 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1514738500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1514738500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2470762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2470762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3985500500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3985500500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3985500500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3985500500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7449.509182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10034.406995 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8865.276947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8865.276947 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73601 # number of replacements -system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use -system.cpu.l2cache.total_refs 452847 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72913 # number of replacements +system.cpu.l2cache.tagsinuse 17778.272536 # Cycle average of tags in use +system.cpu.l2cache.total_refs 433720 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88532 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.899020 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15990.088083 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 59.987883 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1921.510326 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.487979 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001831 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.058640 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.548449 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 15879.906924 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 60.867967 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1837.497645 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.484616 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001858 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.056076 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.542550 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 181342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 181345 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 409999 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 409999 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 190815 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 190815 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 171422 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 171425 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 400737 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 400737 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187869 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187869 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 372157 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 372160 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 359291 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 359294 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 372157 # number of overall hits -system.cpu.l2cache.overall_hits::total 372160 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 891 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32271 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33162 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 58707 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 58707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 891 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 90978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 91869 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 891 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 90978 # number of overall misses -system.cpu.l2cache.overall_misses::total 91869 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30543500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1099141000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1129684500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2008512000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2008512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30543500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3107653000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3138196500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30543500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3107653000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3138196500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 894 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 213613 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 214507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 409999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 409999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 249522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 249522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 894 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 463135 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 464029 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 894 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 463135 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 464029 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996644 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151072 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235278 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996644 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.196439 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996644 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.196439 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 359291 # number of overall hits +system.cpu.l2cache.overall_hits::total 359294 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 917 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31902 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 32819 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58366 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58366 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 917 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 90268 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 91185 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 917 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 90268 # number of overall misses +system.cpu.l2cache.overall_misses::total 91185 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093292500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1124725500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998037500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1998037500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31433000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3091330000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3122763000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31433000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3091330000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3122763000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203324 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204244 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 400737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 400737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246235 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246235 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449559 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450479 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 449559 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450479 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996739 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156902 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.237034 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996739 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200792 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996739 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200792 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.080698 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34270.343552 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34232.901004 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.080698 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34246.133735 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.080698 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34246.133735 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,44 +538,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58492 # number of writebacks -system.cpu.l2cache.writebacks::total 58492 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 891 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33162 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58707 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91869 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 891 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91869 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27674500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1000499000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028173500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1819949000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1819949000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27674500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2820448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2848122500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27674500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2820448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2848122500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151072 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235278 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 58331 # number of writebacks +system.cpu.l2cache.writebacks::total 58331 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 917 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31902 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32819 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58366 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 917 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 917 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90268 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91185 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28488000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989063500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1017551500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1809374000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1809374000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2798437500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2826925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2798437500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2826925500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156902 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.237034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31066.521265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.181619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.479731 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index bc658a4d7..2b7b5d7d4 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:46:15 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:09:43 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 33080570000 because target called exit() +Exiting @ tick 30872383000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0264f97d4..8b866508b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033081 # Number of seconds simulated -sim_ticks 33080570000 # Number of ticks simulated -final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030872 # Number of seconds simulated +sim_ticks 30872383000 # Number of ticks simulated +final_tick 30872383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183696 # Simulator instruction rate (inst/s) -host_op_rate 185015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67072888 # Simulator tick rate (ticks/s) -host_mem_usage 356156 # Number of bytes of host memory used -host_seconds 493.20 # Real time elapsed on the host -sim_insts 90599331 # Number of instructions simulated -sim_ops 91249885 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997440 # Number of bytes read from this memory -system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory +host_inst_rate 191980 # Simulator instruction rate (inst/s) +host_op_rate 193358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65418525 # Simulator tick rate (ticks/s) +host_mem_usage 356268 # Number of bytes of host memory used +host_seconds 471.92 # Real time elapsed on the host +sim_insts 90599371 # Number of instructions simulated +sim_ops 91249925 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 997760 # Number of bytes read from this memory +system.physmem.bytes_inst_read 44992 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15585 # Number of read requests responded to by this memory +system.physmem.num_reads 15590 # Number of read requests responded to by this memory system.physmem.num_writes 32 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 30151838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 30213748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 32318853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1457354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 66338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 32385190 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 66161141 # number of cpu cycles simulated +system.cpu.numCycles 61744767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits +system.cpu.BPredUnit.lookups 27625975 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21961767 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1057803 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12484908 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12217504 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15373267 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131330347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 32575588 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5466804 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14146452 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14744727 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 369536 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66131345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 63839 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9989 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14937013 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131159638 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27625975 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12281343 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25187217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5166004 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 17501831 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 968 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14529102 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404990 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61714285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.143323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.095410 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33609060 50.82% 50.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6636469 10.04% 60.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4857985 7.35% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2814890 4.26% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1559273 2.36% 86.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2974432 4.50% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6276068 9.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 36568128 59.25% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3588248 5.81% 65.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2263683 3.67% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1635825 2.65% 71.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2193562 3.55% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3029199 4.91% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1536493 2.49% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1081808 1.75% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9817339 15.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66131345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17946387 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12652277 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30529032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4007001 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129091783 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4007001 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19654593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1107803 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 29777338 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3160119 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124853428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1879607 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145685596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 543523130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 543516149 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38256157 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 662188 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 664356 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7619540 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29336358 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117270526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 106162051 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26211100 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 62748267 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66131345 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 61714285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.447422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.124223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17894765 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15294092 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23449441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 997710 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4078277 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4446063 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129128963 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42641 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4078277 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19986704 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1990048 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8372890 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 22331092 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4955274 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124988307 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 34 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 274534 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3719943 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145477524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 543658099 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 543650283 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429503 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38048021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 624217 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 628906 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13326064 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29929002 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5552922 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1387770 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 675384 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118695204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 614278 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105786177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44246 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27759340 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68809466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 59426 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61714285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.714128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.857544 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24322505 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14238731 21.53% 58.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9857797 14.91% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8080871 12.22% 85.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4216459 6.38% 91.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2267136 3.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2478029 3.75% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21784376 35.30% 35.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13573552 21.99% 57.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8691007 14.08% 71.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6574195 10.65% 82.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4926850 7.98% 90.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2861627 4.64% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2480649 4.02% 98.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 367635 0.60% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 454394 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66131345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61714285 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 52363 10.30% 10.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 192835 37.95% 48.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29792 4.51% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 350883 53.15% 57.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279419 42.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74696385 70.36% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26155386 24.64% 95.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74674896 70.59% 70.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10966 0.01% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 250 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 304 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25913310 24.50% 95.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5186446 4.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106162051 # Type of FU issued -system.cpu.iq.rate 1.604598 # Inst issue rate -system.cpu.iq.fu_busy_cnt 508132 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 278993240 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144129636 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102521130 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106669731 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 366279 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105786177 # Type of FU issued +system.cpu.iq.rate 1.713282 # Inst issue rate +system.cpu.iq.fu_busy_cnt 660121 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006240 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 273989825 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 147067719 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102775878 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1722 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 504 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106445710 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 588 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 360974 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6760486 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42468 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7353122 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 910 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 806165 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 206 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4007001 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 117958139 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29336358 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104530427 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1631624 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4078277 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 189303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 32978 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119345782 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 472137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29929002 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5552922 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 610367 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13002 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 910 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 660488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 474136 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1134624 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104503498 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25461820 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282679 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38806 # number of nop insts executed -system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed -system.cpu.iew.exec_branches 21214083 # Number of branches executed -system.cpu.iew.exec_stores 5202833 # Number of stores executed -system.cpu.iew.exec_rate 1.579937 # Inst execution rate -system.cpu.iew.wb_sent 102941812 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102521542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60312663 # num instructions producing a value -system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value +system.cpu.iew.exec_nop 36300 # number of nop insts executed +system.cpu.iew.exec_refs 30578127 # number of memory reference insts executed +system.cpu.iew.exec_branches 21320345 # Number of branches executed +system.cpu.iew.exec_stores 5116307 # Number of stores executed +system.cpu.iew.exec_rate 1.692508 # Inst execution rate +system.cpu.iew.wb_sent 103143555 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102776382 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60808791 # num instructions producing a value +system.cpu.iew.wb_consumers 98854571 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back +system.cpu.iew.wb_rate 1.664536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.615134 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611980 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262534 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 28084875 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554852 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1060689 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 57636009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.583429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.316969 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25053220 43.47% 43.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15762866 27.35% 70.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4731133 8.21% 79.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3928107 6.82% 85.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1673357 2.90% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 949808 1.65% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 650100 1.13% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 189331 0.33% 91.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4698087 8.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611940 # Number of instructions committed -system.cpu.commit.committedOps 91262494 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 57636009 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611980 # Number of instructions committed +system.cpu.commit.committedOps 91262534 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322621 # Number of memory references committed -system.cpu.commit.loads 22575872 # Number of loads committed +system.cpu.commit.refs 27322637 # Number of memory references committed +system.cpu.commit.loads 22575880 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722466 # Number of branches committed +system.cpu.commit.branches 18722474 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533302 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533334 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4698087 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 175546960 # The number of ROB reads -system.cpu.rob.rob_writes 239939856 # The number of ROB writes -system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599331 # Number of Instructions Simulated -system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated -system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads -system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496902735 # number of integer regfile reads -system.cpu.int_regfile_writes 120936098 # number of integer regfile writes -system.cpu.fp_regfile_reads 197 # number of floating regfile reads -system.cpu.fp_regfile_writes 534 # number of floating regfile writes -system.cpu.misc_regfile_reads 184886717 # number of misc regfile reads -system.cpu.misc_regfile_writes 11594 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 611.587679 # Cycle average of tags in use -system.cpu.icache.total_refs 14743811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 172279597 # The number of ROB reads +system.cpu.rob.rob_writes 242795229 # The number of ROB writes +system.cpu.timesIdled 1482 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30482 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599371 # Number of Instructions Simulated +system.cpu.committedOps 91249925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599371 # Number of Instructions Simulated +system.cpu.cpi 0.681514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681514 # CPI: Total CPI of All Threads +system.cpu.ipc 1.467321 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.467321 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496888008 # number of integer regfile reads +system.cpu.int_regfile_writes 120864998 # number of integer regfile writes +system.cpu.fp_regfile_reads 242 # number of floating regfile reads +system.cpu.fp_regfile_writes 665 # number of floating regfile writes +system.cpu.misc_regfile_reads 184727514 # number of misc regfile reads +system.cpu.misc_regfile_writes 11610 # number of misc regfile writes +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 619.944154 # Cycle average of tags in use +system.cpu.icache.total_refs 14528145 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19956.243132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 611.587679 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.298627 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.298627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14743811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14743811 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14743811 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14743811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14743811 # number of overall hits -system.cpu.icache.overall_hits::total 14743811 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 916 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 916 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 916 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 916 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 916 # number of overall misses -system.cpu.icache.overall_misses::total 916 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32376000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32376000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32376000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32376000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14744727 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14744727 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14744727 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14744727 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14744727 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000062 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000062 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000062 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 619.944154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.302707 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.302707 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14528145 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14528145 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14528145 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14528145 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14528145 # number of overall hits +system.cpu.icache.overall_hits::total 14528145 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33256500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33256500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33256500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33256500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33256500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33256500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14529102 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14529102 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14529102 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14529102 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14529102 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14529102 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34750.783699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34750.783699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,214 +382,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 194 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 194 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 194 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 194 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24887000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24887000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24887000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24887000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 728 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 728 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 728 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 728 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 728 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 728 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24950500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24950500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24950500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24950500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24950500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24950500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000050 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34272.664835 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34272.664835 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943456 # number of replacements -system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use -system.cpu.dcache.total_refs 28819271 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3558.808733 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.868850 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 24247440 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24247440 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4559242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4559242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6797 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6797 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28806682 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28806682 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28806682 # number of overall hits -system.cpu.dcache.overall_hits::total 28806682 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 989267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 989267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 175739 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 175739 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1165006 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1165006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1165006 # number of overall misses -system.cpu.dcache.overall_misses::total 1165006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5475545000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4498707428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9974252428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9974252428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9974252428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 25236707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 25236707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943467 # number of replacements +system.cpu.dcache.tagsinuse 3573.833384 # Cycle average of tags in use +system.cpu.dcache.total_refs 28543530 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947563 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.123095 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11199321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3573.833384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.872518 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.872518 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23972222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23972222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4559610 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4559610 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28531832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28531832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28531832 # number of overall hits +system.cpu.dcache.overall_hits::total 28531832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 990009 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 990009 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 175371 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 175371 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1165380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1165380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1165380 # number of overall misses +system.cpu.dcache.overall_misses::total 1165380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5599290000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5599290000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4531637443 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4531637443 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10130927443 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10130927443 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10130927443 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10130927443 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24962231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24962231 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6804 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29971688 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29971688 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29971688 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29971688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039200 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037115 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038870 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5534.951636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29697212 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29697212 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29697212 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29697212 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039660 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037037 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039242 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039242 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5655.797069 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25840.289689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8693.239495 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23215506 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.109154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942907 # number of writebacks -system.cpu.dcache.writebacks::total 942907 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 86240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131213 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131213 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217453 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217453 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903027 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903027 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44526 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 44526 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947553 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947553 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2253076500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081063056 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3334139556 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3334139556 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035782 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009404 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2495.026727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942867 # number of writebacks +system.cpu.dcache.writebacks::total 942867 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86758 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86758 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131059 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131059 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217817 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217817 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217817 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217817 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903251 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903251 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44312 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 44312 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947563 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947563 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947563 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947563 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2324909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2324909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081042568 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081042568 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3405952068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3405952068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3405952068 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3405952068 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031907 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2573.935152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24396.158332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3594.433371 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 744 # number of replacements -system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 755 # number of replacements +system.cpu.l2cache.tagsinuse 9376.851207 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1597250 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15574 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.558752 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.032269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.269680 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006096 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005891 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.281667 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 901393 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 901413 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942907 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942907 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 31267 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 31267 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932660 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932660 # number of overall hits -system.cpu.l2cache.overall_hits::total 932680 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 702 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1057 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14893 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14893 # number of overall misses -system.cpu.l2cache.overall_misses::total 15595 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24071000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 36209000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 498763000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 498763000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24071000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 510901000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 534972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24071000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 510901000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 534972000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 901748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 902470 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942907 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942907 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 45805 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 45805 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947553 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948275 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947553 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948275 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.972299 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.317389 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.972299 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.972299 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 8984.898235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 195.884523 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 196.068450 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.274197 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005978 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005984 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.286159 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 901676 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 901700 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942867 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942867 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 30990 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 30990 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932666 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932690 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932666 # number of overall hits +system.cpu.l2cache.overall_hits::total 932690 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1064 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14897 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15601 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14897 # number of overall misses +system.cpu.l2cache.overall_misses::total 15601 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24129500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12327000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 36456500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499453000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 499453000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24129500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 511780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24129500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 511780000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 902036 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 902764 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942867 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942867 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 45527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 45527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947563 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948291 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947563 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948291 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319305 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015721 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015721 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.857955 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34241.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34357.363968 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.857955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34354.568034 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,50 +601,50 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks system.cpu.l2cache.writebacks::total 32 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1047 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21793500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10767000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32560500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21793500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 484338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21793500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462544500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484338000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000384 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.317389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1053 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14887 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15590 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14887 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15590 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21846000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10912500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32758500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21846000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463281500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485127500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21846000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463281500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485127500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.391181 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31178.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31118.456353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.391181 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31119.869685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 90035090e..f02df016b 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:13:01 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:37:07 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,6 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 70046988500 because target called exit() +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Exiting @ tick 67367177000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1bd6324e3..652133ba6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,265 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070047 # Number of seconds simulated -sim_ticks 70046988500 # Number of ticks simulated -final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067367 # Number of seconds simulated +sim_ticks 67367177000 # Number of ticks simulated +final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120922 # Simulator instruction rate (inst/s) -host_op_rate 212925 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53613076 # Simulator tick rate (ticks/s) -host_mem_usage 355612 # Number of bytes of host memory used -host_seconds 1306.53 # Real time elapsed on the host +host_inst_rate 124120 # Simulator instruction rate (inst/s) +host_op_rate 218555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52925417 # Simulator tick rate (ticks/s) +host_mem_usage 355732 # Number of bytes of host memory used +host_seconds 1272.87 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 3895936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written 892288 # Number of bytes written to this memory -system.physmem.num_reads 60874 # Number of read requests responded to by this memory -system.physmem.num_writes 13942 # Number of write requests responded to by this memory +system.physmem.bytes_read 3905024 # Number of bytes read from this memory +system.physmem.bytes_inst_read 69056 # Number of instructions bytes read from this memory +system.physmem.bytes_written 895552 # Number of bytes written to this memory +system.physmem.num_reads 61016 # Number of read requests responded to by this memory +system.physmem.num_writes 13993 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55618894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 931032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12738421 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 68357314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 57966270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1025069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13293595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 71259866 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 140093978 # number of cpu cycles simulated +system.cpu.numCycles 134734355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37937752 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 37937752 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1331995 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 33815417 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33320649 # Number of BTB hits +system.cpu.BPredUnit.lookups 36117705 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 36117705 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1086223 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25647744 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25539011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29024363 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 203514307 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37937752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33320649 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 63466806 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10233892 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37945043 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 68 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28213885 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 212642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139306492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.579216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.290579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27986454 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 196428178 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36117705 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25539011 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59419496 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8404854 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 39237097 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27269445 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 142050 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 133931620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.578005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.358197 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78286088 56.20% 56.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3759512 2.70% 58.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2809249 2.02% 60.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4511465 3.24% 64.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7046412 5.06% 69.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5071327 3.64% 72.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7671850 5.51% 78.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4389018 3.15% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25761571 18.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77253594 57.68% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2167416 1.62% 59.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2996676 2.24% 61.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4105343 3.07% 64.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8023701 5.99% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5042154 3.76% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2892095 2.16% 76.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1463696 1.09% 77.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29986945 22.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139306492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.270802 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.452698 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 41961886 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28163540 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52299140 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8011732 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8870194 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 354926885 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8870194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48488899 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4721769 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 53110553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24105995 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 349921643 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 105361 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20166032 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 314159745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 860584858 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 860581891 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2967 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 133931620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.268066 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.457892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40456608 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 30121503 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46487725 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9577404 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7288380 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 341192383 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7288380 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45850157 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5075267 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9166 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50344983 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25363667 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 337332641 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24553 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 23217040 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 301814702 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 829797290 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 829794179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3111 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65815553 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 479 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57293063 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112603571 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37556545 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47800126 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8208845 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343290045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 316029105 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 76885 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 64917017 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 92716043 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1890 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139306492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.268588 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.744230 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 53470510 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 56181617 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108142373 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37171875 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46300098 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7898843 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 331653497 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2738 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 311383007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53202508 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 70962751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2292 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 133931620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.324940 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.724540 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32068137 23.02% 23.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17712067 12.71% 35.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24423194 17.53% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 32289069 23.18% 76.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18335734 13.16% 89.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9491103 6.81% 96.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3154604 2.26% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1783304 1.28% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 49280 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 27909124 20.84% 20.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17260254 12.89% 33.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25571257 19.09% 52.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31151034 23.26% 76.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17658757 13.18% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9043417 6.75% 96.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3762327 2.81% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1502538 1.12% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 72912 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139306492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 133931620 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25569 1.30% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1859415 94.86% 96.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 75095 3.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 23628 1.12% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1962682 92.75% 93.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 129707 6.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 180131547 57.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101432595 32.10% 89.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34448103 10.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177172854 56.90% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99705652 32.02% 88.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34472981 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 316029105 # Type of FU issued -system.cpu.iq.rate 2.255836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1960079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006202 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773400844 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 408240794 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 312293905 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 822 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1922 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 317972066 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 407 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52311971 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 311383007 # Type of FU issued +system.cpu.iq.rate 2.311088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2116017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006796 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 758999086 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 384888890 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 308243683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1062 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1674 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 367 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 313467157 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 496 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52573681 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21824183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 143830 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34021 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6116794 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17362985 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 99732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32451 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5732124 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3244 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3822 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3854 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8870194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 981730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88786 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343292381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 39929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112603571 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37556545 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1316 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 42406 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34021 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1234482 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 211725 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1446207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 313835720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100810143 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2193385 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7288380 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 913145 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 89980 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 331656235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 45880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108142373 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37171875 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 43472 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32451 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 613492 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 579011 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1192503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 309419383 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 99171010 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1963624 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134854161 # number of memory reference insts executed -system.cpu.iew.exec_branches 31726163 # Number of branches executed -system.cpu.iew.exec_stores 34044018 # Number of stores executed -system.cpu.iew.exec_rate 2.240180 # Inst execution rate -system.cpu.iew.wb_sent 313006075 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 312294221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231754622 # num instructions producing a value -system.cpu.iew.wb_consumers 317218208 # num instructions consuming a value +system.cpu.iew.exec_refs 133254790 # number of memory reference insts executed +system.cpu.iew.exec_branches 31526578 # Number of branches executed +system.cpu.iew.exec_stores 34083780 # Number of stores executed +system.cpu.iew.exec_rate 2.296514 # Inst execution rate +system.cpu.iew.wb_sent 308790761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 308244050 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227493444 # num instructions producing a value +system.cpu.iew.wb_consumers 314310835 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back +system.cpu.iew.wb_rate 2.287791 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.723785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 53467881 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130436298 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.132785 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.651894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1086244 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126643240 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.196663 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674492 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 49351461 37.84% 37.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24978168 19.15% 56.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17073618 13.09% 70.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12436945 9.53% 79.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3526211 2.70% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3453253 2.65% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2711146 2.08% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1125673 0.86% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15779823 12.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46336828 36.59% 36.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24193827 19.10% 55.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16853923 13.31% 69.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12623187 9.97% 78.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3354078 2.65% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3557907 2.81% 84.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2707686 2.14% 86.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157110 0.91% 87.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15858694 12.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126643240 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988582 # Number of instructions committed system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,63 +270,63 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15779823 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15858694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457952368 # The number of ROB reads -system.cpu.rob.rob_writes 695479183 # The number of ROB writes -system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 442444946 # The number of ROB reads +system.cpu.rob.rob_writes 670617818 # The number of ROB writes +system.cpu.timesIdled 23939 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 802735 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988582 # Number of Instructions Simulated system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated -system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads -system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554395898 # number of integer regfile reads -system.cpu.int_regfile_writes 279799467 # number of integer regfile writes -system.cpu.fp_regfile_reads 352 # number of floating regfile reads -system.cpu.fp_regfile_writes 262 # number of floating regfile writes -system.cpu.misc_regfile_reads 200946158 # number of misc regfile reads -system.cpu.icache.replacements 64 # number of replacements -system.cpu.icache.tagsinuse 822.534021 # Cycle average of tags in use -system.cpu.icache.total_refs 28212585 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks. +system.cpu.cpi 0.852811 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.852811 # CPI: Total CPI of All Threads +system.cpu.ipc 1.172593 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.172593 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549500021 # number of integer regfile reads +system.cpu.int_regfile_writes 275642637 # number of integer regfile writes +system.cpu.fp_regfile_reads 429 # number of floating regfile reads +system.cpu.fp_regfile_writes 242 # number of floating regfile writes +system.cpu.misc_regfile_reads 197910962 # number of misc regfile reads +system.cpu.icache.replacements 103 # number of replacements +system.cpu.icache.tagsinuse 848.450455 # Cycle average of tags in use +system.cpu.icache.total_refs 27268036 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24947.882891 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits -system.cpu.icache.overall_hits::total 28212585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses -system.cpu.icache.overall_misses::total 1300 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 848.450455 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.414282 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.414282 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27268036 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27268036 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27268036 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27268036 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27268036 # number of overall hits +system.cpu.icache.overall_hits::total 27268036 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1409 # number of overall misses +system.cpu.icache.overall_misses::total 1409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50108000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50108000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50108000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50108000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50108000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50108000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27269445 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27269445 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27269445 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27269445 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27269445 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27269445 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35562.810504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1094 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1094 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1094 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1094 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1094 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1094 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38230000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38230000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38230000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38230000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38230000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38230000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34945.155393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072906 # number of replacements -system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use -system.cpu.dcache.total_refs 77489413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits -system.cpu.dcache.overall_hits::total 77489404 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses -system.cpu.dcache.overall_misses::total 2375012 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15268016288 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15268016288 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072116 # number of replacements +system.cpu.dcache.tagsinuse 4072.716490 # Cycle average of tags in use +system.cpu.dcache.total_refs 75611002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076212 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.417766 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22583642000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.716490 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994316 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994316 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 44257159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 44257159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31353834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31353834 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 75610993 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 75610993 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 75610993 # number of overall hits +system.cpu.dcache.overall_hits::total 75610993 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2289224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2289224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85917 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85917 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2375141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2375141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2375141 # number of overall misses +system.cpu.dcache.overall_misses::total 2375141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13801326000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13801326000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502330294 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1502330294 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15303656294 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15303656294 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15303656294 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15303656294 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46546383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46546383 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 77986134 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77986134 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77986134 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77986134 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002733 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.030456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6028.822867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17485.832769 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,121 +417,121 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks -system.cpu.dcache.writebacks::total 1880780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3918 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 298007 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 298007 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077005 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077005 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks +system.cpu.dcache.writebacks::total 1879081 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295092 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295092 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3834 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3834 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 298926 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 298926 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 298926 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 298926 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994132 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994132 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82083 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82083 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076215 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076215 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076215 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076215 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5588966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5588966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158785294 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158785294 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6747751294 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6747751294 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6747751294 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6747751294 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042842 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2802.706140 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14117.238576 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 33246 # number of replacements -system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3764517 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 33385 # number of replacements +system.cpu.l2cache.tagsinuse 18998.818974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3761978 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 61393 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 61.276986 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 12927.949414 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 243.086422 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 5793.952244 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.394530 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007418 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.176817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.578766 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1964440 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1964445 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1880780 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1880780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52709 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52709 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2017149 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2017154 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2017149 # number of overall hits -system.cpu.l2cache.overall_hits::total 2017154 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 30342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31361 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 12949.193091 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 250.074892 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 5799.550991 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.395178 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007632 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.176988 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.579798 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1963577 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1963591 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1879081 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1879081 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52700 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52700 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2016277 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2016291 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2016277 # number of overall hits +system.cpu.l2cache.overall_hits::total 2016291 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1079 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 30422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31501 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29513 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29513 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 59855 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 60874 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 59855 # number of overall misses -system.cpu.l2cache.overall_misses::total 60874 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34913500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1036289000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1071202500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006190000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1006190000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34913500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2042479000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2077392500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34913500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2042479000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2077392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1024 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994782 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995806 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1880780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1880780 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 29515 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29515 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1079 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 59937 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 61016 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1079 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 59937 # number of overall misses +system.cpu.l2cache.overall_misses::total 61016 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36980000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1039210000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1076190000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006243500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1006243500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36980000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2045453500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2082433500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36980000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2045453500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2082433500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1093 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993999 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995092 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1879081 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1879081 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82222 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82222 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077004 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078028 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077004 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078028 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995117 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82215 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82215 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077307 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.987191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015257 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358943 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.028818 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995117 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.028818 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358998 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.028868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.028868 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.474513 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34159.818552 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34092.613925 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,50 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 13942 # number of writebacks -system.cpu.l2cache.writebacks::total 13942 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31361 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 13993 # number of writebacks +system.cpu.l2cache.writebacks::total 13993 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31501 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29513 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 59855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 60874 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 59855 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 60874 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31643000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941211000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 972854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29515 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29515 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 59937 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 61016 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 59937 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 61016 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33519500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 943737500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 977257000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 914925500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 914925500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31643000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915036000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915036000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33519500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1858773500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1892293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33519500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1858773500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1892293000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015257 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358998 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.338276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31021.546907 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.405556 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index f2e7dd662..4e6ce5d2a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:53:02 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:11:33 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 274128411000 because target called exit() +Exiting @ tick 237773144000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index de8607854..12ab99f41 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274128 # Number of seconds simulated -sim_ticks 274128411000 # Number of ticks simulated -final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.237773 # Number of seconds simulated +sim_ticks 237773144000 # Number of ticks simulated +final_tick 237773144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133293 # Simulator instruction rate (inst/s) -host_op_rate 150155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71792865 # Simulator tick rate (ticks/s) -host_mem_usage 228092 # Number of bytes of host memory used -host_seconds 3818.32 # Real time elapsed on the host -sim_insts 508954626 # Number of instructions simulated -sim_ops 573341187 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15240192 # Number of bytes read from this memory -system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10959680 # Number of bytes written to this memory -system.physmem.num_reads 238128 # Number of read requests responded to by this memory -system.physmem.num_writes 171245 # Number of write requests responded to by this memory +host_inst_rate 146125 # Simulator instruction rate (inst/s) +host_op_rate 164611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68266787 # Simulator tick rate (ticks/s) +host_mem_usage 228468 # Number of bytes of host memory used +host_seconds 3483.00 # Real time elapsed on the host +sim_insts 508954831 # Number of instructions simulated +sim_ops 573341392 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15219328 # Number of bytes read from this memory +system.physmem.bytes_inst_read 242816 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10954048 # Number of bytes written to this memory +system.physmem.num_reads 237802 # Number of read requests responded to by this memory +system.physmem.num_writes 171157 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55595084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 837447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 39980095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 95575179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 64007767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1021209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46069324 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 110077091 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 548256823 # number of cpu cycles simulated +system.cpu.numCycles 475546289 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 224897268 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 178814817 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18282790 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 189563731 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156236753 # Number of BTB hits +system.cpu.BPredUnit.lookups 201118526 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 157326791 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13717812 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 115015344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 100642141 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11742995 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2591276 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 154191878 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 995397299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224897268 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167979748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 252064252 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 69921430 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88879876 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27589 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 141619226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4743130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.119468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.816244 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10773560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2444561 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 139270247 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 897566716 # Number of instructions fetch has processed +system.cpu.fetch.Branches 201118526 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 111415701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 200565082 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 55484178 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 92468709 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57772 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 128673930 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3900313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.235169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.071802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 292419737 53.71% 53.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22605861 4.15% 57.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39604588 7.27% 65.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 38612877 7.09% 72.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44079940 8.10% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15590470 2.86% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18445012 3.39% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13511392 2.48% 89.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59601833 10.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 271176826 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 15439241 3.27% 60.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22205632 4.71% 65.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23455924 4.97% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27555464 5.84% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13622297 2.89% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13443686 2.85% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13465943 2.85% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 71365143 15.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.410204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.815568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 173466263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84575198 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 232805016 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4404092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49221141 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33081437 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88923 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1069021878 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219487 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 49221141 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 189418333 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6243189 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 67194010 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 221110320 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11284717 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 983280870 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1088 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2966299 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5203884 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1174814245 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4267939396 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4267936218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3178 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199336 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 502614909 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6158838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6158596 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 63324865 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 196341124 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77971699 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17887364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12637820 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869953710 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7817073 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 735125256 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1650830 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 301557809 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 749773525 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3938874 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 544471710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.350162 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.594792 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.422921 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.887443 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 155306709 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88053503 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 184585127 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4622182 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 39162635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30800384 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 208217 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 978321020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 232355 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 39162635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 168791117 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6653114 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 68132598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 175576746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13413946 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 897480764 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1345 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2815262 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7531261 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 34 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1053491537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898622100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898617765 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4335 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199664 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 381291873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6229815 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6227679 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 73783257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 185038415 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74452080 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16894922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11270431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 807932126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7506931 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 704469962 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1695866 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 239081434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 584885650 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3628691 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 471730156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700371 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241490713 44.35% 44.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 95232425 17.49% 61.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 86360231 15.86% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58954468 10.83% 88.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37235413 6.84% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14676941 2.70% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6419263 1.18% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3351018 0.62% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 751238 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 199497504 42.29% 42.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75863834 16.08% 58.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72319675 15.33% 73.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60290914 12.78% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35341098 7.49% 93.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15480382 3.28% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7623367 1.62% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3919524 0.83% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1393858 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 544471710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 471730156 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133047 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6635057 68.81% 70.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2874860 29.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 439890 4.44% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6794232 68.56% 73.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2675170 27.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 497160573 67.63% 67.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 379945 0.05% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 138 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 170682566 23.22% 90.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 66902031 9.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 475256545 67.46% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 387188 0.05% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 152 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163321629 23.18% 90.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65504445 9.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 735125256 # Type of FU issued -system.cpu.iq.rate 1.340841 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9642964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2026015704 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1179385447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 693708754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 312 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 466 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 704469962 # Type of FU issued +system.cpu.iq.rate 1.481391 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9909292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1892274898 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1054577614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 670769247 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744768062 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 158 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8478103 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 714379082 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9015037 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 69568189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50872 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61447 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20367843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 58265439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44467 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61251 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16848183 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28247 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 21514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49221141 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2690580 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121747 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 887104350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12434546 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 196341124 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77971699 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6076746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46013 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61447 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18517236 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5450893 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 23968129 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 710591708 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 161345852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 24533548 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 39162635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2883414 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 177046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 825140786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8538399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 185038415 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74452080 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6018162 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86541 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61251 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11204470 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7715069 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18919539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 684747739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 156362538 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19722223 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9333567 # number of nop insts executed -system.cpu.iew.exec_refs 226275553 # number of memory reference insts executed -system.cpu.iew.exec_branches 147479421 # Number of branches executed -system.cpu.iew.exec_stores 64929701 # Number of stores executed -system.cpu.iew.exec_rate 1.296093 # Inst execution rate -system.cpu.iew.wb_sent 699249012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 693708770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395011112 # num instructions producing a value -system.cpu.iew.wb_consumers 663436791 # num instructions consuming a value +system.cpu.iew.exec_nop 9701729 # number of nop insts executed +system.cpu.iew.exec_refs 220343005 # number of memory reference insts executed +system.cpu.iew.exec_branches 142216769 # Number of branches executed +system.cpu.iew.exec_stores 63980467 # Number of stores executed +system.cpu.iew.exec_rate 1.439918 # Inst execution rate +system.cpu.iew.wb_sent 675765320 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 670769263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 382570075 # num instructions producing a value +system.cpu.iew.wb_consumers 656640727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back +system.cpu.iew.wb_rate 1.410524 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582617 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 495250570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.160393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.863970 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298715 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685276 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 250472455 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878240 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15860538 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 432567522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.328545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050034 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 259977309 52.49% 52.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116342120 23.49% 75.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44473265 8.98% 84.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 21252753 4.29% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19820819 4.00% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7387112 1.49% 94.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7391590 1.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3775030 0.76% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14830572 2.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 212834429 49.20% 49.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104865988 24.24% 73.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 39942503 9.23% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19801516 4.58% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17404518 4.02% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7252453 1.68% 92.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7574279 1.75% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930965 0.91% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18960871 4.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298510 # Number of instructions committed -system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 432567522 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298715 # Number of instructions committed +system.cpu.commit.committedOps 574685276 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376791 # Number of memory references committed -system.cpu.commit.loads 126772935 # Number of loads committed +system.cpu.commit.refs 184376873 # Number of memory references committed +system.cpu.commit.loads 126772976 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192120 # Number of branches committed +system.cpu.commit.branches 120192161 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701217 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701381 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14830572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18960871 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1367535962 # The number of ROB reads -system.cpu.rob.rob_writes 1823647630 # The number of ROB writes -system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954626 # Number of Instructions Simulated -system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated -system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads -system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads -system.cpu.int_regfile_writes 815117578 # number of integer regfile writes +system.cpu.rob.rob_reads 1238757244 # The number of ROB reads +system.cpu.rob.rob_writes 1689633153 # The number of ROB writes +system.cpu.timesIdled 98384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3816133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954831 # Number of Instructions Simulated +system.cpu.committedOps 573341392 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954831 # Number of Instructions Simulated +system.cpu.cpi 0.934359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934359 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070253 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070253 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3178302017 # number of integer regfile reads +system.cpu.int_regfile_writes 781282618 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1230585750 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463842 # number of misc regfile writes -system.cpu.icache.replacements 12883 # number of replacements -system.cpu.icache.tagsinuse 1062.179544 # Cycle average of tags in use -system.cpu.icache.total_refs 141602716 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1130957302 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463924 # number of misc regfile writes +system.cpu.icache.replacements 15572 # number of replacements +system.cpu.icache.tagsinuse 1101.255140 # Cycle average of tags in use +system.cpu.icache.total_refs 128654642 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17427 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7382.489356 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits -system.cpu.icache.overall_hits::total 141602717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses -system.cpu.icache.overall_misses::total 16509 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1101.255140 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537722 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 128654644 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 128654644 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 128654644 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 128654644 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 128654644 # number of overall hits +system.cpu.icache.overall_hits::total 128654644 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19286 # number of overall misses +system.cpu.icache.overall_misses::total 19286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 260902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 260902000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 260902000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 260902000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 128673930 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 128673930 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 128673930 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 128673930 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13528.051436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,226 +381,226 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1646 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1646 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1646 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14863 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 14863 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 14863 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 14863 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 14863 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 14863 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 154537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17572 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17572 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17572 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17572 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168050000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9563.510130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1212291 # number of replacements -system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use -system.cpu.dcache.total_refs 203801196 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits -system.cpu.dcache.overall_hits::total 199081041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1241922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1467008 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1467008 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 55 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2708930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2708930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2708930 # number of overall misses -system.cpu.dcache.overall_misses::total 2708930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39219667493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39219667493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 147550665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 147550665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1204759 # number of replacements +system.cpu.dcache.tagsinuse 4053.244205 # Cycle average of tags in use +system.cpu.dcache.total_refs 198410390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208855 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.130843 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5569662000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4053.244205 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 141155461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 141155461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52782371 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52782371 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240321 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2240321 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231961 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231961 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 193937832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 193937832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 193937832 # number of overall hits +system.cpu.dcache.overall_hits::total 193937832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1317563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1317563 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1456935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1456935 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 75 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 75 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2774498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2774498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2774498 # number of overall misses +system.cpu.dcache.overall_misses::total 2774498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40364104500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40364104500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 142473024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 142473024 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201789971 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201789971 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201789971 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201789971 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 196712330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 196712330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 196712330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 196712330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026861 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014104 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014104 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11627.182913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17189.894196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9633.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 563000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6119.565217 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1079423 # number of writebacks -system.cpu.dcache.writebacks::total 1079423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365990 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1492410 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1492410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 875932 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 875932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340588 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 340588 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1216520 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1216520 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1216520 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1216520 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6305474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6305474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4364186500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4364186500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10669660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10669660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006279 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7198.588475 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12813.682514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1073285 # number of writebacks +system.cpu.dcache.writebacks::total 1073285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 449185 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 449185 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1116316 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1116316 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 75 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 75 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1565501 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1565501 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1565501 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1565501 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 868378 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 868378 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 340619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1208997 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1208997 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006095 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7188.124296 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12787.529468 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8765.683041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218982 # number of replacements -system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1568375 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.552862 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 204310095000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13543.446906 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 176.680615 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7343.199477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.413313 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005392 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.224097 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.642802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 11134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 749402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 760536 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1079424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1079424 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 96 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 96 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232415 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232415 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 11134 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 981817 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 992951 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 11134 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 981817 # number of overall hits -system.cpu.l2cache.overall_hits::total 992951 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3590 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 126139 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 129729 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 108423 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 108423 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3590 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 234562 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 238152 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3590 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 234562 # number of overall misses -system.cpu.l2cache.overall_misses::total 238152 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4314165500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4437312000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 171500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 171500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713377000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3713377000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 123146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8027542500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8150689000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 123146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8027542500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8150689000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14724 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 875541 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 890265 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1079424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1079424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 340838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 340838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 14724 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1216379 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1231103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14724 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1216379 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1231103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243820 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144070 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.267176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318107 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243820 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.192836 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243820 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.192836 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.646240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34201.678307 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4900 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.978538 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency +system.cpu.l2cache.replacements 218559 # number of replacements +system.cpu.l2cache.tagsinuse 20991.845074 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1557585 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 238962 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.518128 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 174271912000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 13517.987906 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 194.270119 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7279.587049 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.412536 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.005929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.222155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.640620 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13657 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 742223 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 755880 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1073287 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1073287 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 101 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 101 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232585 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232585 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13657 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 974808 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 988465 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13657 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 974808 # number of overall hits +system.cpu.l2cache.overall_hits::total 988465 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3799 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 125573 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 129372 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 108459 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 108459 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3799 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 234032 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 237831 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3799 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 234032 # number of overall misses +system.cpu.l2cache.overall_misses::total 237831 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 130242500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4294239000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4424481500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 130242500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8008070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8138312500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 130242500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8008070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8138312500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 17456 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 867796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 885252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 17456 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1208840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1226296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 17456 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1208840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1226296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.217633 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144703 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.251852 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318021 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.217633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193600 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193600 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34283.364043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.152254 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7058.823529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.796439 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,59 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks -system.cpu.l2cache.writebacks::total 171245 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 171157 # number of writebacks +system.cpu.l2cache.writebacks::total 171157 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 125550 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 129344 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 234009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 237803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 234009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 237803 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3896803000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4014726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7259959000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7377882000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7259959000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7377882000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.251852 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.444386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31037.857427 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31014.705882 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.547009 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index a99eb01f1..447926c85 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:22:59 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:44:57 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +***************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +*********** 58924 words stored in 3784810 bytes @@ -21,10 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -69,4 +80,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 488026375000 because target called exit() +Exiting @ tick 460107924500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index e2e62743e..2a0c6a8f9 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,267 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.488026 # Number of seconds simulated -sim_ticks 488026375000 # Number of ticks simulated -final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460108 # Number of seconds simulated +sim_ticks 460107924500 # Number of ticks simulated +final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101458 # Simulator instruction rate (inst/s) -host_op_rate 187607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59880945 # Simulator tick rate (ticks/s) -host_mem_usage 257144 # Number of bytes of host memory used -host_seconds 8149.94 # Real time elapsed on the host +host_inst_rate 106471 # Simulator instruction rate (inst/s) +host_op_rate 196876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59244607 # Simulator tick rate (ticks/s) +host_mem_usage 257468 # Number of bytes of host memory used +host_seconds 7766.24 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37539712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26338560 # Number of bytes written to this memory -system.physmem.num_reads 586558 # Number of read requests responded to by this memory -system.physmem.num_writes 411540 # Number of write requests responded to by this memory +system.physmem.bytes_read 37486912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26317760 # Number of bytes written to this memory +system.physmem.num_reads 585733 # Number of read requests responded to by this memory +system.physmem.num_writes 411215 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 81474172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 822903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 57199102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 138673273 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 976052751 # number of cpu cycles simulated +system.cpu.numCycles 920215850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits +system.cpu.BPredUnit.lookups 225637815 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225637815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14289291 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160516526 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155855542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed -system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191547382 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1262992642 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225637815 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155855542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392021264 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98465808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 234027765 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 270251 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183405801 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3663632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389419 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 514254997 57.02% 57.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25968939 2.88% 59.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29098594 3.23% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30321386 3.36% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19622378 2.18% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25616419 2.84% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32613002 3.62% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30831455 3.42% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193489002 21.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245201 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372496 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252794809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 186036258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 330006285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49055494 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83923326 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290111824 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 83923326 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289463344 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42750657 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14592 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340217218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 145447035 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240140505 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23735126 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 104491412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2078098051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5261736827 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5260872310 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 864517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 650799024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1282 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 348171673 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540080847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217272434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 215393524 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63213343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2142982647 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62293 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846789239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1603792 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612307626 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 971971651 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901816172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.047856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805282 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 246447632 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 157137359 17.42% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150782303 16.72% 61.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147402025 16.35% 77.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103278327 11.45% 89.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58944184 6.54% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27765839 3.08% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9016087 1.00% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1042416 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901816172 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2649753 16.80% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9923154 62.91% 79.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3201078 20.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2725633 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219452054 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447143707 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177467845 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued -system.cpu.iq.rate 1.965583 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846789239 # Type of FU issued +system.cpu.iq.rate 2.006909 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15773985 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008541 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4612764501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755319104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806286815 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 295108 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 254 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859834785 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2806 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168142861 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 155978687 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 426493 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 273307 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68112538 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6604 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83923326 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7067341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1165909 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143044940 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2779083 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540080847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217272723 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5880 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 921481 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15876 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 273307 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10083404 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5246002 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15329406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818781271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438673892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 28007968 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed -system.cpu.iew.exec_branches 176458351 # Number of branches executed -system.cpu.iew.exec_stores 173832782 # Number of stores executed -system.cpu.iew.exec_rate 1.931402 # Inst execution rate -system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1436941600 # num instructions producing a value -system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value +system.cpu.iew.exec_refs 610552632 # number of memory reference insts executed +system.cpu.iew.exec_branches 170822936 # Number of branches executed +system.cpu.iew.exec_stores 171878740 # Number of stores executed +system.cpu.iew.exec_rate 1.976472 # Inst execution rate +system.cpu.iew.wb_sent 1813583044 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806287069 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379599827 # num instructions producing a value +system.cpu.iew.wb_consumers 2050187147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back +system.cpu.iew.wb_rate 1.962895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614080092 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14315856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 817892846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.869424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327438 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301647537 36.88% 36.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204220955 24.97% 61.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73668560 9.01% 70.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95020529 11.62% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30882746 3.78% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28791442 3.52% 89.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16321974 2.00% 91.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11763768 1.44% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55575335 6.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 817892846 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,62 +270,63 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55575335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3076935822 # The number of ROB reads -system.cpu.rob.rob_writes 4651204201 # The number of ROB writes -system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2905386359 # The number of ROB reads +system.cpu.rob.rob_writes 4370176424 # The number of ROB writes +system.cpu.timesIdled 410524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18399678 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads -system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes -system.cpu.fp_regfile_reads 120 # number of floating regfile reads -system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads -system.cpu.icache.replacements 10111 # number of replacements -system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use -system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks. +system.cpu.cpi 1.112881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898569 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898569 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3086863683 # number of integer regfile reads +system.cpu.int_regfile_writes 1679046201 # number of integer regfile writes +system.cpu.fp_regfile_reads 253 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001956200 # number of misc regfile reads +system.cpu.icache.replacements 10582 # number of replacements +system.cpu.icache.tagsinuse 994.041407 # Cycle average of tags in use +system.cpu.icache.total_refs 183174422 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12099 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15139.633193 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits -system.cpu.icache.overall_hits::total 193665655 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses -system.cpu.icache.overall_misses::total 234749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 994.041407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.485372 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.485372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183181303 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183181303 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183181303 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183181303 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183181303 # number of overall hits +system.cpu.icache.overall_hits::total 183181303 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 224498 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 224498 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 224498 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 224498 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 224498 # number of overall misses +system.cpu.icache.overall_misses::total 224498 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1640944500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1640944500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1640944500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1640944500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183405801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183405801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183405801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183405801 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001224 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001224 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -336,82 +335,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 4 # number of writebacks -system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2040 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2040 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2040 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2040 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2040 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2040 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 232709 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 232709 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 232709 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 232709 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 232709 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 232709 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 952455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 952455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 952455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 952455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 952455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 952455000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4092.901435 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 8 # number of writebacks +system.cpu.icache.writebacks::total 8 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2528 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2528 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2528 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2528 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2528 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2528 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221970 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 221970 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 221970 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 221970 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 221970 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 221970 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915300500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 915300500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915300500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 915300500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915300500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 915300500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001210 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4123.532459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4123.532459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4123.532459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529316 # number of replacements -system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use -system.cpu.dcache.total_refs 427611101 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.520068 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 278887188 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 278887188 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148162157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148162157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 427049345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 427049345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 427049345 # number of overall hits -system.cpu.dcache.overall_hits::total 427049345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2665882 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2665882 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 998044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 998044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3663926 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3663926 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3663926 # number of overall misses -system.cpu.dcache.overall_misses::total 3663926 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39487902000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39487902000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20586128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20586128000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 60074030000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 60074030000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 60074030000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 60074030000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 281553070 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 281553070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2526943 # number of replacements +system.cpu.dcache.tagsinuse 4087.013788 # Cycle average of tags in use +system.cpu.dcache.total_refs 415067708 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531039 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.991036 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2117980000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.013788 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266225231 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266225231 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148171071 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148171071 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414396302 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414396302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414396302 # number of overall hits +system.cpu.dcache.overall_hits::total 414396302 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2666540 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2666540 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 989130 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 989130 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3655670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3655670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3655670 # number of overall misses +system.cpu.dcache.overall_misses::total 3655670 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38988147500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38988147500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20140670500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20140670500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59128818000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59128818000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59128818000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59128818000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 268891771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268891771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418051972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418051972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418051972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418051972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009917 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006631 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008745 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008745 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,126 +419,126 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2229932 # number of writebacks -system.cpu.dcache.writebacks::total 2229932 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902993 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 902993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 909446 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 909446 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 909446 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 909446 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762889 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762889 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks +system.cpu.dcache.writebacks::total 2228961 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 914788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 914788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 979925 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2740882 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2740882 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17128067500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17128067500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32041820000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32041820000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32041820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32041820000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006549 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8469.117928 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.957573 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11690.331798 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11690.331798 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 575774 # number of replacements -system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3195554 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13783.482177 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 57.596580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7780.654120 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.420638 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001758 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.237447 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.659843 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6132 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1428148 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1434280 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2229936 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2229936 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 524029 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 524029 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6132 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1952177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1958309 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6132 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1952177 # number of overall hits -system.cpu.l2cache.overall_hits::total 1958309 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5424 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 334032 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 339456 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 219771 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 219771 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 247125 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 247125 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5424 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 581157 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 586581 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5424 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 581157 # number of overall misses -system.cpu.l2cache.overall_misses::total 586581 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 185788500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11408936500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11594725000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9650000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 9650000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8467808500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8467808500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 185788500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19876745000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20062533500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 185788500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19876745000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20062533500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11556 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762180 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1773736 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2229936 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2229936 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 221060 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 221060 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771154 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771154 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11556 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533334 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544890 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11556 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533334 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544890 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469367 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189556 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994169 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320461 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469367 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229404 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469367 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229404 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 43.909342 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency +system.cpu.l2cache.replacements 574923 # number of replacements +system.cpu.l2cache.tagsinuse 21610.762617 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3193774 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594114 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.375692 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 253017747000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 13759.541955 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 63.216767 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7788.003895 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.419908 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001929 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.237671 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.659508 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6104 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1427022 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1433126 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2228969 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2228969 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1305 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1305 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 524074 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 524074 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6104 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1951096 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1957200 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6104 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1951096 # number of overall hits +system.cpu.l2cache.overall_hits::total 1957200 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5916 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 332816 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 338732 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 208530 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 208530 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 247038 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 247038 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5916 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 579854 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 585770 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5916 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 579854 # number of overall misses +system.cpu.l2cache.overall_misses::total 585770 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 202632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11362833000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11565465500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9919500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 9919500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8463656500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8463656500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 202632500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19826489500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20029122000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 202632500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19826489500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20029122000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12020 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1759838 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1771858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2228969 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2228969 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209835 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 209835 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771112 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771112 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12020 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2530950 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2542970 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12020 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2530950 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2542970 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.492180 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189117 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993781 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320366 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.492180 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229105 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.492180 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229105 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.605815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.486587 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.568695 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.544936 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.605815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34192.209591 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,50 +547,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 411540 # number of writebacks -system.cpu.l2cache.writebacks::total 411540 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334032 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 339456 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 219771 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 219771 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247125 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 247125 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 581157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 586581 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 581157 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 586581 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168319500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10361694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10530013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6813351000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6813351000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7661828500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7661828500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18023522500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18191842000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168319500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18023522500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18191842000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189556 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994169 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320461 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 411215 # number of writebacks +system.cpu.l2cache.writebacks::total 411215 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5916 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332816 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 338732 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208530 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 208530 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247038 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 247038 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5916 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 579854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 585770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5916 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 579854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 585770 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10325106000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10508686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6464792000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6464792000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658792000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658792000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17983898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18167478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17983898000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18167478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993781 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320366 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index b600ef537..371dd4693 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:43 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:34:00 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 139995113500 because target called exit() +Exiting @ tick 141175129500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 58ea20ddf..6b6e927bf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139995 # Number of seconds simulated -sim_ticks 139995113500 # Number of ticks simulated -final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141175 # Number of seconds simulated +sim_ticks 141175129500 # Number of ticks simulated +final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154307 # Simulator instruction rate (inst/s) -host_op_rate 154307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54186341 # Simulator tick rate (ticks/s) -host_mem_usage 215920 # Number of bytes of host memory used -host_seconds 2583.59 # Real time elapsed on the host +host_inst_rate 157275 # Simulator instruction rate (inst/s) +host_op_rate 157275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55694402 # Simulator tick rate (ticks/s) +host_mem_usage 215928 # Number of bytes of host memory used +host_seconds 2534.82 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 469184 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory +system.physmem.bytes_read 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7331 # Number of read requests responded to by this memory +system.physmem.num_reads 7328 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 168277058 # DT system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 168277114 # DTB accesses -system.cpu.itb.fetch_hits 48859849 # ITB hits -system.cpu.itb.fetch_misses 44521 # ITB misses +system.cpu.itb.fetch_hits 49111850 # ITB hits +system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48904370 # ITB accesses +system.cpu.itb.fetch_accesses 49200632 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279990228 # number of cpu cycles simulated +system.cpu.numCycles 282350260 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed. -system.cpu.activity 95.173539 # Percentage of cycles cpu is active +system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. +system.cpu.activity 95.227214 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads -system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits +system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168369236 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168700458 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1970 # number of replacements -system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use -system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1974 # number of replacements +system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use +system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits -system.cpu.icache.overall_hits::total 48855472 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses -system.cpu.icache.overall_misses::total 4376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits +system.cpu.icache.overall_hits::total 49107469 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses +system.cpu.icache.overall_misses::total 4380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -174,34 +174,34 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 479 system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.892021 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73508694 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63830500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63830500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 626731500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 626731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690562000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -238,16 +238,16 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks @@ -268,98 +268,98 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215722500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215722500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215722500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215722500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48615.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.376640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51956.286127 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use -system.cpu.l2cache.total_refs 729 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use +system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.532609 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2905.642885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 623.829454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119019 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 541 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 658 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 541 # number of overall hits +system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 718 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3356 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 725 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4186 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3356 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3356 # number of overall misses +system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175581500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43628000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 219209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164966000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 164966000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175581500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208594000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 384175500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175581500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208594000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 384175500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3897 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7328 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4844 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,42 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index d3938f090..39c5315c7 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:45 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:34:05 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -10,5 +10,5 @@ info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.083333 -Exiting @ tick 89480174500 because target called exit() +OO-style eon Time= 0.066667 +Exiting @ tick 80257421500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e5ff3033e..54f4ab1b0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.089480 # Number of seconds simulated -sim_ticks 89480174500 # Number of ticks simulated -final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080257 # Number of seconds simulated +sim_ticks 80257421500 # Number of ticks simulated +final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246728 # Simulator instruction rate (inst/s) -host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58782597 # Simulator tick rate (ticks/s) -host_mem_usage 216860 # Number of bytes of host memory used -host_seconds 1522.22 # Real time elapsed on the host -sim_insts 375574794 # Number of instructions simulated -sim_ops 375574794 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 475840 # Number of bytes read from this memory -system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory +host_inst_rate 261701 # Simulator instruction rate (inst/s) +host_op_rate 261701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55923550 # Simulator tick rate (ticks/s) +host_mem_usage 217092 # Number of bytes of host memory used +host_seconds 1435.13 # Real time elapsed on the host +sim_insts 375574808 # Number of instructions simulated +sim_ops 375574808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 478528 # Number of bytes read from this memory +system.physmem.bytes_inst_read 222720 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7435 # Number of read requests responded to by this memory +system.physmem.num_reads 7477 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 5962414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2775070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 5962414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105444914 # DTB read hits -system.cpu.dtb.read_misses 94699 # DTB read misses -system.cpu.dtb.read_acv 48617 # DTB read access violations -system.cpu.dtb.read_accesses 105539613 # DTB read accesses -system.cpu.dtb.write_hits 79763652 # DTB write hits -system.cpu.dtb.write_misses 1536 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 79765188 # DTB write accesses -system.cpu.dtb.data_hits 185208566 # DTB hits -system.cpu.dtb.data_misses 96235 # DTB misses -system.cpu.dtb.data_acv 48618 # DTB access violations -system.cpu.dtb.data_accesses 185304801 # DTB accesses -system.cpu.itb.fetch_hits 57904086 # ITB hits -system.cpu.itb.fetch_misses 346 # ITB misses +system.cpu.dtb.read_hits 103368572 # DTB read hits +system.cpu.dtb.read_misses 88956 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 103457528 # DTB read accesses +system.cpu.dtb.write_hits 78975243 # DTB write hits +system.cpu.dtb.write_misses 1664 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78976907 # DTB write accesses +system.cpu.dtb.data_hits 182343815 # DTB hits +system.cpu.dtb.data_misses 90620 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 182434435 # DTB accesses +system.cpu.itb.fetch_hits 52487109 # ITB hits +system.cpu.itb.fetch_misses 461 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 57904432 # ITB accesses +system.cpu.itb.fetch_accesses 52487570 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,315 +53,315 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 178960351 # number of cpu cycles simulated +system.cpu.numCycles 160514845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits +system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued -system.cpu.iq.rate 2.339216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued +system.cpu.iq.rate 2.539806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25662667 # number of nop insts executed -system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed -system.cpu.iew.exec_branches 48120403 # Number of branches executed -system.cpu.iew.exec_stores 79765216 # Number of stores executed -system.cpu.iew.exec_rate 2.290702 # Inst execution rate -system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back -system.cpu.iew.wb_producers 197894075 # num instructions producing a value -system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value +system.cpu.iew.exec_nop 24943165 # number of nop insts executed +system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed +system.cpu.iew.exec_branches 47188511 # Number of branches executed +system.cpu.iew.exec_stores 78976945 # Number of stores executed +system.cpu.iew.exec_rate 2.511684 # Inst execution rate +system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195210305 # num instructions producing a value +system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back +system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.committedInsts 398664569 # Number of instructions committed -system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 398664583 # Number of instructions committed +system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168275214 # Number of memory references committed -system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.refs 168275216 # Number of memory references committed +system.cpu.commit.loads 94754487 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 44587530 # Number of branches committed +system.cpu.commit.branches 44587533 # Number of branches committed system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. +system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 605411260 # The number of ROB reads -system.cpu.rob.rob_writes 926487800 # The number of ROB writes -system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 375574794 # Number of Instructions Simulated -system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads -system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 409675274 # number of integer regfile reads -system.cpu.int_regfile_writes 175727060 # number of integer regfile writes -system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads -system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes +system.cpu.rob.rob_reads 570775521 # The number of ROB reads +system.cpu.rob.rob_writes 888672842 # The number of ROB writes +system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574808 # Number of Instructions Simulated +system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated +system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads +system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402674037 # number of integer regfile reads +system.cpu.int_regfile_writes 172514061 # number of integer regfile writes +system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads +system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2110 # number of replacements -system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use -system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. +system.cpu.icache.replacements 2234 # number of replacements +system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use +system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits -system.cpu.icache.overall_hits::total 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses -system.cpu.icache.overall_misses::total 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits +system.cpu.icache.overall_hits::total 52481453 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses +system.cpu.icache.overall_misses::total 5656 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,202 +370,202 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 793 # number of replacements -system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use -system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. +system.cpu.dcache.replacements 804 # number of replacements +system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use +system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits -system.cpu.dcache.overall_hits::total 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses -system.cpu.dcache.overall_misses::total 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 164752113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 164752113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 164752113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.occ_blocks::cpu.data 3297.800145 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.805127 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.805127 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88308332 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88308332 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501218 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 16 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161809550 # number of overall hits +system.cpu.dcache.overall_hits::total 161809550 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1689 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1689 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19511 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21200 # number of overall misses +system.cpu.dcache.overall_misses::total 21200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56020500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56020500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 567228500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 567228500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 623249000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 623249000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 623249000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 623249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 671 # number of writebacks -system.cpu.dcache.writebacks::total 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16294 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16294 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144837000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 682 # number of writebacks +system.cpu.dcache.writebacks::total 682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 686 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 686 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16309 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16309 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1003 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1003 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4205 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4205 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4205 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4205 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31754500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31754500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144878500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144878500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 10 # number of replacements -system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use -system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 11 # number of replacements +system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use +system.cpu.l2cache.total_refs 903 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4887 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.184776 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 377.670641 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2971.084033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 658.701251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011526 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.090670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.122298 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 600 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 730 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 671 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 600 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 795 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 600 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits -system.cpu.l2cache.overall_hits::total 795 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3437 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 868 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3437 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7435 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3437 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3998 # number of overall misses -system.cpu.l2cache.overall_misses::total 7435 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118151500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30012000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 148163500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108392000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 108392000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 118151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 138404000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 256555500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 118151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 138404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 256555500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5035 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4193 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4193 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.851375 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869739 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979656 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.851375 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.953494 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.851375 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.953494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 374.716771 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3001.811767 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 662.773402 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.091608 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020226 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123270 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 684 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 133 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 75 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 75 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 684 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 208 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 892 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 684 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 208 # number of overall hits +system.cpu.l2cache.overall_hits::total 892 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3480 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 870 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4350 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3127 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3127 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3480 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3997 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7477 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3480 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3997 # number of overall misses +system.cpu.l2cache.overall_misses::total 7477 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 119653000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30088500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 149741500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108341500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108341500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 119653000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 138430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258083000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 119653000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 138430000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258083000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4164 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1003 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4164 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4205 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8369 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4164 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4205 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8369 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.835735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976577 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.835735 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950535 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.835735 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950535 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,42 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 870 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3127 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3127 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3480 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7477 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3480 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7477 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 108421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135761000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98470000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98470000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108421000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 347d30ac0..6a43cd1d6 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:57:28 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:20:40 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.100000 -Exiting @ tick 104492506500 because target called exit() +Exiting @ tick 106128099500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 242cca723..47e84b8b4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.104493 # Number of seconds simulated -sim_ticks 104492506500 # Number of ticks simulated -final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.106128 # Number of seconds simulated +sim_ticks 106128099500 # Number of ticks simulated +final_tick 106128099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158423 # Simulator instruction rate (inst/s) -host_op_rate 202536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60628822 # Simulator tick rate (ticks/s) -host_mem_usage 231676 # Number of bytes of host memory used -host_seconds 1723.48 # Real time elapsed on the host -sim_insts 273038258 # Number of instructions simulated -sim_ops 349066034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 464000 # Number of bytes read from this memory -system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory +host_inst_rate 157297 # Simulator instruction rate (inst/s) +host_op_rate 201096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61140107 # Simulator tick rate (ticks/s) +host_mem_usage 232128 # Number of bytes of host memory used +host_seconds 1735.82 # Real time elapsed on the host +sim_insts 273038358 # Number of instructions simulated +sim_ops 349066134 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 467776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 196608 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7250 # Number of read requests responded to by this memory +system.physmem.num_reads 7309 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 4407655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1852554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4407655 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,105 +63,105 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 208985014 # number of cpu cycles simulated +system.cpu.numCycles 212256200 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits +system.cpu.BPredUnit.lookups 38600701 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20829729 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3463171 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24539034 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19977747 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7676103 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 50709 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 45583571 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349929862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38600701 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27653850 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79742933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11999643 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78327340 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3689 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 43047745 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 991560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 212145839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.131606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.210594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133058921 62.72% 62.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9120644 4.30% 67.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5867847 2.77% 69.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6815573 3.21% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5485208 2.59% 75.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4655113 2.19% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3623686 1.71% 79.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4201022 1.98% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39317825 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 212145839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181859 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.648620 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53244552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73538238 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 73218017 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3725881 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8419151 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7680933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69313 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 439362017 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 203984 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8419151 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 60748190 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1237136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57632287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69638027 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14471048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 424701352 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 42052 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7943055 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 460812549 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2479929544 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1407452570 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072476974 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568759 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 76243790 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3964610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4028744 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48494722 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 109274429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 96208348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3462613 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2507488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 400084611 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3851975 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 382840510 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1563616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 52114616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 153570381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 296314 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 212145839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.804610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.994995 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 84176099 39.68% 39.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 34982222 16.49% 56.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24755932 11.67% 67.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18634598 8.78% 76.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22073169 10.40% 87.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15324157 7.22% 94.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8735583 4.12% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2596961 1.22% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 867118 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 212145839 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2806 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available @@ -181,197 +181,197 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 40388 0.23% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3425 0.02% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 360 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 70580 0.40% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 658 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 165111 0.94% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9772061 55.35% 56.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7595169 43.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 132056726 34.49% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147658 0.56% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6773802 1.77% 36.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8676385 2.27% 39.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3409492 0.89% 39.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1588042 0.41% 40.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21173468 5.53% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175134 1.87% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7113298 1.86% 49.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 104144752 27.20% 76.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88406462 23.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued -system.cpu.iq.rate 1.814089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 382840510 # Type of FU issued +system.cpu.iq.rate 1.803672 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17655604 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046117 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 748490100 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 326330004 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 254739452 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 248555979 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 129729375 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118008670 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 272729101 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 127767013 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7377796 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14625409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 156782 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8434 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13832497 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8419151 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18839 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 495 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 403985333 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2312327 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 109274429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 96208348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3840849 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8434 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3230502 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 526451 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3756953 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 375755558 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102316904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7084952 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47248 # number of nop insts executed -system.cpu.iew.exec_refs 188073317 # number of memory reference insts executed -system.cpu.iew.exec_branches 32214551 # Number of branches executed -system.cpu.iew.exec_stores 85955074 # Number of stores executed -system.cpu.iew.exec_rate 1.784986 # Inst execution rate -system.cpu.iew.wb_sent 370819014 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 369814808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175635069 # num instructions producing a value -system.cpu.iew.wb_consumers 345639533 # num instructions consuming a value +system.cpu.iew.exec_nop 48747 # number of nop insts executed +system.cpu.iew.exec_refs 188828362 # number of memory reference insts executed +system.cpu.iew.exec_branches 32585670 # Number of branches executed +system.cpu.iew.exec_stores 86511458 # Number of stores executed +system.cpu.iew.exec_rate 1.770292 # Inst execution rate +system.cpu.iew.wb_sent 373866507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 372748122 # cumulative count of insts written-back +system.cpu.iew.wb_producers 177468543 # num instructions producing a value +system.cpu.iew.wb_consumers 349211993 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back +system.cpu.iew.wb_rate 1.756124 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508197 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273038870 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349066646 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 201258644 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734418 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.321139 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273038970 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349066746 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 54918764 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555661 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3435880 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 203726689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.713407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.315617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89876372 44.66% 44.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39560210 19.66% 64.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17969648 8.93% 73.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13168483 6.54% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14551255 7.23% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92152533 45.23% 45.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39786932 19.53% 64.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18046593 8.86% 73.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13175994 6.47% 80.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14586259 7.16% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7495826 3.68% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3332635 1.64% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3360666 1.65% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11789251 5.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273038870 # Number of instructions committed -system.cpu.commit.committedOps 349066646 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 203726689 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273038970 # Number of instructions committed +system.cpu.commit.committedOps 349066746 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024831 # Number of memory references committed -system.cpu.commit.loads 94649000 # Number of loads committed +system.cpu.commit.refs 177024871 # Number of memory references committed +system.cpu.commit.loads 94649020 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521879 # Number of branches committed +system.cpu.commit.branches 30521899 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279585929 # Number of committed integer instructions. +system.cpu.commit.int_insts 279586009 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11789251 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 587812621 # The number of ROB reads -system.cpu.rob.rob_writes 803956224 # The number of ROB writes -system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273038258 # Number of Instructions Simulated -system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated -system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads -system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads -system.cpu.int_regfile_writes 235832393 # number of integer regfile writes -system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads -system.cpu.fp_regfile_writes 133870920 # number of floating regfile writes -system.cpu.misc_regfile_reads 1003409978 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes -system.cpu.icache.replacements 14108 # number of replacements -system.cpu.icache.tagsinuse 1842.733120 # Cycle average of tags in use -system.cpu.icache.total_refs 41220872 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 595920425 # The number of ROB reads +system.cpu.rob.rob_writes 816392505 # The number of ROB writes +system.cpu.timesIdled 2445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 110361 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273038358 # Number of Instructions Simulated +system.cpu.committedOps 349066134 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273038358 # Number of Instructions Simulated +system.cpu.cpi 0.777386 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.777386 # CPI: Total CPI of All Threads +system.cpu.ipc 1.286362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.286362 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1793972904 # number of integer regfile reads +system.cpu.int_regfile_writes 239970573 # number of integer regfile writes +system.cpu.fp_regfile_reads 188856116 # number of floating regfile reads +system.cpu.fp_regfile_writes 132824047 # number of floating regfile writes +system.cpu.misc_regfile_reads 1016778379 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422233 # number of misc regfile writes +system.cpu.icache.replacements 14013 # number of replacements +system.cpu.icache.tagsinuse 1856.982815 # Cycle average of tags in use +system.cpu.icache.total_refs 43030970 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15905 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2705.499528 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1842.733120 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.899772 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.899772 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 41220872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41220872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41220872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41220872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41220872 # number of overall hits -system.cpu.icache.overall_hits::total 41220872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16648 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16648 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16648 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16648 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16648 # number of overall misses -system.cpu.icache.overall_misses::total 16648 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201025000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201025000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201025000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201025000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201025000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201025000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41237520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41237520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41237520 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41237520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41237520 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41237520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000404 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000404 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000404 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1856.982815 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906730 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906730 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 43030972 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 43030972 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 43030972 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 43030972 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 43030972 # number of overall hits +system.cpu.icache.overall_hits::total 43030972 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16773 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16773 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16773 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16773 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16773 # number of overall misses +system.cpu.icache.overall_misses::total 16773 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207159500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207159500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207159500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207159500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207159500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207159500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 43047745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 43047745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 43047745 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 43047745 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 43047745 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 43047745 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000390 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000390 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000390 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12350.772074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12350.772074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12350.772074 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,219 +380,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 637 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 637 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 637 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 637 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 637 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 637 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 135953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 135953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 135953500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000388 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8491.256011 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8491.256011 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 843 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 843 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 843 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 843 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 843 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 843 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15930 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15930 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15930 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15930 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15930 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15930 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137878000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 137878000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137878000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 137878000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137878000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 137878000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000370 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000370 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000370 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8655.241682 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8655.241682 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8655.241682 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1410 # number of replacements -system.cpu.dcache.tagsinuse 3098.497902 # Cycle average of tags in use -system.cpu.dcache.total_refs 176602100 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4594 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38441.902481 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1418 # number of replacements +system.cpu.dcache.tagsinuse 3097.151560 # Cycle average of tags in use +system.cpu.dcache.total_refs 176716826 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38450.136205 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3098.497902 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.756469 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.756469 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94546395 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94546395 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82033205 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82033205 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11358 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11358 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11114 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11114 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176579600 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176579600 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176579600 # number of overall hits -system.cpu.dcache.overall_hits::total 176579600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3383 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3383 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3097.151560 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.756141 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.756141 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94660466 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94660466 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82033560 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82033560 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11630 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11630 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11134 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11134 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176694026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176694026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176694026 # number of overall hits +system.cpu.dcache.overall_hits::total 176694026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19134 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19134 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 22872 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22872 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22872 # number of overall misses -system.cpu.dcache.overall_misses::total 22872 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 111712500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 111712500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 649715000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 649715000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 22493 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22493 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22493 # number of overall misses +system.cpu.dcache.overall_misses::total 22493 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 110156500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 110156500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 636387000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 636387000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 761427500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 761427500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 761427500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 761427500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94549778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94549778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 746543500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 746543500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 746543500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 746543500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94663825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94663825 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052694 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11114 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11114 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176602472 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176602472 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176602472 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176602472 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000036 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000176 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33021.726278 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33337.523731 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11632 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11632 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11134 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11134 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 176716519 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176716519 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176716519 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176716519 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000035 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000233 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000172 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32794.432867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33259.485732 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33290.814096 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33190.036900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33190.036900 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 291000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26454.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1034 # number of writebacks -system.cpu.dcache.writebacks::total 1034 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16622 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16622 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18255 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18255 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 18255 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 18255 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1750 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1750 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2867 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2867 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4617 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4617 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4617 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4617 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101787500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155131500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 155131500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155131500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 155131500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 17873 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17873 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17873 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17873 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1755 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1755 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2865 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2865 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53389000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53389000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 155087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155087000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 155087000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30482.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35503.139170 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33600.064977 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30421.082621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35496.684119 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33568.614719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33568.614719 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 57 # number of replacements -system.cpu.l2cache.tagsinuse 3892.486015 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13341 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5352 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.492713 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 63 # number of replacements +system.cpu.l2cache.tagsinuse 3956.949717 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13199 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5419 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.435689 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 378.577721 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2756.979421 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 756.928873 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084136 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.023100 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.118789 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 288 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13258 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1034 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1034 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 19 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 19 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13277 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 13277 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3018 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1461 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4479 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 23 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 23 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2826 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2826 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3018 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4287 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7305 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3018 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4287 # number of overall misses -system.cpu.l2cache.overall_misses::total 7305 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50287500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 153679500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97429500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 97429500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 103392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 147717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 251109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 103392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 147717000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 251109000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17737 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 23 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 23 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2845 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2845 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15988 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20582 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15988 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20582 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188767 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835334 # miss rate for ReadReq accesses +system.cpu.l2cache.occ_blocks::writebacks 381.172265 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2808.385982 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 767.391470 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011632 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.085705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.023419 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.120757 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12826 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 290 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13116 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1039 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1039 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 22 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 22 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12826 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 312 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13138 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12826 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 312 # number of overall hits +system.cpu.l2cache.overall_hits::total 13138 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3080 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1464 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4544 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 24 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 24 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2820 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2820 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3080 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4284 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7364 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3080 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4284 # number of overall misses +system.cpu.l2cache.overall_misses::total 7364 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50316500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 155800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97165500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 97165500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 105484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 147482000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 252966000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 105484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 147482000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 252966000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15906 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17660 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15906 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20502 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15906 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20502 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193638 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834664 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993322 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.933174 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.933174 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34258.449304 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34419.917864 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.114650 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992259 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193638 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.932115 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193638 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932115 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34248.051948 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34369.193989 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34455.851064 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34248.051948 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34426.237162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34248.051948 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34426.237162 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,57 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 47 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 47 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 47 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3008 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1416 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4424 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 23 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 23 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2826 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3008 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4242 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7250 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3008 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4242 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7250 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93473500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44349000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 137822500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 713000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 713000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93473500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 226240500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93473500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 226240500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3072 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1417 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4489 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 24 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 24 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2820 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7309 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4237 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7309 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95429000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44339500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139768500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 744000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 744000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88163500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95429000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132503000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 227932000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95429000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132503000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 227932000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807868 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993322 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992259 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193135 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.127604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31291.107975 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31263.652482 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.127604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31272.834553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index af8dce3f0..df01c27da 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:12:28 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:35:37 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 643030478500 because target called exit() +Exiting @ tick 645508416000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4c98d6289..119153a53 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643030 # Number of seconds simulated -sim_ticks 643030478500 # Number of ticks simulated -final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.645508 # Number of seconds simulated +sim_ticks 645508416000 # Number of ticks simulated +final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198283 # Simulator instruction rate (inst/s) -host_op_rate 198283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69939236 # Simulator tick rate (ticks/s) -host_mem_usage 217424 # Number of bytes of host memory used -host_seconds 9194.13 # Real time elapsed on the host +host_inst_rate 197220 # Simulator instruction rate (inst/s) +host_op_rate 197220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69832178 # Simulator tick rate (ticks/s) +host_mem_usage 217536 # Number of bytes of host memory used +host_seconds 9243.71 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94779264 # Number of bytes read from this memory -system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory +system.physmem.bytes_read 94795136 # Number of bytes read from this memory +system.physmem.bytes_inst_read 192384 # Number of instructions bytes read from this memory system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1480926 # Number of read requests responded to by this memory +system.physmem.num_reads 1481174 # Number of read requests responded to by this memory system.physmem.num_writes 66898 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 147394668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 288733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6658272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 154052940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 146853447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 153486160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 520282071 # DTB read hits -system.cpu.dtb.read_misses 658976 # DTB read misses +system.cpu.dtb.read_hits 526109598 # DTB read hits +system.cpu.dtb.read_misses 625347 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 520941047 # DTB read accesses -system.cpu.dtb.write_hits 283837075 # DTB write hits -system.cpu.dtb.write_misses 53680 # DTB write misses +system.cpu.dtb.read_accesses 526734945 # DTB read accesses +system.cpu.dtb.write_hits 292167921 # DTB write hits +system.cpu.dtb.write_misses 53946 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283890755 # DTB write accesses -system.cpu.dtb.data_hits 804119146 # DTB hits -system.cpu.dtb.data_misses 712656 # DTB misses +system.cpu.dtb.write_accesses 292221867 # DTB write accesses +system.cpu.dtb.data_hits 818277519 # DTB hits +system.cpu.dtb.data_misses 679293 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 804831802 # DTB accesses -system.cpu.itb.fetch_hits 398310361 # ITB hits -system.cpu.itb.fetch_misses 225 # ITB misses +system.cpu.dtb.data_accesses 818956812 # DTB accesses +system.cpu.itb.fetch_hits 402604817 # ITB hits +system.cpu.itb.fetch_misses 847 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398310586 # ITB accesses +system.cpu.itb.fetch_accesses 402605664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286060958 # number of cpu cycles simulated +system.cpu.numCycles 1291016833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402586298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 267183275 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28898117 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 333702913 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 271687015 # Number of BTB hits +system.cpu.BPredUnit.lookups 393573728 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 256530657 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27586844 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324820294 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 261991971 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60998120 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7269 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 415096525 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3352093116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402586298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 332685135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 645195661 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 165271358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89752324 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4176 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398310361 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11197226 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.606736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.132660 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57786471 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 8197 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421176645 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3321335108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393573728 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319778442 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638257970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162812665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 96711303 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8593 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402604817 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9565592 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1290891849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.572900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.136734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 640739381 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57260959 4.45% 54.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45174683 3.51% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 73956325 5.75% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134643957 10.47% 74.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43704830 3.40% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44948525 3.50% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8228368 0.64% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 237278014 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 652633879 50.56% 50.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 59721794 4.63% 55.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43804545 3.39% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72624877 5.63% 64.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127484332 9.88% 74.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46855386 3.63% 77.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41599950 3.22% 80.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7021053 0.54% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239146033 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1285935042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313038 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.606481 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 451176980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71498937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 618592802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8792068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 135874255 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30910962 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3252787569 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 45959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 135874255 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 481268394 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29024257 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25510 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 595950971 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43791655 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3151351284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 355 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750555 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 36590752 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2105050619 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3698513195 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3586317765 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112195430 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1290891849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.304856 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.572651 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 453921580 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79454568 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 612779431 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10011349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134724921 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33550717 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12520 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3227083732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46784 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134724921 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 483920973 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32457268 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25980 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 591448832 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48313875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3136668879 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 405 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 8064 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42516144 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2086288186 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3648925200 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3531562512 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117362688 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 720081549 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 124172087 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 732020123 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 345520616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66357929 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8901879 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642218507 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 75 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2155449111 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17941201 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 818701684 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 780988431 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1285935042 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.676173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.767949 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 701319116 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4353 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 267 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142890931 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 736649308 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 360329563 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68950696 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9282518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2642275746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 205 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2193056773 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17946555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 819111732 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 708893207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1290891849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.698869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804017 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 465245543 36.18% 36.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 229606292 17.86% 54.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 242969112 18.89% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 129449912 10.07% 83.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105111994 8.17% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 71454382 5.56% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 23774402 1.85% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15398679 1.20% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2924726 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470876253 36.48% 36.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 218068463 16.89% 53.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252707156 19.58% 72.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121463164 9.41% 82.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106308054 8.24% 90.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77452334 6.00% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21076392 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17287996 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5652037 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1285935042 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1290891849 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19151 0.06% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21356146 65.69% 65.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11134345 34.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1141130 3.16% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24070571 66.71% 69.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10868345 30.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238361266 57.45% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850917 1.29% 58.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584304865 27.11% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 289453270 13.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1255545244 57.25% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29218260 1.33% 58.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589185884 26.87% 86.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303628594 13.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2155449111 # Type of FU issued -system.cpu.iq.rate 1.676009 # Inst issue rate -system.cpu.iq.fu_busy_cnt 32509642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015083 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5498808910 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3382020905 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990959088 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148475197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78969876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72622847 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2112315501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75640500 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67702370 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2193056773 # Type of FU issued +system.cpu.iq.rate 1.698705 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36080046 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016452 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5576578817 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3377639693 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2021595592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154453179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 83821528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75359015 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2150081181 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79052886 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67169273 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 220950097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 171000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 71734 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134725720 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225579282 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22953 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76359 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 149534667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4434 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 135874255 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3818188 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203306 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3005431260 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2750522 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 732020123 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 345520616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 75 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 71734 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30723187 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 903682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 31626869 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066254472 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 520941220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 89194639 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134724921 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3817892 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 203271 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3000868514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2715875 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 736649308 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 360329563 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 205 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131040 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76359 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27588382 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31906 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27620288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2101232365 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526735105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 91824408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363212678 # number of nop insts executed -system.cpu.iew.exec_refs 804832688 # number of memory reference insts executed -system.cpu.iew.exec_branches 279771397 # Number of branches executed -system.cpu.iew.exec_stores 283891468 # Number of stores executed -system.cpu.iew.exec_rate 1.606654 # Inst execution rate -system.cpu.iew.wb_sent 2065581707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063581935 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1176945723 # num instructions producing a value -system.cpu.iew.wb_consumers 1742555439 # num instructions consuming a value +system.cpu.iew.exec_nop 358592563 # number of nop insts executed +system.cpu.iew.exec_refs 818957488 # number of memory reference insts executed +system.cpu.iew.exec_branches 281208298 # Number of branches executed +system.cpu.iew.exec_stores 292222383 # Number of stores executed +system.cpu.iew.exec_rate 1.627579 # Inst execution rate +system.cpu.iew.wb_sent 2099740429 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2096954607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1185148628 # num instructions producing a value +system.cpu.iew.wb_consumers 1754528061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.604576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.624266 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675480 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 975184756 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150060787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.746853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513737 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27574586 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1156166928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.737628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 543040951 47.22% 47.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 216685952 18.84% 66.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119778809 10.41% 76.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 61132291 5.32% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44136002 3.84% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24968433 2.17% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19265020 1.68% 89.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16055764 1.40% 90.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104997565 9.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 540094894 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227413285 19.67% 66.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119190896 10.31% 76.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56737431 4.91% 81.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50997203 4.41% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24159454 2.09% 88.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18394192 1.59% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15607584 1.35% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103571989 8.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1156166928 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 104997565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103571989 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4028153074 # The number of ROB reads -system.cpu.rob.rob_writes 6113513811 # The number of ROB writes -system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4031130889 # The number of ROB reads +system.cpu.rob.rob_writes 6103072592 # The number of ROB writes +system.cpu.timesIdled 3457 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 124984 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads -system.cpu.ipc 1.417540 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.417540 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2630724063 # number of integer regfile reads -system.cpu.int_regfile_writes 1493026464 # number of integer regfile writes -system.cpu.fp_regfile_reads 77824314 # number of floating regfile reads -system.cpu.fp_regfile_writes 52830391 # number of floating regfile writes +system.cpu.cpi 0.708166 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708166 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412099 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.412099 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2678294251 # number of integer regfile reads +system.cpu.int_regfile_writes 1517633044 # number of integer regfile writes +system.cpu.fp_regfile_reads 81926245 # number of floating regfile reads +system.cpu.fp_regfile_writes 54028832 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8239 # number of replacements -system.cpu.icache.tagsinuse 1650.873085 # Cycle average of tags in use -system.cpu.icache.total_refs 398299261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks. +system.cpu.icache.replacements 8444 # number of replacements +system.cpu.icache.tagsinuse 1673.037469 # Cycle average of tags in use +system.cpu.icache.total_refs 402593289 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10171 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39582.468685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398299261 # number of overall hits -system.cpu.icache.overall_hits::total 398299261 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11100 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11100 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11100 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11100 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11100 # number of overall misses -system.cpu.icache.overall_misses::total 11100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182477500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182477500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182477500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182477500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182477500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398310361 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398310361 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398310361 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398310361 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398310361 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1673.037469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.816913 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.816913 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402593289 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402593289 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402593289 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402593289 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402593289 # number of overall hits +system.cpu.icache.overall_hits::total 402593289 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11528 # number of overall misses +system.cpu.icache.overall_misses::total 11528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 191663000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 191663000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 191663000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 191663000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 191663000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 191663000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402604817 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402604817 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402604817 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402604817 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,262 +371,262 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9947 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9947 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9947 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9947 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 119555000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 119555000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 119555000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 119555000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1356 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1356 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1356 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1356 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1356 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10172 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10172 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10172 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10172 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10172 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10172 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123488000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123488000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123488000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123488000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527592 # number of replacements -system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use -system.cpu.dcache.total_refs 660890207 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.113983 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 450646939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 450646939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210243259 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210243259 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 660890198 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660890198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660890198 # number of overall hits -system.cpu.dcache.overall_hits::total 660890198 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928305 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 551637 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 551637 # number of WriteReq misses +system.cpu.dcache.replacements 1528059 # number of replacements +system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use +system.cpu.dcache.total_refs 667250429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532155 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.497994 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267049000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.059846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999770 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999770 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 457007415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 457007415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210242966 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210242966 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667250381 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667250381 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667250381 # number of overall hits +system.cpu.dcache.overall_hits::total 667250381 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928420 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928420 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 551930 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 551930 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2479942 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2479942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2479942 # number of overall misses -system.cpu.dcache.overall_misses::total 2479942 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71444429000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20878144491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92322573491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92322573491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92322573491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 452575244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 452575244 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2480350 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2480350 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2480350 # number of overall misses +system.cpu.dcache.overall_misses::total 2480350 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71491683500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71491683500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20877271991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20877271991 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 58500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 58500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92368955491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92368955491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92368955491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92368955491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458935835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458935835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 663370140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 663370140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 663370140 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 663370140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004261 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37050.377923 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37847.614448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37227.714798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 50 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 50 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669730731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669730731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6187.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107326 # number of writebacks -system.cpu.dcache.writebacks::total 107326 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 468223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480032 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 480032 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 107245 # number of writebacks +system.cpu.dcache.writebacks::total 107245 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467870 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467870 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 480326 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 948255 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 948255 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 948255 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 948255 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460082 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460082 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 948196 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 948196 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 948196 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 948196 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460550 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460550 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71604 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71604 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49942277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49942277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2493130000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2493130000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1532154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49990545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49990545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492898500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492898500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52435407500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52435407500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003226 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52483443500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002309 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34205.118274 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34817.819985 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34233.761532 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480630 # number of replacements -system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63583 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480784 # number of replacements +system.cpu.l2cache.tagsinuse 31940.343129 # Cycle average of tags in use +system.cpu.l2cache.total_refs 64039 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513473 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.042313 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3059.437870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 43.056925 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28833.418493 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.093367 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.879926 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974607 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7046 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 48913 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 55959 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107326 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107326 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4750 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4750 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7046 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 53663 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 60709 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7046 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 53663 # number of overall hits -system.cpu.l2cache.overall_hits::total 60709 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2901 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411170 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1414071 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66855 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66855 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2901 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1478025 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1480926 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2901 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1478025 # number of overall misses -system.cpu.l2cache.overall_misses::total 1480926 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99564500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48413945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48513510000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2349021500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2349021500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 99564500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50762967000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50862531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 99564500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50762967000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50862531500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460083 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107326 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107326 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9947 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1531688 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1541635 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9947 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531688 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541635 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.291646 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966500 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933664 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.291646 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964965 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.291646 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964965 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 3040.164037 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 45.228004 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28854.951088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.092778 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.880583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.974742 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7166 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 49233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 56399 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107245 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107245 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 53987 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 61153 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 53987 # number of overall hits +system.cpu.l2cache.overall_hits::total 61153 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3006 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1411318 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1414324 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66850 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66850 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3006 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1478168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1481174 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3006 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1478168 # number of overall misses +system.cpu.l2cache.overall_misses::total 1481174 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103160500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48462575000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48565735500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2348759000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2348759000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 103160500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50811334000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50914494500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 103160500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50811334000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50914494500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10172 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460551 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107245 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107245 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10172 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1532155 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1542327 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10172 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1532155 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1542327 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.295517 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966291 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933607 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.295517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964764 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964764 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34318.196939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.522573 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35134.764398 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 40500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3681.818182 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3006 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1414324 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3006 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3006 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481174 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93472000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43751757500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43845229500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147444000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147444000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45899201500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45992673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93472000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45899201500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45992673500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966291 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933607 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31095.143047 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.637348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32123.320868 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 96ddf0fe4..47a0b85a1 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:06:03 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:29:25 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 708285420500 because target called exit() +Exiting @ tick 733277720500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b8fd6e344..ed14e8975 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708285 # Number of seconds simulated -sim_ticks 708285420500 # Number of ticks simulated -final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.733278 # Number of seconds simulated +sim_ticks 733277720500 # Number of ticks simulated +final_tick 733277720500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110657 # Simulator instruction rate (inst/s) -host_op_rate 150700 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56615274 # Simulator tick rate (ticks/s) -host_mem_usage 229476 # Number of bytes of host memory used -host_seconds 12510.50 # Real time elapsed on the host -sim_insts 1384379033 # Number of instructions simulated -sim_ops 1885333786 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94806144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory +host_inst_rate 105807 # Simulator instruction rate (inst/s) +host_op_rate 144094 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56043664 # Simulator tick rate (ticks/s) +host_mem_usage 229440 # Number of bytes of host memory used +host_seconds 13084.04 # Real time elapsed on the host +sim_insts 1384379038 # Number of instructions simulated +sim_ops 1885333791 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 94834048 # Number of bytes read from this memory +system.physmem.bytes_inst_read 211584 # Number of instructions bytes read from this memory system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481346 # Number of read requests responded to by this memory +system.physmem.num_reads 1481782 # Number of read requests responded to by this memory system.physmem.num_writes 66099 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 133853022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 283818 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5972643 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 139825665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 129328964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 288546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5769078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 135098042 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1416570842 # number of cpu cycles simulated +system.cpu.numCycles 1466555442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 502965792 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 388083906 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32892883 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 402994214 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 282903329 # Number of BTB hits +system.cpu.BPredUnit.lookups 521605883 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 398295805 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35472641 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324070281 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 281628461 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59754999 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2839304 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410473974 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2542481038 # Number of instructions fetch has processed -system.cpu.fetch.Branches 502965792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 342658328 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 682850611 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 204993234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 105359667 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2118 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34717 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 384198016 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12176398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1365244569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160393 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 60884201 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2837075 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 442389760 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2602751444 # Number of instructions fetch has processed +system.cpu.fetch.Branches 521605883 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 342512662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 710958340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 222650773 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102112433 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2045 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27281 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 413558926 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12436668 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1437090852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.547593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 682433791 49.99% 49.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48186597 3.53% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108652804 7.96% 61.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 62364195 4.57% 66.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89334703 6.54% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54302238 3.98% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35506449 2.60% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34966658 2.56% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249497134 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 726180548 50.53% 50.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55293209 3.85% 54.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113089207 7.87% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71780914 4.99% 67.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 85098858 5.92% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53585663 3.73% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 33501630 2.33% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33512244 2.33% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 265048579 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1365244569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355059 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.794814 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455297388 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85147033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 647142661 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11145809 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 166511678 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 68705297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11995 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3424572913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23770 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 166511678 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 496865002 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29032521 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3717307 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 615240410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53877651 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3297959575 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4556255 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42355939 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3260022737 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15624313135 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14988978570 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 635334565 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1266869138 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 309495 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 305230 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155871874 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1045378245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 527599628 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35911477 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 45240488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3077735106 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 301755 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2619169948 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18682763 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1192120154 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2900187573 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 90425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1365244569 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.918462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.900067 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1437090852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355667 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.774738 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 490749730 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81942012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 671828843 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10983114 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 181587153 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 78430944 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14399 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3525428920 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31224 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 181587153 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 528591839 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29769579 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3592366 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 643071064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50478851 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3416214159 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4185905 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40940283 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 71 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3334777668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16188662039 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15531956325 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 656705714 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153607 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1341624061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 276669 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 271964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142813939 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1064118913 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 569792794 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 34207890 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 39464438 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3183095569 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 272489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2713070131 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26125821 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1297647909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3029004541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1437090852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.887890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908228 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 480555764 35.20% 35.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182601458 13.37% 48.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216587645 15.86% 64.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179670065 13.16% 77.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 151134600 11.07% 88.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 89532476 6.56% 95.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48791102 3.57% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11536059 0.84% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4835400 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 520966392 36.25% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196978260 13.71% 49.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217896132 15.16% 65.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179000352 12.46% 77.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155500191 10.82% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101390463 7.06% 95.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48751651 3.39% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11023722 0.77% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5583689 0.39% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1365244569 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1437090852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2042243 2.25% 2.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23945 0.03% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55656078 61.41% 63.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32910645 36.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1973852 2.08% 2.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23832 0.03% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56484939 59.46% 61.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36512276 38.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1200490200 45.83% 45.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11234425 0.43% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876478 0.26% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5505051 0.21% 46.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24362738 0.93% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 896045352 34.21% 81.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 473280415 18.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1254030566 46.22% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11231291 0.41% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876617 0.25% 46.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503438 0.20% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 51 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23339517 0.86% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 904708245 33.35% 81.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 506005116 18.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2619169948 # Type of FU issued -system.cpu.iq.rate 1.848951 # Inst issue rate -system.cpu.iq.fu_busy_cnt 90632911 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6584397091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4170852442 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2409395411 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128503048 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 99357739 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57077748 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2644176123 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 65626736 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71999032 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2713070131 # Type of FU issued +system.cpu.iq.rate 1.849961 # Inst issue rate +system.cpu.iq.fu_busy_cnt 94994899 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6850643246 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4377903008 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2485399987 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 133708588 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 103168081 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59868624 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2739540927 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68524103 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73975735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 413989376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1389984 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250602644 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 432730043 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 290479 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1327592 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 292795809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 86 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 77 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 166511678 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16376007 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1473970 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3078105405 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12712072 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1045378245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 527599628 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 290278 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1470963 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1389984 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34573717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8788062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 43361779 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2534356508 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 842568807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 84813440 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 181587153 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16026457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1578003 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3183438661 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7039132 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1064118913 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 569792794 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 261469 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1577202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 221 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1327592 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36771149 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9229244 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46000393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2613620752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 848933154 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99449379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 68544 # number of nop insts executed -system.cpu.iew.exec_refs 1294694969 # number of memory reference insts executed -system.cpu.iew.exec_branches 344427498 # Number of branches executed -system.cpu.iew.exec_stores 452126162 # Number of stores executed -system.cpu.iew.exec_rate 1.789079 # Inst execution rate -system.cpu.iew.wb_sent 2495474043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2466473159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1448284961 # num instructions producing a value -system.cpu.iew.wb_consumers 2707735412 # num instructions consuming a value +system.cpu.iew.exec_nop 70603 # number of nop insts executed +system.cpu.iew.exec_refs 1326104884 # number of memory reference insts executed +system.cpu.iew.exec_branches 359304869 # Number of branches executed +system.cpu.iew.exec_stores 477171730 # Number of stores executed +system.cpu.iew.exec_rate 1.782149 # Inst execution rate +system.cpu.iew.wb_sent 2573682929 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2545268611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1471406784 # num instructions producing a value +system.cpu.iew.wb_consumers 2751379282 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back +system.cpu.iew.wb_rate 1.735542 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534789 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1198732893 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.572781 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256860 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384390054 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885344807 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1298094205 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211331 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 40996327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1255503701 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.501664 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.213150 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 532007294 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 299056293 24.95% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 106726660 8.90% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 77517857 6.47% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53371752 4.45% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23357463 1.95% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17108647 1.43% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9340003 0.78% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 80246924 6.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 576634792 45.93% 45.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 315329042 25.12% 71.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102673368 8.18% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 78981369 6.29% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52937200 4.22% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24029706 1.91% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17032250 1.36% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9453700 0.75% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78432274 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390049 # Number of instructions committed -system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1255503701 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390054 # Number of instructions committed +system.cpu.commit.committedOps 1885344807 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385853 # Number of memory references committed -system.cpu.commit.loads 631388869 # Number of loads committed +system.cpu.commit.refs 908385855 # Number of memory references committed +system.cpu.commit.loads 631388870 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350232 # Number of branches committed +system.cpu.commit.branches 291350233 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705627 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 80246924 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78432274 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4196573290 # The number of ROB reads -system.cpu.rob.rob_writes 6322749564 # The number of ROB writes -system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379033 # Number of Instructions Simulated -system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated -system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads -system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads -system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes -system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads -system.cpu.fp_regfile_writes 50191784 # number of floating regfile writes -system.cpu.misc_regfile_reads 3980708505 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes -system.cpu.icache.replacements 27241 # number of replacements -system.cpu.icache.tagsinuse 1638.335274 # Cycle average of tags in use -system.cpu.icache.total_refs 384162744 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4360492094 # The number of ROB reads +system.cpu.rob.rob_writes 6548474997 # The number of ROB writes +system.cpu.timesIdled 1306597 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29464590 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379038 # Number of Instructions Simulated +system.cpu.committedOps 1885333791 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379038 # Number of Instructions Simulated +system.cpu.cpi 1.059360 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.059360 # CPI: Total CPI of All Threads +system.cpu.ipc 0.943966 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.943966 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12901082944 # number of integer regfile reads +system.cpu.int_regfile_writes 2417885668 # number of integer regfile writes +system.cpu.fp_regfile_reads 70910494 # number of floating regfile reads +system.cpu.fp_regfile_writes 51358984 # number of floating regfile writes +system.cpu.misc_regfile_reads 4077651963 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776278 # number of misc regfile writes +system.cpu.icache.replacements 29135 # number of replacements +system.cpu.icache.tagsinuse 1664.054518 # Cycle average of tags in use +system.cpu.icache.total_refs 413522379 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30834 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13411.246643 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1638.335274 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.799968 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.799968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 384163979 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 384163979 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 384163979 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 384163979 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 384163979 # number of overall hits -system.cpu.icache.overall_hits::total 384163979 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34037 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34037 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34037 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34037 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34037 # number of overall misses -system.cpu.icache.overall_misses::total 34037 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 300707500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 300707500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 300707500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 300707500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 300707500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 300707500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 384198016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 384198016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 384198016 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 384198016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 384198016 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 384198016 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8834.723977 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1664.054518 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.812527 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.812527 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 413522385 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 413522385 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 413522385 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 413522385 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 413522385 # number of overall hits +system.cpu.icache.overall_hits::total 413522385 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36541 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36541 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36541 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36541 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36541 # number of overall misses +system.cpu.icache.overall_misses::total 36541 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 319633500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 319633500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 319633500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 319633500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 319633500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 319633500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 413558926 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 413558926 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 413558926 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 413558926 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 413558926 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 413558926 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8747.256506 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8747.256506 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,221 +382,221 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 775 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 775 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33262 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33262 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33262 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33262 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33262 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33262 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 180621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 180621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 180621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180621500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 180621500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5430.265769 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 817 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 817 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 817 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 817 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 817 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 817 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35724 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 35724 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 35724 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 35724 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 35724 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 35724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191012000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191012000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5346.881648 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5346.881648 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531781 # number of replacements -system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use -system.cpu.dcache.total_refs 1029515809 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.791758 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 753356755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 753356755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276118556 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276118556 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15246 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15246 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11672 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11672 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1029475311 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1029475311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1029475311 # number of overall hits -system.cpu.dcache.overall_hits::total 1029475311 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1938073 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1938073 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 817122 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 817122 # number of WriteReq misses +system.cpu.dcache.replacements 1532451 # number of replacements +system.cpu.dcache.tagsinuse 4094.804050 # Cycle average of tags in use +system.cpu.dcache.total_refs 1033430950 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536547 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.567094 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 312701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.804050 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 757273946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 757273946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276114941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276114941 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 12925 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 12925 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11673 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11673 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1033388887 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1033388887 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1033388887 # number of overall hits +system.cpu.dcache.overall_hits::total 1033388887 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2471866 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2471866 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820737 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820737 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2755195 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2755195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2755195 # number of overall misses -system.cpu.dcache.overall_misses::total 2755195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69347083500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69347083500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28485572000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28485572000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97832655500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97832655500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97832655500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97832655500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 755294828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 755294828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3292603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3292603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3292603 # number of overall misses +system.cpu.dcache.overall_misses::total 3292603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82130752000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82130752000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28580919500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28580919500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 110711671500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 110711671500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 110711671500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 110711671500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 759745812 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 759745812 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15249 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15249 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1032230506 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1032230506 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1032230506 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1032230506 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002566 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000197 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35781.461018 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34860.855539 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11673 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11673 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036681490 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036681490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036681490 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036681490 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003254 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003176 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003176 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33226.215337 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34823.481213 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33624.360878 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20875 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 106815 # number of writebacks -system.cpu.dcache.writebacks::total 106815 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474897 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740078 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 740078 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 106628 # number of writebacks +system.cpu.dcache.writebacks::total 106628 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1008030 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1008030 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743137 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1214975 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1214975 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1214975 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1214975 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463176 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1463176 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1540220 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1540220 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1540220 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1540220 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50021914000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50021914000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483063000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2483063000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52504977000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52504977000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52504977000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52504977000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001937 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34187.216029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32229.154769 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1751167 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1751167 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1751167 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1751167 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1463836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77600 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77600 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541436 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541436 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541436 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541436 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029558000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029558000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2501048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2501048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52530606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52530606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52530606000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52530606000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34177.023929 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.005551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.005551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480005 # number of replacements -system.cpu.l2cache.tagsinuse 31970.457215 # Cycle average of tags in use -system.cpu.l2cache.total_refs 85123 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512725 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.056271 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480282 # number of replacements +system.cpu.l2cache.tagsinuse 31969.351764 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87232 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.057655 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 2966.972548 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 53.821499 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28949.663167 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.090545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001643 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.883474 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.975661 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25776 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 76806 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 106815 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 106815 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 2974.802927 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 59.292981 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28935.255856 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.090784 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.883034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.975627 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27526 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51416 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 78942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 106628 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 106628 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6620 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6620 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25776 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 57650 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 83426 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25776 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 57650 # number of overall hits -system.cpu.l2cache.overall_hits::total 83426 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3145 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1412146 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1415291 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4338 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4338 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66082 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3145 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1478228 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1481373 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3145 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1478228 # number of overall misses -system.cpu.l2cache.overall_misses::total 1481373 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107831000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48448893500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48556724500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252633500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2252633500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107831000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 50701527000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50809358000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107831000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 50701527000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50809358000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 28921 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1463176 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1492097 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 106815 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 106815 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4342 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4342 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72702 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72702 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 28921 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1535878 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1564799 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 28921 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1535878 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1564799 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108745 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965124 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908943 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108745 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.962464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108745 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.962464 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.486486 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34308.700021 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34088.458279 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 6631 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6631 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 58047 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 85573 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27526 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 58047 # number of overall hits +system.cpu.l2cache.overall_hits::total 85573 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3310 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1412420 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1415730 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4885 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4885 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3310 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1478500 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1481810 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3310 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1478500 # number of overall misses +system.cpu.l2cache.overall_misses::total 1481810 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113464000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48455616000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48569080000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252382000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2252382000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113464000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50707998000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50821462000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113464000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50707998000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50821462000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 30836 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1463836 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1494672 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 106628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 106628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4889 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4889 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72711 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72711 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30836 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1536547 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1567383 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30836 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1536547 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1567383 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107342 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964876 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999182 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908803 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107342 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.962222 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107342 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.962222 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34279.154079 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.803925 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.684019 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34279.154079 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.921204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34279.154079 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.921204 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -607,56 +608,56 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3141 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412123 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1415264 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1478205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1481346 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1481346 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97624500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43873380000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43971004500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 134478000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 134478000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3306 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1415702 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1478476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1481782 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3306 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1478476 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1481782 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102729500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43881583500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 151435000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 151435000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102729500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45930125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46032854500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102729500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45930125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46032854500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908803 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107212 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962207 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.653962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.895338 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.930690 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.653962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.857680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 8786d03ec..a906c40f3 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:15:15 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:38:51 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 46914279500 because target called exit() +Exiting @ tick 47232621500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 22fcb32bd..447e68abd 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046914 # Number of seconds simulated -sim_ticks 46914279500 # Number of ticks simulated -final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047233 # Number of seconds simulated +sim_ticks 47232621500 # Number of ticks simulated +final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145791 # Simulator instruction rate (inst/s) -host_op_rate 145791 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77424105 # Simulator tick rate (ticks/s) -host_mem_usage 218104 # Number of bytes of host memory used -host_seconds 605.94 # Real time elapsed on the host +host_inst_rate 142426 # Simulator instruction rate (inst/s) +host_op_rate 142426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76149893 # Simulator tick rate (ticks/s) +host_mem_usage 218108 # Number of bytes of host memory used +host_seconds 620.26 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11164096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7712960 # Number of bytes written to this memory -system.physmem.num_reads 174439 # Number of read requests responded to by this memory -system.physmem.num_writes 120515 # Number of write requests responded to by this memory +system.physmem.bytes_read 11167232 # Number of bytes read from this memory +system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713024 # Number of bytes written to this memory +system.physmem.num_reads 174488 # Number of read requests responded to by this memory +system.physmem.num_writes 120516 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277222 # DTB read hits +system.cpu.dtb.read_hits 20277221 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367370 # DTB read accesses +system.cpu.dtb.read_accesses 20367369 # DTB read accesses system.cpu.dtb.write_hits 14736811 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014033 # DTB hits +system.cpu.dtb.data_hits 35014032 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111433 # DTB accesses -system.cpu.itb.fetch_hits 12380499 # ITB hits -system.cpu.itb.fetch_misses 10576 # ITB misses +system.cpu.dtb.data_accesses 35111432 # DTB accesses +system.cpu.itb.fetch_hits 12477897 # ITB hits +system.cpu.itb.fetch_misses 13095 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12391075 # ITB accesses +system.cpu.itb.fetch_accesses 12490992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93828560 # number of cpu cycles simulated +system.cpu.numCycles 94465244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed. -system.cpu.activity 74.177435 # Percentage of cycles cpu is active +system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. +system.cpu.activity 74.400368 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target. +system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35053135 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064147 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 83610 # number of replacements -system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use -system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85310 # number of replacements +system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use +system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits -system.cpu.icache.overall_hits::total 12263478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses -system.cpu.icache.overall_misses::total 116984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.040544 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921407 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921407 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12359577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12359577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12359577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12359577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12359577 # number of overall hits +system.cpu.icache.overall_hits::total 12359577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118263 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118263 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118263 # number of overall misses +system.cpu.icache.overall_misses::total 118263 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2089534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use +system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits -system.cpu.dcache.overall_hits::total 34126014 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses -system.cpu.dcache.overall_misses::total 764001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits +system.cpu.dcache.overall_hits::total 34125996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses +system.cpu.dcache.overall_misses::total 764019 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks -system.cpu.dcache.writebacks::total 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks +system.cpu.dcache.writebacks::total 161215 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -269,98 +269,98 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254482000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148060 # number of replacements -system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 148111 # number of replacements +system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use +system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 15657.217235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.269041 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1640.204088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477820 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.041939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050055 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.569815 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 77946 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 26999 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 104945 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161215 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits -system.cpu.l2cache.overall_hits::total 115564 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 77946 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39269 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 117215 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 77946 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39269 # number of overall hits +system.cpu.l2cache.overall_hits::total 117215 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9410 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 42988 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses -system.cpu.l2cache.overall_misses::total 174439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 9410 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165078 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174488 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9410 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165078 # number of overall misses +system.cpu.l2cache.overall_misses::total 174488 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 492013000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752923000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2244936000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854378000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6854378000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492013000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8607301000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9099314000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492013000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8607301000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9099314000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 87356 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 147933 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161215 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161215 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,44 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks -system.cpu.l2cache.writebacks::total 120515 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks +system.cpu.l2cache.writebacks::total 120516 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9410 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42988 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 8276bb368..4f0567259 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:19:29 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:42:57 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21259532000 because target called exit() +Exiting @ tick 21302882000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index a0babad48..3e4315992 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021260 # Number of seconds simulated -sim_ticks 21259532000 # Number of ticks simulated -final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021303 # Number of seconds simulated +sim_ticks 21302882000 # Number of ticks simulated +final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240617 # Simulator instruction rate (inst/s) -host_op_rate 240617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64270421 # Simulator tick rate (ticks/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 330.78 # Real time elapsed on the host +host_inst_rate 238426 # Simulator instruction rate (inst/s) +host_op_rate 238426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63815052 # Simulator tick rate (ticks/s) +host_mem_usage 219800 # Number of bytes of host memory used +host_seconds 333.82 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11229312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713344 # Number of bytes written to this memory -system.physmem.num_reads 175458 # Number of read requests responded to by this memory -system.physmem.num_writes 120521 # Number of write requests responded to by this memory +system.physmem.bytes_read 11250368 # Number of bytes read from this memory +system.physmem.bytes_inst_read 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713792 # Number of bytes written to this memory +system.physmem.num_reads 175787 # Number of read requests responded to by this memory +system.physmem.num_writes 120528 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 528114834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 30917131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 362100865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 890215699 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22309038 # DTB read hits -system.cpu.dtb.read_misses 216523 # DTB read misses -system.cpu.dtb.read_acv 41 # DTB read access violations -system.cpu.dtb.read_accesses 22525561 # DTB read accesses -system.cpu.dtb.write_hits 15629688 # DTB write hits -system.cpu.dtb.write_misses 39366 # DTB write misses -system.cpu.dtb.write_acv 9 # DTB write access violations -system.cpu.dtb.write_accesses 15669054 # DTB write accesses -system.cpu.dtb.data_hits 37938726 # DTB hits -system.cpu.dtb.data_misses 255889 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38194615 # DTB accesses -system.cpu.itb.fetch_hits 13877051 # ITB hits -system.cpu.itb.fetch_misses 28133 # ITB misses +system.cpu.dtb.read_hits 22551743 # DTB read hits +system.cpu.dtb.read_misses 221888 # DTB read misses +system.cpu.dtb.read_acv 31 # DTB read access violations +system.cpu.dtb.read_accesses 22773631 # DTB read accesses +system.cpu.dtb.write_hits 15815895 # DTB write hits +system.cpu.dtb.write_misses 41880 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 15857775 # DTB write accesses +system.cpu.dtb.data_hits 38367638 # DTB hits +system.cpu.dtb.data_misses 263768 # DTB misses +system.cpu.dtb.data_acv 34 # DTB access violations +system.cpu.dtb.data_accesses 38631406 # DTB accesses +system.cpu.itb.fetch_hits 14242802 # ITB hits +system.cpu.itb.fetch_misses 40881 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13905184 # ITB accesses +system.cpu.itb.fetch_accesses 14283683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42519067 # number of cpu cycles simulated +system.cpu.numCycles 42605767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16615602 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10784809 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 464390 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14543138 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8570194 # Number of BTB hits +system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1986002 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14905140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105779121 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615602 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10556196 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20616414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026173 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4867777 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 282637 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13877051 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 219292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.511107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.106328 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21508089 51.06% 51.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2128231 5.05% 56.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1654689 3.93% 60.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2031982 4.82% 64.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3913911 9.29% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1970832 4.68% 78.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 733979 1.74% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1130432 2.68% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7052358 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.390780 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.487804 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15964361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4443062 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19692488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 675645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3728678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99733 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103933078 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 280329 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16452599 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2364451 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19835916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2038559 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102562493 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 192 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2676 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1925408 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61709040 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123636906 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123159992 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 476914 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9162159 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5460 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4149992 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23138107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16243401 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1017520 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 376699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90712605 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5415 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88293060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101013 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10834162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4923026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 832 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42124503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.096002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.077334 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13300851 31.58% 31.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7326403 17.39% 48.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5817137 13.81% 62.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4863957 11.55% 74.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4880067 11.58% 85.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2467879 5.86% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1850711 4.39% 96.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1163401 2.76% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 454097 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42124503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 99927 5.41% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 762620 41.31% 46.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 983690 53.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49334128 55.88% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44107 0.05% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 126794 0.14% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 90 0.00% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 127284 0.14% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22763265 25.78% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15858425 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88293060 # Type of FU issued -system.cpu.iq.rate 2.076552 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1846238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020910 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220034609 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101108296 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86316001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 623265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 459484 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 302223 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89827554 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 311744 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1421900 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued +system.cpu.iq.rate 2.095998 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2861469 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1630024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1395228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 60292 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100209488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 330917 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23138107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16243401 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5415 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 717 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 305754 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 116766 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 422520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87324044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22528336 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 969016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9491468 # number of nop insts executed -system.cpu.iew.exec_refs 38197877 # number of memory reference insts executed -system.cpu.iew.exec_branches 15069707 # Number of branches executed -system.cpu.iew.exec_stores 15669541 # Number of stores executed -system.cpu.iew.exec_rate 2.053762 # Inst execution rate -system.cpu.iew.wb_sent 87015038 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86618224 # cumulative count of insts written-back -system.cpu.iew.wb_producers 32981280 # num instructions producing a value -system.cpu.iew.wb_consumers 42978824 # num instructions consuming a value +system.cpu.iew.exec_nop 9561759 # number of nop insts executed +system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172966 # Number of branches executed +system.cpu.iew.exec_stores 15858326 # Number of stores executed +system.cpu.iew.exec_rate 2.071748 # Inst execution rate +system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33493281 # num instructions producing a value +system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.037162 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back +system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40775556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.166511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804904 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17645835 43.28% 43.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7080138 17.36% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3592753 8.81% 69.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2169640 5.32% 74.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2013725 4.94% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1230420 3.02% 82.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1128970 2.77% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727312 1.78% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5186763 12.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5186763 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131447177 # The number of ROB reads -system.cpu.rob.rob_writes 195703293 # The number of ROB writes -system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132302765 # The number of ROB reads +system.cpu.rob.rob_writes 197976180 # The number of ROB writes +system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads -system.cpu.ipc 1.871907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.871907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115518864 # number of integer regfile reads -system.cpu.int_regfile_writes 57354047 # number of integer regfile writes -system.cpu.fp_regfile_reads 252314 # number of floating regfile reads -system.cpu.fp_regfile_writes 251108 # number of floating regfile writes -system.cpu.misc_regfile_reads 38108 # number of misc regfile reads +system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116852046 # number of integer regfile reads +system.cpu.int_regfile_writes 57987678 # number of integer regfile writes +system.cpu.fp_regfile_reads 254259 # number of floating regfile reads +system.cpu.fp_regfile_writes 241396 # number of floating regfile writes +system.cpu.misc_regfile_reads 38319 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 88378 # number of replacements -system.cpu.icache.tagsinuse 1927.638696 # Cycle average of tags in use -system.cpu.icache.total_refs 13782143 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1927.638696 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13782143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13782143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13782143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13782143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13782143 # number of overall hits -system.cpu.icache.overall_hits::total 13782143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 94908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 94908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 94908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 94908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 94908 # number of overall misses -system.cpu.icache.overall_misses::total 94908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 914028500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 914028500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 914028500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 914028500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13877051 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13877051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13877051 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13877051 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006839 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006839 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006839 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9630.679184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency +system.cpu.icache.replacements 94879 # number of replacements +system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use +system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits +system.cpu.icache.overall_hits::total 14141018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 101784 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 101784 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 101784 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 101784 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 101784 # number of overall misses +system.cpu.icache.overall_misses::total 101784 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 964559500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 964559500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 964559500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 964559500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 964559500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 964559500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14242802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14242802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14242802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14242802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,248 +371,248 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4481 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4481 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4481 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 90427 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 90427 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 90427 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 90427 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 90427 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 90427 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 542589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 542589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 542589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 542589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 542589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 542589500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006516 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6000.304113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6000.304113 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4856 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4856 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4856 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4856 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4856 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4856 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 96928 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 96928 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 96928 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 96928 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 96928 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 96928 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 566036000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 566036000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 566036000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 566036000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201340 # number of replacements -system.cpu.dcache.tagsinuse 4076.154176 # Cycle average of tags in use -system.cpu.dcache.total_refs 34207250 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205436 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.510495 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 157430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.154176 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995155 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995155 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20628725 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20628725 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13578476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13578476 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34207201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34207201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34207201 # number of overall hits -system.cpu.dcache.overall_hits::total 34207201 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 257071 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 257071 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1034901 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1034901 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1291972 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1291972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1291972 # number of overall misses -system.cpu.dcache.overall_misses::total 1291972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8273144500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8273144500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33900181500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33900181500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42173326000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42173326000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42173326000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42173326000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20885796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20885796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201683 # number of replacements +system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use +system.cpu.dcache.total_refs 34409774 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205779 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.217131 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 158059000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.258401 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995180 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995180 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20831540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20831540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13578164 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13578164 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits +system.cpu.dcache.overall_hits::total 34409704 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1292995 # number of overall misses +system.cpu.dcache.overall_misses::total 1292995 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8279025500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8279025500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34022399498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34022399498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42301424998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42301424998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42301424998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42301424998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21089322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21089322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 49 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35499173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35499173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35499173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35499173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012308 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070819 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036394 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036394 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32182.332896 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32756.931822 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.600614 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 53500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2675 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35702699 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35702699 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32116.383223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161613 # number of writebacks -system.cpu.dcache.writebacks::total 161613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195029 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 195029 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1086536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1086536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1086536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1086536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62042 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62042 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205436 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205436 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205436 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205436 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1278233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1278233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733826000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733826000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6012059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6012059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6012059000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6012059000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002971 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20602.704619 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33012.720197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks +system.cpu.dcache.writebacks::total 161705 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195431 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 195431 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891785 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891785 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1087216 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1087216 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1087216 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1087216 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62351 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62351 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143428 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143428 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205779 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205779 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205779 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205779 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1281958000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1281958000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4735775500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4735775500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6017733500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 149119 # number of replacements -system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 136861 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149461 # number of replacements +system.cpu.l2cache.tagsinuse 18973.137542 # Cycle average of tags in use +system.cpu.l2cache.total_refs 143447 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174828 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.820504 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15723.499493 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1497.146716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1703.151052 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.479843 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.045689 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051976 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.577508 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 80385 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 28006 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 108391 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161613 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161613 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12014 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12014 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 80385 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 40020 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 120405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 80385 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 40020 # number of overall hits -system.cpu.l2cache.overall_hits::total 120405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 10042 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 34008 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 44050 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131408 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131408 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10042 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 165416 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 175458 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10042 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 165416 # number of overall misses -system.cpu.l2cache.overall_misses::total 175458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 344615000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1171447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1516062500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525488500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4525488500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 344615000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5696936000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6041551000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 344615000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5696936000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6041551000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 90427 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62014 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 152441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 161613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 161613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143422 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143422 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 90427 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 295863 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 90427 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 295863 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111051 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.548392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916233 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111051 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.805195 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111051 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.805195 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.367058 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34446.233239 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.455041 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 15709.127164 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1544.894785 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1719.115593 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.479405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.047146 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.052463 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.579014 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 86637 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 28247 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 114884 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161705 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161705 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12036 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12036 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86637 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 40283 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 126920 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86637 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 40283 # number of overall hits +system.cpu.l2cache.overall_hits::total 126920 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 10291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 34099 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 44390 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131397 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131397 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165496 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 175787 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10291 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165496 # number of overall misses +system.cpu.l2cache.overall_misses::total 175787 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 353191500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1174547500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1527739000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525137500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4525137500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 353191500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5699685000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6052876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 353191500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5699685000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6052876500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 96928 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62346 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 159274 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161705 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161705 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 96928 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 302707 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 96928 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 302707 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.106172 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.546932 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916086 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106172 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.804241 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106172 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.804241 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.425615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34445.218335 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.666788 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120521 # number of writebacks -system.cpu.l2cache.writebacks::total 120521 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10042 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34008 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 44050 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131408 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131408 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10042 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 175458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10042 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 175458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 312130500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1055457000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1367587500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118168500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118168500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 312130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5173625500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5485756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 312130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5173625500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5485756000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.548392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916233 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.503485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.550459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31338.795964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks +system.cpu.l2cache.writebacks::total 120528 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34099 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 44390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131397 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131397 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165496 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 175787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165496 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 175787 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 319907000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1058267500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1378174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 319907000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176426000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5496333000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 319907000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index e2d26e372..2abcbcd2a 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:25:27 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:47:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 31189496500 because target called exit() +Exiting @ tick 30746529500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 228286404..a9b05e877 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.031189 # Number of seconds simulated -sim_ticks 31189496500 # Number of ticks simulated -final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030747 # Number of seconds simulated +sim_ticks 30746529500 # Number of ticks simulated +final_tick 30746529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144507 # Simulator instruction rate (inst/s) -host_op_rate 205068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63556485 # Simulator tick rate (ticks/s) -host_mem_usage 231932 # Number of bytes of host memory used -host_seconds 490.74 # Real time elapsed on the host -sim_insts 70914922 # Number of instructions simulated -sim_ops 100634170 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8651712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661248 # Number of bytes written to this memory -system.physmem.num_reads 135183 # Number of read requests responded to by this memory -system.physmem.num_writes 88457 # Number of write requests responded to by this memory +host_inst_rate 146131 # Simulator instruction rate (inst/s) +host_op_rate 207370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63356016 # Simulator tick rate (ticks/s) +host_mem_usage 232084 # Number of bytes of host memory used +host_seconds 485.30 # Real time elapsed on the host +sim_insts 70917047 # Number of instructions simulated +sim_ops 100636295 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 8680064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 363776 # Number of instructions bytes read from this memory +system.physmem.bytes_written 5661120 # Number of bytes written to this memory +system.physmem.num_reads 135626 # Number of read requests responded to by this memory +system.physmem.num_writes 88455 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 277391846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11224291 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 181511362 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 458903208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282310366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 11831449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 184122244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 466432610 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 62378994 # number of cpu cycles simulated +system.cpu.numCycles 61493060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17633191 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11526968 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 822695 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15043788 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9743985 # Number of BTB hits +system.cpu.BPredUnit.lookups 17207683 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11124675 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 739996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12413226 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8258713 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1887457 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 176874 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12969342 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88531281 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17633191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11631442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22985471 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2899094 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23117489 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 528 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12209631 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231060 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 61072156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.021104 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.077628 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1860363 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 182681 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13006035 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87629176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17207683 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10119076 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21952285 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2766047 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23185818 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2820 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12232999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 233597 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60095316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.044969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38102442 62.39% 62.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2437370 3.99% 66.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2604913 4.27% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2468790 4.04% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1717886 2.81% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1703957 2.79% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1004465 1.64% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1297144 2.12% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9735189 15.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38160956 63.50% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2271093 3.78% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1990023 3.31% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2119724 3.53% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1647401 2.74% 76.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1441763 2.40% 79.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1000150 1.66% 80.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1230223 2.05% 82.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10233983 17.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 61072156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282678 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.419248 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14874533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21847562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21380234 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1066852 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1902975 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3467400 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97940 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120324997 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 332105 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1902975 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16806585 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2006065 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15518837 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20487124 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4350570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117025506 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3001536 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118973415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538271633 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538269997 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1636 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99144341 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19829074 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 778296 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 778691 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12144889 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29749506 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22307130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2475389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3455641 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111742619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 774376 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107620542 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 306039 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11663320 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29339036 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 61072156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.762187 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.902803 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 60095316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279831 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.425025 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14817180 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21950690 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20398412 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086428 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1842606 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3463605 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108661 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119794628 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 354485 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1842606 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16634867 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1966833 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15615217 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19642472 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4393321 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116600703 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4194 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3033361 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 70 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116869923 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536821347 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536814358 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6989 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99147741 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17722182 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 787670 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786973 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12493394 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29971388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22471181 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2503550 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3551864 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111668104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 780017 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107789312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 331076 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11606029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28797672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 76559 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60095316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.793639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.921516 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22164835 36.29% 36.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11626045 19.04% 55.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8572984 14.04% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7394656 12.11% 81.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4788181 7.84% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3517678 5.76% 95.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1664983 2.73% 97.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 808803 1.32% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 533991 0.87% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21617080 35.97% 35.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11242625 18.71% 54.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8368043 13.92% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7334755 12.21% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4853612 8.08% 88.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3598814 5.99% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699571 2.83% 97.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 846136 1.41% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 534680 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 61072156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60095316 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 87531 3.32% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1485029 56.34% 59.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1063128 40.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 104237 3.89% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1507488 56.31% 60.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1065632 39.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57005331 52.97% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87377 0.08% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28993103 26.94% 79.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21534684 20.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56897133 52.79% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88643 0.08% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 206 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29161823 27.05% 79.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21641500 20.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107620542 # Type of FU issued -system.cpu.iq.rate 1.725269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2635688 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 279254757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124195436 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105415832 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 210 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 218 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110256122 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1866930 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107789312 # Type of FU issued +system.cpu.iq.rate 1.752870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2677358 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024839 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 278681648 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124068735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105618069 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 726 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 180 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110466305 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1905391 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2440940 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3458 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15970 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1749935 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2662397 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4708 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1913561 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 52 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1902975 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 953135 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28579 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112593446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 617881 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29749506 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22307130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 757118 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1133 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1194 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15970 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682654 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 198883 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 881537 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106278016 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28622846 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1342526 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1842606 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 954066 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28419 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112530590 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 448477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29971388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22471181 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 763809 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1185 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1150 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 16942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525308 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 249263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 774571 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106544172 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28789537 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1245140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76451 # number of nop insts executed -system.cpu.iew.exec_refs 49854993 # number of memory reference insts executed -system.cpu.iew.exec_branches 14601868 # Number of branches executed -system.cpu.iew.exec_stores 21232147 # Number of stores executed -system.cpu.iew.exec_rate 1.703747 # Inst execution rate -system.cpu.iew.wb_sent 105729046 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105415908 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52516965 # num instructions producing a value -system.cpu.iew.wb_consumers 101175097 # num instructions consuming a value +system.cpu.iew.exec_nop 82469 # number of nop insts executed +system.cpu.iew.exec_refs 50119660 # number of memory reference insts executed +system.cpu.iew.exec_branches 14611553 # Number of branches executed +system.cpu.iew.exec_stores 21330123 # Number of stores executed +system.cpu.iew.exec_rate 1.732621 # Inst execution rate +system.cpu.iew.wb_sent 105962456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105618249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52610922 # num instructions producing a value +system.cpu.iew.wb_consumers 101691142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back +system.cpu.iew.wb_rate 1.717564 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.517360 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 59169182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.700881 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.430495 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70922599 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100641847 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11889102 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 703458 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 696794 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 58252711 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.727677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.445395 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 26246833 44.36% 44.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14645427 24.75% 69.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4228470 7.15% 76.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3643076 6.16% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2266929 3.83% 86.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1888235 3.19% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703093 1.19% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 496274 0.84% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5050845 8.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25477544 43.74% 43.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14542293 24.96% 68.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4151131 7.13% 75.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3607676 6.19% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2313094 3.97% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1905802 3.27% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 675667 1.16% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 497156 0.85% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5082348 8.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70920474 # Number of instructions committed -system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 58252711 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70922599 # Number of instructions committed +system.cpu.commit.committedOps 100641847 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865761 # Number of memory references committed -system.cpu.commit.loads 27308566 # Number of loads committed +system.cpu.commit.refs 47866611 # Number of memory references committed +system.cpu.commit.loads 27308991 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670085 # Number of branches committed +system.cpu.commit.branches 13670510 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478615 # Number of committed integer instructions. +system.cpu.commit.int_insts 91480315 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5050845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5082348 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166686934 # The number of ROB reads -system.cpu.rob.rob_writes 227096473 # The number of ROB writes -system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70914922 # Number of Instructions Simulated -system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated -system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads -system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511674990 # number of integer regfile reads -system.cpu.int_regfile_writes 103897673 # number of integer regfile writes -system.cpu.fp_regfile_reads 166 # number of floating regfile reads -system.cpu.fp_regfile_writes 126 # number of floating regfile writes -system.cpu.misc_regfile_reads 146219619 # number of misc regfile reads -system.cpu.misc_regfile_writes 34754 # number of misc regfile writes -system.cpu.icache.replacements 26131 # number of replacements -system.cpu.icache.tagsinuse 1805.600642 # Cycle average of tags in use -system.cpu.icache.total_refs 12180358 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 165676013 # The number of ROB reads +system.cpu.rob.rob_writes 226913156 # The number of ROB writes +system.cpu.timesIdled 61654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1397744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70917047 # Number of Instructions Simulated +system.cpu.committedOps 100636295 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70917047 # Number of Instructions Simulated +system.cpu.cpi 0.867113 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.867113 # CPI: Total CPI of All Threads +system.cpu.ipc 1.153253 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.153253 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512941825 # number of integer regfile reads +system.cpu.int_regfile_writes 103506893 # number of integer regfile writes +system.cpu.fp_regfile_reads 822 # number of floating regfile reads +system.cpu.fp_regfile_writes 678 # number of floating regfile writes +system.cpu.misc_regfile_reads 145707136 # number of misc regfile reads +system.cpu.misc_regfile_writes 35604 # number of misc regfile writes +system.cpu.icache.replacements 30139 # number of replacements +system.cpu.icache.tagsinuse 1825.169858 # Cycle average of tags in use +system.cpu.icache.total_refs 12199552 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32178 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.127105 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits -system.cpu.icache.overall_hits::total 12180359 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses -system.cpu.icache.overall_misses::total 29272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1825.169858 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.891196 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.891196 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12199556 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12199556 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12199556 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12199556 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12199556 # number of overall hits +system.cpu.icache.overall_hits::total 12199556 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33443 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33443 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33443 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33443 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33443 # number of overall misses +system.cpu.icache.overall_misses::total 33443 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 390329000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 390329000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 390329000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 390329000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 390329000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 390329000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12232999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12232999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12232999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12232999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12232999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12232999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11671.470861 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,223 +382,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1227 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1227 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1227 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1227 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32216 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32216 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32216 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32216 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32216 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32216 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262568000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 262568000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262568000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 262568000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262568000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 262568000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8150.235908 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157892 # number of replacements -system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use -system.cpu.dcache.total_refs 44746410 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits -system.cpu.dcache.overall_hits::total 44709945 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 108879 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1539615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1539615 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1648494 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1648494 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1648494 # number of overall misses -system.cpu.dcache.overall_misses::total 1648494 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2418798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2418798500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52283607500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52283607500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158787 # number of replacements +system.cpu.dcache.tagsinuse 4071.855025 # Cycle average of tags in use +system.cpu.dcache.total_refs 44862936 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162883 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 275.430438 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 309114000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.855025 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26515454 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26515454 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18310363 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18310363 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 19173 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 19173 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 17801 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 17801 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44825817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44825817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44825817 # number of overall hits +system.cpu.dcache.overall_hits::total 44825817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 110570 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 110570 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1539538 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1539538 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1650108 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1650108 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650108 # number of overall misses +system.cpu.dcache.overall_misses::total 1650108 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2444111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2444111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52524497000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52524497000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 460000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 460000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54968608000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54968608000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54968608000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54968608000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26626024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26626024 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 18950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 17376 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 17376 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46358439 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46358439 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46358439 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46358439 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004107 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077563 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035560 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035560 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19208 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 19208 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46475925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46475925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46475925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46475925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077559 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001822 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035505 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035505 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22104.648639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34117.051349 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19136.363636 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123473 # number of writebacks -system.cpu.dcache.writebacks::total 123473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53766 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53766 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1486461 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1486461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55113 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55113 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106920 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106920 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162033 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162033 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162033 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162033 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1035745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1035745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3662420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3662420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4698165500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002079 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 123777 # number of writebacks +system.cpu.dcache.writebacks::total 123777 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432641 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1432641 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1487185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1487185 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1487185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1487185 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56026 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56026 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106897 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106897 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162923 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162923 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162923 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162923 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045999000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045999000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3665143000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3665143000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4711142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4711142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4711142000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4711142000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18669.885410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34286.677830 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114916 # number of replacements -system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use -system.cpu.l2cache.total_refs 72481 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 115366 # number of replacements +system.cpu.l2cache.tagsinuse 18380.056703 # Cycle average of tags in use +system.cpu.l2cache.total_refs 77246 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 134234 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.575458 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15934.147051 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 839.668596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1530.891195 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.486272 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025625 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.046719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.558615 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 22667 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27904 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 50571 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 123474 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 123474 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4310 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4310 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22667 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 32214 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 54881 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22667 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 32214 # number of overall hits -system.cpu.l2cache.overall_hits::total 54881 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5494 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32667 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102597 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102597 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5494 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129770 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 135264 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5494 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129770 # number of overall misses -system.cpu.l2cache.overall_misses::total 135264 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188188000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 930191000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1118379000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3526118000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3526118000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 188188000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4456309000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4644497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 188188000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4456309000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4644497000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 28161 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55077 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 83238 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 123474 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 123474 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 106907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 106907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 28161 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 161984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 190145 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 28161 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195093 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.493364 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.681818 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959685 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195093 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.801129 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195093 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.801129 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15926.417770 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 869.276792 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1584.362140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.486036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026528 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048351 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.560915 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 26467 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 28565 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 55032 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 123777 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 123777 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4312 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4312 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26467 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 32877 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 59344 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26467 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 32877 # number of overall hits +system.cpu.l2cache.overall_hits::total 59344 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5707 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27425 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33132 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102581 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102581 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5707 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 130006 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 135713 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5707 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 130006 # number of overall misses +system.cpu.l2cache.overall_misses::total 135713 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195425500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 938664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1134089500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 34000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3518121500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3518121500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195425500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4456785500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4652211000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195425500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4456785500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4652211000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 32174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55990 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 88164 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123777 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123777 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 40 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 40 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106893 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106893 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 32174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 195057 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 32174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162883 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 195057 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177379 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489820 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.725000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959661 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177379 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.798156 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177379 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.798156 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34243.122481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34226.581586 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1172.413793 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34296.034353 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34243.122481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34281.383167 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -607,59 +608,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks -system.cpu.l2cache.writebacks::total 88457 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5470 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27116 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32586 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129713 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 135183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129713 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 135183 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169929500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 842885000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1012814500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3197894500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3197894500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169929500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 88455 # number of writebacks +system.cpu.l2cache.writebacks::total 88455 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5684 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27361 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33045 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102581 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102581 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5684 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135626 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5684 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135626 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176568000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850424500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1026992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 901000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 901000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044037000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4220605000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044037000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4220605000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959661 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.039409 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.630788 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31068.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.592780 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index d36129661..b48111dc2 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:25:39 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:49:22 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1009857089500 because target called exit() +Exiting @ tick 1009998808500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index d5a78ee76..b53980a02 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009857 # Number of seconds simulated -sim_ticks 1009857089500 # Number of ticks simulated -final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.009999 # Number of seconds simulated +sim_ticks 1009998808500 # Number of ticks simulated +final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137029 # Simulator instruction rate (inst/s) -host_op_rate 137029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76042102 # Simulator tick rate (ticks/s) -host_mem_usage 209964 # Number of bytes of host memory used -host_seconds 13280.24 # Real time elapsed on the host +host_inst_rate 135204 # Simulator instruction rate (inst/s) +host_op_rate 135204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75039783 # Simulator tick rate (ticks/s) +host_mem_usage 209960 # Number of bytes of host memory used +host_seconds 13459.51 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172617984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 172618048 # Number of bytes read from this memory +system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written 74938304 # Number of bytes written to this memory -system.physmem.num_reads 2697156 # Number of read requests responded to by this memory +system.physmem.num_reads 2697157 # Number of read requests responded to by this memory system.physmem.num_writes 1170911 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614420 # DTB read hits +system.cpu.dtb.read_hits 444614444 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511498 # DTB read accesses -system.cpu.dtb.write_hits 160920903 # DTB write hits +system.cpu.dtb.read_accesses 449511522 # DTB read accesses +system.cpu.dtb.write_hits 160920906 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622207 # DTB write accesses -system.cpu.dtb.data_hits 605535323 # DTB hits +system.cpu.dtb.write_accesses 162622210 # DTB write accesses +system.cpu.dtb.data_hits 605535350 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133705 # DTB accesses -system.cpu.itb.fetch_hits 233080732 # ITB hits +system.cpu.dtb.data_accesses 612133732 # DTB accesses +system.cpu.itb.fetch_hits 231980230 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 233080754 # ITB accesses +system.cpu.itb.fetch_accesses 231980252 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019714180 # number of cpu cycles simulated +system.cpu.numCycles 2019997618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed. -system.cpu.activity 78.072669 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. +system.cpu.activity 78.063714 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits +system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617252269 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989652 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use -system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use +system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits -system.cpu.icache.overall_hits::total 233079667 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses -system.cpu.icache.overall_misses::total 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits +system.cpu.icache.overall_hits::total 231979155 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses +system.cpu.icache.overall_misses::total 1072 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use -system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use +system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271428 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157798653 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157798653 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595070081 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595070081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595070081 # number of overall hits -system.cpu.dcache.overall_hits::total 595070081 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324235 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324235 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2929849 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2929849 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254084 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254084 # number of overall misses -system.cpu.dcache.overall_misses::total 10254084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles +system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits +system.cpu.dcache.overall_hits::total 595069970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses +system.cpu.dcache.overall_misses::total 10254195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -239,28 +239,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks system.cpu.dcache.writebacks::total 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses @@ -269,36 +269,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686299 # number of replacements -system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2686301 # number of replacements +system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits @@ -309,41 +309,41 @@ system.cpu.l2cache.demand_hits::cpu.data 6415150 # nu system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 858 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2697156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 858 # number of overall misses +system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses -system.cpu.l2cache.overall_misses::total 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44903500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94408605500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94453509000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94456733000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses @@ -351,13 +351,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -368,28 +368,28 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks system.cpu.l2cache.writebacks::total 1170911 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses @@ -397,13 +397,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 17636478e..6f27fa680 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:26:22 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:50:00 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 615292058500 because target called exit() +Exiting @ tick 614317285000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a211c592b..2f0a96bc0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.615292 # Number of seconds simulated -sim_ticks 615292058500 # Number of ticks simulated -final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.614317 # Number of seconds simulated +sim_ticks 614317285000 # Number of ticks simulated +final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195644 # Simulator instruction rate (inst/s) -host_op_rate 195644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69340417 # Simulator tick rate (ticks/s) -host_mem_usage 211040 # Number of bytes of host memory used -host_seconds 8873.50 # Real time elapsed on the host +host_inst_rate 195309 # Simulator instruction rate (inst/s) +host_op_rate 195309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69112237 # Simulator tick rate (ticks/s) +host_mem_usage 211096 # Number of bytes of host memory used +host_seconds 8888.69 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173080384 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74996480 # Number of bytes written to this memory -system.physmem.num_reads 2704381 # Number of read requests responded to by this memory -system.physmem.num_writes 1171820 # Number of write requests responded to by this memory +system.physmem.bytes_read 173249728 # Number of bytes read from this memory +system.physmem.bytes_inst_read 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_written 75020608 # Number of bytes written to this memory +system.physmem.num_reads 2707027 # Number of read requests responded to by this memory +system.physmem.num_writes 1172197 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 281297933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 121887612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 403185545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282019947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 404140242 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 602552271 # DTB read hits -system.cpu.dtb.read_misses 10614048 # DTB read misses +system.cpu.dtb.read_hits 613430411 # DTB read hits +system.cpu.dtb.read_misses 10984160 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 613166319 # DTB read accesses -system.cpu.dtb.write_hits 207913538 # DTB write hits -system.cpu.dtb.write_misses 6806894 # DTB write misses +system.cpu.dtb.read_accesses 624414571 # DTB read accesses +system.cpu.dtb.write_hits 208466528 # DTB write hits +system.cpu.dtb.write_misses 6835381 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214720432 # DTB write accesses -system.cpu.dtb.data_hits 810465809 # DTB hits -system.cpu.dtb.data_misses 17420942 # DTB misses +system.cpu.dtb.write_accesses 215301909 # DTB write accesses +system.cpu.dtb.data_hits 821896939 # DTB hits +system.cpu.dtb.data_misses 17819541 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 827886751 # DTB accesses -system.cpu.itb.fetch_hits 385401096 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 839716480 # DTB accesses +system.cpu.itb.fetch_hits 401793450 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 385401134 # ITB accesses +system.cpu.itb.fetch_accesses 401793501 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1230584118 # number of cpu cycles simulated +system.cpu.numCycles 1228634571 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 368788427 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 284655595 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19443984 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 335810201 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 329206676 # Number of BTB hits +system.cpu.BPredUnit.lookups 381761173 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 293769294 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18987814 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 267293652 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262906896 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 24336435 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1745 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 397544739 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3103801885 # Number of instructions fetch has processed -system.cpu.fetch.Branches 368788427 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 353543111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 607804339 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 131920976 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 113986099 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 385401096 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9585477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1225061020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.533590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.019465 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25187123 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6338 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 413237757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162516337 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381761173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 288094019 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 577364277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 136217023 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 121997880 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1099 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401793450 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10461001 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1223060627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.585740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.163188 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 617256681 50.39% 50.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52795543 4.31% 54.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 34983733 2.86% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 53721044 4.39% 61.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 135046011 11.02% 72.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74719502 6.10% 79.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 51323378 4.19% 83.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 43567102 3.56% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 161648026 13.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 645696350 52.79% 52.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43491890 3.56% 56.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22343235 1.83% 58.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40947227 3.35% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127434510 10.42% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63845944 5.22% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40777509 3.33% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30328214 2.48% 82.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208195748 17.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1225061020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299686 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.522218 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 426009855 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101612047 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 578250802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13464213 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 105724103 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 57118243 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 889 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3023280149 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1933 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 105724103 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 448226724 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 58166398 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 568166155 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 44774196 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2937967281 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 510732 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1525332 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40266143 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2197783940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3797275773 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3796267426 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1008347 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1223060627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310720 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.574009 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 442798352 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107558051 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546235232 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16010373 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 110458619 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60401844 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3083471433 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 110458619 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 464144259 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 59142722 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539650759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49657978 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3001214428 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 543640 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1796675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 45123611 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2245055787 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3876991628 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3875592361 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1399267 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 821580977 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 180 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 178 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 93606956 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 663953354 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 248514283 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54484359 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 31450059 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647456890 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2459087861 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1981205 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 899874302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 377613541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1225061020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007319 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.938295 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 868852824 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 246 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 246 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105587598 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 677972013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251679590 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61268278 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33927488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2695905085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2494910980 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3371495 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 947658243 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 400911726 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1223060627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.039892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.968690 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 390052689 31.84% 31.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197664545 16.14% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194534552 15.88% 63.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152397104 12.44% 76.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 138172730 11.28% 87.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75830053 6.19% 93.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56958095 4.65% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14036871 1.15% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5414381 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 388423198 31.76% 31.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 198296660 16.21% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 183821950 15.03% 63.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153332369 12.54% 75.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 135876340 11.11% 86.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79653803 6.51% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63718799 5.21% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14613920 1.19% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5323588 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1225061020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1223060627 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1870870 11.50% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11042349 67.89% 79.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3352440 20.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2019639 10.76% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12227310 65.14% 75.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4524424 24.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1607157901 65.36% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 631365239 25.67% 91.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220564170 8.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1630534588 65.35% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 292 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 176 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642000765 25.73% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222374992 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2459087861 # Type of FU issued -system.cpu.iq.rate 1.998309 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16265659 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006615 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6159722029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3546409355 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2357254024 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1761577 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1006663 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 825129 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2474476437 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 877083 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54564037 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2494910980 # Type of FU issued +system.cpu.iq.rate 2.030637 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18771373 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007524 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6233033546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3642313752 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2391820907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1991909 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1355027 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 871735 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2512703438 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 978915 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57347014 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 219357691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 276764 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 87944 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 87785781 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233376350 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 247116 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107150 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 90951088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 71 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162830 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 227 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162717 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 105724103 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22305472 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1113476 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2788688851 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12944530 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 663953354 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 248514283 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 231462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18115 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 87944 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 20335960 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2039327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22375287 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2405013673 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 613166540 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 54074188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 110458619 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22362549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1121439 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2838563958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17898504 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 677972013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 251679590 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 208 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 216005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15651 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107150 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13325619 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8884381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22210000 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2442758638 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 624415478 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52152342 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141231807 # number of nop insts executed -system.cpu.iew.exec_refs 827886992 # number of memory reference insts executed -system.cpu.iew.exec_branches 294323253 # Number of branches executed -system.cpu.iew.exec_stores 214720452 # Number of stores executed -system.cpu.iew.exec_rate 1.954368 # Inst execution rate -system.cpu.iew.wb_sent 2384887539 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2358079153 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347433304 # num instructions producing a value -system.cpu.iew.wb_consumers 1703552370 # num instructions consuming a value +system.cpu.iew.exec_nop 142658665 # number of nop insts executed +system.cpu.iew.exec_refs 839717432 # number of memory reference insts executed +system.cpu.iew.exec_branches 299305457 # Number of branches executed +system.cpu.iew.exec_stores 215301954 # Number of stores executed +system.cpu.iew.exec_rate 1.988190 # Inst execution rate +system.cpu.iew.wb_sent 2421432535 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2392692642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1370537618 # num instructions producing a value +system.cpu.iew.wb_consumers 1736169101 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.916228 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back +system.cpu.iew.wb_rate 1.947440 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789403 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 782630603 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1119336917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625766 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.487685 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18986848 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1112602008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.635607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 586822597 52.43% 52.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 186310200 16.64% 69.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95274520 8.51% 77.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53747896 4.80% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37177452 3.32% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26985316 2.41% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21737766 1.94% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22635146 2.02% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88646024 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 589258835 52.96% 52.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 179628091 16.14% 69.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90469983 8.13% 77.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53793341 4.83% 82.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36407733 3.27% 85.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27937238 2.51% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22627047 2.03% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23085278 2.07% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89394462 8.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1112602008 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88646024 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89394462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3500830866 # The number of ROB reads -system.cpu.rob.rob_writes 5217723058 # The number of ROB writes -system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3539839075 # The number of ROB reads +system.cpu.rob.rob_writes 5315403238 # The number of ROB writes +system.cpu.timesIdled 405378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5573944 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads -system.cpu.ipc 1.410748 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.410748 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3237009112 # number of integer regfile reads -system.cpu.int_regfile_writes 1887111006 # number of integer regfile writes -system.cpu.fp_regfile_reads 12550 # number of floating regfile reads -system.cpu.fp_regfile_writes 508 # number of floating regfile writes +system.cpu.cpi 0.707721 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.707721 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.412986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3284485483 # number of integer regfile reads +system.cpu.int_regfile_writes 1919152187 # number of integer regfile writes +system.cpu.fp_regfile_reads 52475 # number of floating regfile reads +system.cpu.fp_regfile_writes 577 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 746.155324 # Cycle average of tags in use -system.cpu.icache.total_refs 385399748 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 800.240430 # Cycle average of tags in use +system.cpu.icache.total_refs 401791975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 409573.878695 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 746.155324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.364334 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.364334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 385399748 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 385399748 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 385399748 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 385399748 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 385399748 # number of overall hits -system.cpu.icache.overall_hits::total 385399748 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1348 # number of overall misses -system.cpu.icache.overall_misses::total 1348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47398000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47398000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47398000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47398000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47398000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47398000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 385401096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 385401096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 385401096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 385401096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 385401096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 385401096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.721068 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.721068 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.721068 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 800.240430 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.390742 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.390742 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 401791975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 401791975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 401791975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 401791975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 401791975 # number of overall hits +system.cpu.icache.overall_hits::total 401791975 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses +system.cpu.icache.overall_misses::total 1475 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50482500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50482500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50482500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50482500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50482500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50482500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 401793450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 401793450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 401793450 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 401793450 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 401793450 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 401793450 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,257 +371,259 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 406 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 406 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 406 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 406 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 406 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 942 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 942 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 942 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 942 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 942 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 942 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33448000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33448000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 494 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 494 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 494 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 494 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 494 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34897000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34897000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34897000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34897000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34897000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34897000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35507.430998 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35507.430998 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35507.430998 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35572.884811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9159821 # number of replacements -system.cpu.dcache.tagsinuse 4086.961398 # Cycle average of tags in use -system.cpu.dcache.total_refs 693411949 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9163917 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.667637 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5157991000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.961398 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997793 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997793 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 537597174 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 537597174 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155814773 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155814773 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 693411947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 693411947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 693411947 # number of overall hits -system.cpu.dcache.overall_hits::total 693411947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10313435 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10313435 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4913729 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4913729 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15227164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15227164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15227164 # number of overall misses -system.cpu.dcache.overall_misses::total 15227164 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 172073260500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 172073260500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 137521396881 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 137521396881 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 309594657381 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 309594657381 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 309594657381 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 309594657381 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 547910609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 547910609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9176629 # number of replacements +system.cpu.dcache.tagsinuse 4086.046414 # Cycle average of tags in use +system.cpu.dcache.total_refs 701329771 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180725 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.391545 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5690384000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.046414 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 545515438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 545515438 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155814328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155814328 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 701329766 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 701329766 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 701329766 # number of overall hits +system.cpu.dcache.overall_hits::total 701329766 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10490369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10490369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4914174 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4914174 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15404543 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15404543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15404543 # number of overall misses +system.cpu.dcache.overall_misses::total 15404543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 175047680000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 175047680000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 137439947293 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 137439947293 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 47000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 47000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 312487627293 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 312487627293 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 312487627293 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 312487627293 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 556005807 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 556005807 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 708639111 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 708639111 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 708639111 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 708639111 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018823 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030572 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021488 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021488 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16684.379210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27987.175703 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20331.734615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20331.734615 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 119268264 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37813 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65113 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.160315 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 716734309 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 716734309 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 716734309 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 716734309 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018867 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030574 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.285714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021493 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021493 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16686.513125 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27968.066921 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3157.127470 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32992.651688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3077535 # number of writebacks -system.cpu.dcache.writebacks::total 3077535 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3034555 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3034555 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3028693 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3028693 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6063248 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6063248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6063248 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6063248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7278880 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7278880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1885036 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3083289 # number of writebacks +system.cpu.dcache.writebacks::total 3083289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3193376 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3193376 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3030443 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3030443 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6223819 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6223819 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6223819 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6223819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296993 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296993 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9163916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9163916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9163916 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9163916 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 81039107500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 81039107500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38640356536 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38640356536 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180724 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180724 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180724 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180724 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 81348046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 81348046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38571686956 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38571686956 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119679464036 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 119679464036 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119679464036 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 119679464036 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013285 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011728 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012932 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012932 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11133.458375 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20498.471401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119919732956 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 119919732956 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119919732956 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 119919732956 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013124 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11148.160071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13059.860439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13059.860439 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2693797 # number of replacements -system.cpu.l2cache.tagsinuse 26669.588705 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7633154 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2718439 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.807918 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 126954186500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10766.563932 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.661075 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15881.363698 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.328569 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000661 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.484661 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.813891 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5458962 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5458962 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3077535 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3077535 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1001516 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1001516 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6460478 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6460478 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6460478 # number of overall hits -system.cpu.l2cache.overall_hits::total 6460478 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 942 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1819910 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1820852 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 883529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 883529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 942 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2703439 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2704381 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 942 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2703439 # number of overall misses -system.cpu.l2cache.overall_misses::total 2704381 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32355500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62491703500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62524059000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 30450873000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 30450873000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32355500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 92942576500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 92974932000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32355500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 92942576500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 92974932000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 942 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7278872 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7279814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3077535 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3077535 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1885045 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1885045 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 942 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9163917 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9164859 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 942 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9163917 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9164859 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2696556 # number of replacements +system.cpu.l2cache.tagsinuse 26644.209628 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7654288 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2721176 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.812860 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 130971058500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10796.913806 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 24.565729 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15822.730093 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.329496 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000750 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.813117 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5472701 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5472701 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3083289 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3083289 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1001978 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1001978 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6474679 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6474679 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6474679 # number of overall hits +system.cpu.l2cache.overall_hits::total 6474679 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1824281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1825262 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 881765 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 881765 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 981 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2706046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2707027 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 981 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2706046 # number of overall misses +system.cpu.l2cache.overall_misses::total 2707027 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33718000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62643106000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 62676824000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 30390866500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 30390866500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 33718000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 93033972500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 93067690500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 33718000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 93033972500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 93067690500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 981 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296982 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3083289 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3083289 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883743 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883743 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 981 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180725 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 981 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180725 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250026 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468704 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250005 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468092 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.295009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.294753 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.295009 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34347.664544 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34337.798847 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.052081 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34347.664544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34379.387329 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 17522000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1704 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10404.988124 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1171820 # number of writebacks -system.cpu.l2cache.writebacks::total 1171820 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 942 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1819910 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1820852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 883529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 883529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 942 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2703439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2704381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 942 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2703439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2704381 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29342500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56708410500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56737753000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27632234500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27632234500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29342500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84340645000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 84369987500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29342500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84340645000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 84369987500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks +system.cpu.l2cache.writebacks::total 1172197 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 981 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1824281 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1825262 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 881765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 881765 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2706046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2707027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 981 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2706046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2707027 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 30568000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56848109000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56878677000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 27575743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 27575743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84423852000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 84454420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250026 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468704 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31149.150743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31160.008187 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31274.847232 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 4a2c04206..8fb7001b0 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:28:08 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:51:32 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 483300356500 because target called exit() +Exiting @ tick 464073050000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 1d3623ac5..1790c7443 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.483300 # Number of seconds simulated -sim_ticks 483300356500 # Number of ticks simulated -final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464073 # Number of seconds simulated +sim_ticks 464073050000 # Number of ticks simulated +final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175200 # Simulator instruction rate (inst/s) -host_op_rate 195449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54820940 # Simulator tick rate (ticks/s) -host_mem_usage 223460 # Number of bytes of host memory used -host_seconds 8815.98 # Real time elapsed on the host -sim_insts 1544563036 # Number of instructions simulated -sim_ops 1723073849 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 188191232 # Number of bytes read from this memory -system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 77928320 # Number of bytes written to this memory -system.physmem.num_reads 2940488 # Number of read requests responded to by this memory -system.physmem.num_writes 1217630 # Number of write requests responded to by this memory +host_inst_rate 176271 # Simulator instruction rate (inst/s) +host_op_rate 196643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52961695 # Simulator tick rate (ticks/s) +host_mem_usage 223676 # Number of bytes of host memory used +host_seconds 8762.43 # Real time elapsed on the host +sim_insts 1544563056 # Number of instructions simulated +sim_ops 1723073869 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 189754368 # Number of bytes read from this memory +system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_written 78230272 # Number of bytes written to this memory +system.physmem.num_reads 2964912 # Number of read requests responded to by this memory +system.physmem.num_writes 1222348 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 389387737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 95080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 161242008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 550629745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 966600714 # number of cpu cycles simulated +system.cpu.numCycles 928146101 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 298802813 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 243899992 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18315213 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264194846 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 238628617 # Number of BTB hits +system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17678661 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3338 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 296004888 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2174228266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298802813 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 256307278 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 484507329 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86919023 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 107617273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 140 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285078339 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5300000 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 956319158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.521362 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.026261 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed +system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 471811881 49.34% 49.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35281645 3.69% 53.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 65131283 6.81% 59.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 66854544 6.99% 66.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46816923 4.90% 71.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59777101 6.25% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 54237422 5.67% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 17725648 1.85% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 138682711 14.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 956319158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309127 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.249355 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322991638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92138952 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 459388324 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13611363 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68188881 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46868404 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2351885426 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2233 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68188881 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343108382 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46584354 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 451644595 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46767188 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2295012184 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19840 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2699078 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37731214 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2263685405 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10601312044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10601310861 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1183 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 557365454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 9613 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 9609 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98574159 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 618665433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221947140 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 73974093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 60832432 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2187079584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018219576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3314512 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 457863024 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1047846495 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1559 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 956319158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.110404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.840875 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10570831770 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10570827064 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2190647855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016093744 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1075025866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1349 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 261846751 27.38% 27.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150992981 15.79% 43.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 168342829 17.60% 60.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136328017 14.26% 75.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124939866 13.06% 88.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73493141 7.69% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 29213551 3.05% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10245765 1.07% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 916257 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158306173 17.24% 59.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116338081 12.67% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 956319158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 899945 3.67% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 187 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19005921 77.47% 81.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4627423 18.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238740250 61.38% 61.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1017622 0.05% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 583895352 28.93% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194566336 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234318257 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018219576 # Type of FU issued -system.cpu.iq.rate 2.087956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24533476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012156 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5020606045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2645122896 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958251270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 253 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042752922 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55694024 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016093744 # Type of FU issued +system.cpu.iq.rate 2.172173 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4980646050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958144552 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2041160488 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 132738662 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211257 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180594 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 47100094 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451914 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68188881 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22161421 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1213363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2187099355 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7278228 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 618665433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221947140 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1999 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180594 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18897487 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1819209 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20716696 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1985947715 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570245268 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 32271861 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1789 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986590916 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17709 # number of nop insts executed -system.cpu.iew.exec_refs 761448250 # number of memory reference insts executed -system.cpu.iew.exec_branches 238637230 # Number of branches executed -system.cpu.iew.exec_stores 191202982 # Number of stores executed -system.cpu.iew.exec_rate 2.054569 # Inst execution rate -system.cpu.iew.wb_sent 1967185295 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958251378 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1288041557 # num instructions producing a value -system.cpu.iew.wb_consumers 2036752533 # num instructions consuming a value +system.cpu.iew.exec_nop 7973 # number of nop insts executed +system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed +system.cpu.iew.exec_branches 238204396 # Number of branches executed +system.cpu.iew.exec_stores 190840224 # Number of stores executed +system.cpu.iew.exec_rate 2.140386 # Inst execution rate +system.cpu.iew.wb_sent 1967133110 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958144749 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296172102 # num instructions producing a value +system.cpu.iew.wb_consumers 2068722659 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back +system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1544563054 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1723073867 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888130278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.940114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.672278 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 382955223 43.12% 43.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 200739073 22.60% 65.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 81923550 9.22% 74.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 38679338 4.36% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19675426 2.22% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30976281 3.49% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22277703 2.51% 87.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12029119 1.35% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98874565 11.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563054 # Number of instructions committed -system.cpu.commit.committedOps 1723073867 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563074 # Number of instructions committed +system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773817 # Number of memory references committed -system.cpu.commit.loads 485926771 # Number of loads committed +system.cpu.commit.refs 660773825 # Number of memory references committed +system.cpu.commit.loads 485926775 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462365 # Number of branches committed +system.cpu.commit.branches 213462369 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98874565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2976436889 # The number of ROB reads -system.cpu.rob.rob_writes 4442782654 # The number of ROB writes -system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563036 # Number of Instructions Simulated -system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated -system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads -system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads -system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes -system.cpu.fp_regfile_reads 96 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 2912823996 # number of misc regfile reads -system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 609.966952 # Cycle average of tags in use -system.cpu.icache.total_refs 285077321 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2935066834 # The number of ROB reads +system.cpu.rob.rob_writes 4448881416 # The number of ROB writes +system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563056 # Number of Instructions Simulated +system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated +system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads +system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9951907737 # number of integer regfile reads +system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes +system.cpu.fp_regfile_reads 210 # number of floating regfile reads +system.cpu.fp_regfile_writes 230 # number of floating regfile writes +system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads +system.cpu.misc_regfile_writes 134 # number of misc regfile writes +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use +system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 609.966952 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.297835 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.297835 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285077321 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285077321 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285077321 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285077321 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285077321 # number of overall hits -system.cpu.icache.overall_hits::total 285077321 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1018 # number of overall misses -system.cpu.icache.overall_misses::total 1018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35270500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35270500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35270500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35270500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285078339 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285078339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285078339 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285078339 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits +system.cpu.icache.overall_hits::total 283791788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38624000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38624000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 283792946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 283792946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 283792946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 283792946 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 283792946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 283792946 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33354.058722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,269 +382,269 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 746 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25653000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25653000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 372 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 372 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 372 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 372 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 372 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27049500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27049500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27049500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27049500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27049500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27049500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34414.122137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9570609 # number of replacements -system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use -system.cpu.dcache.total_refs 666885051 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.729265 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 499489564 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 499489564 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167395365 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167395365 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 666884929 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666884929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666884929 # number of overall hits -system.cpu.dcache.overall_hits::total 666884929 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10445560 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10445560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5190682 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5190682 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15636242 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15636242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15636242 # number of overall misses -system.cpu.dcache.overall_misses::total 15636242 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 312990275746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 312990275746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 509935124 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9618384 # number of replacements +system.cpu.dcache.tagsinuse 4087.732309 # Cycle average of tags in use +system.cpu.dcache.total_refs 660741585 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9622480 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.666454 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3347848000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.732309 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997982 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997982 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 493363105 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 493363105 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167378321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167378321 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660741426 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660741426 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660741426 # number of overall hits +system.cpu.dcache.overall_hits::total 660741426 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10695472 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10695472 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5207726 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5207726 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15903198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15903198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15903198 # number of overall misses +system.cpu.dcache.overall_misses::total 15903198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189107739500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189107739500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129597679387 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129597679387 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 148000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 148000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 318705418887 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 318705418887 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 318705418887 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 318705418887 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 504058577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 504058577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 682521171 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 682521171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 682521171 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 682521171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030076 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022910 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022910 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 676644624 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 676644624 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 676644624 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 676644624 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021219 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041237 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.102760 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3128454 # number of writebacks -system.cpu.dcache.writebacks::total 3128454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6061537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6061537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9574705 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9574705 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 3133951 # number of writebacks +system.cpu.dcache.writebacks::total 3133951 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2966989 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2966989 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313729 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3313729 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6280718 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6280718 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6280718 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6280718 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728483 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7728483 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893997 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893997 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9622480 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9622480 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9622480 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9622480 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93034311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 93034311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45389589120 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45389589120 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138423900120 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138423900120 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138423900120 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138423900120 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12037.848954 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23964.974137 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2928111 # number of replacements -system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7850665 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10799.372069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 11.094827 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15969.046951 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.329571 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.487337 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.817246 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5654817 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5654844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3128454 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3128454 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 980108 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 980108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 6634925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6634952 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 6634925 # number of overall hits -system.cpu.l2cache.overall_hits::total 6634952 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 719 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2027251 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2027970 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 912529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 912529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2939780 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2940499 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 719 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2939780 # number of overall misses -system.cpu.l2cache.overall_misses::total 2940499 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24699000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69597988500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 69622687500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101273900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24699000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101273900000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 746 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7682068 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7682814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 746 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9574705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9575451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 746 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9574705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9575451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963807 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.263894 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.482147 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963807 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307036 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963807 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307036 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked +system.cpu.l2cache.replacements 2952443 # number of replacements +system.cpu.l2cache.tagsinuse 26872.767236 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7878289 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2979766 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.643929 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 101003264500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10760.518963 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 11.047760 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16101.200513 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.328385 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.491370 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.820092 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5679969 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5679997 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3133951 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3133951 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 978347 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 978347 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6658316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6658344 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 6658316 # number of overall hits +system.cpu.l2cache.overall_hits::total 6658344 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 758 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 2048513 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2049271 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 915651 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 915651 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 758 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2964164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2964922 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 758 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2964164 # number of overall misses +system.cpu.l2cache.overall_misses::total 2964922 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26043500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70322097500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70348141000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31765624000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 31765624000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26043500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102087721500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102113765000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26043500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102087721500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102113765000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7728482 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7729268 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3133951 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3133951 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893998 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9622480 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9623266 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9622480 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9623266 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964377 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265060 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483449 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964377 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308046 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964377 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308046 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.179420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.362817 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34691.846566 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 57298000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6751 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8505.426590 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8487.335210 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1217630 # number of writebacks -system.cpu.l2cache.writebacks::total 1217630 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1222348 # number of writebacks +system.cpu.l2cache.writebacks::total 1222348 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 718 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2027241 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2027959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 718 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2939770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2940488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 718 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2939770 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2940488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22382500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63220880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63243262500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22382500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92033269000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 92055651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22382500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92033269000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 92055651500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.263893 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.482147 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2048504 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2049261 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915651 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 915651 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ddac6bec8..6032e061b 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:36:18 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:58:42 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41833966000 because target called exit() +122 123 124 Exiting @ tick 42005374000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7525585e3..2e73aee88 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041834 # Number of seconds simulated -sim_ticks 41833966000 # Number of ticks simulated -final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042005 # Number of seconds simulated +sim_ticks 42005374000 # Number of ticks simulated +final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151560 # Simulator instruction rate (inst/s) -host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_inst_rate 147839 # Simulator instruction rate (inst/s) +host_op_rate 147839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67571644 # Simulator tick rate (ticks/s) host_mem_usage 213560 # Number of bytes of host memory used -host_seconds 606.38 # Real time elapsed on the host +host_seconds 621.64 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 4938 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 9991202 # ITB hits +system.cpu.itb.fetch_hits 10037351 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9991251 # ITB accesses +system.cpu.itb.fetch_accesses 10037400 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83667933 # number of cpu cycles simulated +system.cpu.numCycles 84010749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. -system.cpu.activity 90.796172 # Percentage of cycles cpu is active +system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. +system.cpu.activity 90.791663 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -74,158 +74,158 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits +system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26652325 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26765541 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7551 # number of replacements -system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use -system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8111 # number of replacements +system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use +system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits -system.cpu.icache.overall_hits::total 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses -system.cpu.icache.overall_misses::total 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits +system.cpu.icache.overall_hits::total 10025618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses +system.cpu.icache.overall_misses::total 11728 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits -system.cpu.dcache.overall_hits::total 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses -system.cpu.dcache.overall_misses::total 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits +system.cpu.dcache.overall_hits::total 26491208 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses +system.cpu.dcache.overall_misses::total 6093 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -238,28 +238,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -268,49 +268,49 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.overall_hits::total 7281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -322,44 +322,44 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,31 +379,31 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f5b2c31fd..58e98acc5 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:45:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:07:15 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 29167093500 because target called exit() +122 123 124 Exiting @ tick 23638033500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 221154573..8502942e2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.029167 # Number of seconds simulated -sim_ticks 29167093500 # Number of ticks simulated -final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023638 # Number of seconds simulated +sim_ticks 23638033500 # Number of ticks simulated +final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198361 # Simulator instruction rate (inst/s) -host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_inst_rate 231314 # Simulator instruction rate (inst/s) +host_op_rate 231314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64954124 # Simulator tick rate (ticks/s) host_mem_usage 214912 # Number of bytes of host memory used -host_seconds 424.38 # Real time elapsed on the host +host_seconds 363.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 332416 # Number of bytes read from this memory -system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5194 # Number of read requests responded to by this memory +system.physmem.num_reads 5251 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25236325 # DTB read hits -system.cpu.dtb.read_misses 540509 # DTB read misses +system.cpu.dtb.read_hits 23223377 # DTB read hits +system.cpu.dtb.read_misses 198479 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 25776834 # DTB read accesses -system.cpu.dtb.write_hits 7362909 # DTB write hits -system.cpu.dtb.write_misses 1032 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7363941 # DTB write accesses -system.cpu.dtb.data_hits 32599234 # DTB hits -system.cpu.dtb.data_misses 541541 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 33140775 # DTB accesses -system.cpu.itb.fetch_hits 18604047 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 23421856 # DTB read accesses +system.cpu.dtb.write_hits 7079825 # DTB write hits +system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7081228 # DTB write accesses +system.cpu.dtb.data_hits 30303202 # DTB hits +system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 30503084 # DTB accesses +system.cpu.itb.fetch_hits 14943347 # ITB hits +system.cpu.itb.fetch_misses 91 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 18604132 # ITB accesses +system.cpu.itb.fetch_accesses 14943438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,247 +53,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 58334188 # number of cpu cycles simulated +system.cpu.numCycles 47276068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits +system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued -system.cpu.iq.rate 1.798857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued +system.cpu.iq.rate 2.051269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11799539 # number of nop insts executed -system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed -system.cpu.iew.exec_branches 12916232 # Number of branches executed -system.cpu.iew.exec_stores 7364040 # Number of stores executed -system.cpu.iew.exec_rate 1.754258 # Inst execution rate -system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67789343 # num instructions producing a value -system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value +system.cpu.iew.exec_nop 10296358 # number of nop insts executed +system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076445 # Number of branches executed +system.cpu.iew.exec_stores 7081427 # Number of stores executed +system.cpu.iew.exec_rate 2.023822 # Inst execution rate +system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64608180 # num instructions producing a value +system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -304,64 +304,64 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180051805 # The number of ROB reads -system.cpu.rob.rob_writes 271380444 # The number of ROB writes -system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154514159 # The number of ROB reads +system.cpu.rob.rob_writes 236533126 # The number of ROB writes +system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 138495671 # number of integer regfile reads -system.cpu.int_regfile_writes 75435014 # number of integer regfile writes -system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes -system.cpu.misc_regfile_reads 715554 # number of misc regfile reads +system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129442497 # number of integer regfile reads +system.cpu.int_regfile_writes 70765525 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes +system.cpu.misc_regfile_reads 714278 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8695 # number of replacements -system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use -system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. +system.cpu.icache.replacements 10359 # number of replacements +system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use +system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits -system.cpu.icache.overall_hits::total 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses -system.cpu.icache.overall_misses::total 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits +system.cpu.icache.overall_hits::total 14929668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses +system.cpu.icache.overall_misses::total 13679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,258 +370,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use -system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use +system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits -system.cpu.dcache.overall_hits::total 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits +system.cpu.dcache.overall_hits::total 28184387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses -system.cpu.dcache.overall_misses::total 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9001 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9001 # number of overall misses +system.cpu.dcache.overall_misses::total 9001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289283500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289283500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21692285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21692285 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9270 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3617 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.562897 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.633584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2000.487710 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073251 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 56 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7655 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.697251 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2033.991651 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 377.801072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.062072 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011530 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.074142 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9204 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 9258 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7599 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 7680 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3029 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 459 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3488 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3029 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5194 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3029 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5194 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 103998000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15794500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 119792500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59244000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 59244000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 103998000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 75038500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179036500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 103998000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 75038500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179036500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 515 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9204 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 9284 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9204 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits +system.cpu.l2cache.overall_hits::total 9284 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3093 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3551 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1700 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1700 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3093 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2158 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5251 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3093 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2158 # number of overall misses +system.cpu.l2cache.overall_misses::total 5251 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106153500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15762000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 121915500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59022000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 59022000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 106153500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 74784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180937500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 106153500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 74784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180937500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12809 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.285002 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.891262 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.285002 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.285002 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14535 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12297 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index d10088405..8c858c201 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:37:09 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:58:01 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105850842000 because target called exit() +122 123 124 Exiting @ tick 88632152500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 98dddaff0..64cc4b80a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105851 # Number of seconds simulated -sim_ticks 105850842000 # Number of ticks simulated -final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.088632 # Number of seconds simulated +sim_ticks 88632152500 # Number of ticks simulated +final_tick 88632152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122767 # Simulator instruction rate (inst/s) -host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75414821 # Simulator tick rate (ticks/s) -host_mem_usage 227032 # Number of bytes of host memory used -host_seconds 1403.58 # Real time elapsed on the host -sim_insts 172314144 # Number of instructions simulated -sim_ops 188667627 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 239936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory +host_inst_rate 134694 # Simulator instruction rate (inst/s) +host_op_rate 147478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69281557 # Simulator tick rate (ticks/s) +host_mem_usage 227272 # Number of bytes of host memory used +host_seconds 1279.30 # Real time elapsed on the host +sim_insts 172315139 # Number of instructions simulated +sim_ops 188668622 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 244352 # Number of bytes read from this memory +system.physmem.bytes_inst_read 132032 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3749 # Number of read requests responded to by this memory +system.physmem.num_reads 3818 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2756923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1489663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2756923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211701685 # number of cpu cycles simulated +system.cpu.numCycles 177264306 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits +system.cpu.BPredUnit.lookups 96525090 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74749964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6668938 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46796658 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44215963 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4389679 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39966229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 381133369 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96525090 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48605642 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80754991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27412697 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35762422 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9389 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36758976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1679336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.350259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.058598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96615622 54.52% 54.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5430463 3.06% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10300720 5.81% 63.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10325695 5.83% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8756862 4.94% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6889395 3.89% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237128 3.52% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8634116 4.87% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24017231 13.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.544526 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.150085 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46183847 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34297054 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74780894 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20559231 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14846637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165269 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392589126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 748420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20559231 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52356007 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 443712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29007637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69958724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4881921 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 367191514 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 92621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2515930 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 627979317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1558602975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1541578337 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17024638 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298063528 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 329915789 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2303042 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2294526 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21773052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 41898813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 15562062 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3360389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2124393 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 324040554 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2103109 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 248819756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 576048 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 136002156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 346792965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 466892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 177207232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.404117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.633607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 78492090 44.29% 44.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 28577659 16.13% 60.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26660356 15.04% 75.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21359445 12.05% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12490578 7.05% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5763951 3.25% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3149996 1.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 544249 0.31% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 168908 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 177207232 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 627952 27.03% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5535 0.24% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1223626 52.68% 79.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 465789 20.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194916381 78.34% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 997256 0.40% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163976 0.07% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 252533 0.10% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76462 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 463893 0.19% 79.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206151 0.08% 79.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71843 0.03% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 37907135 15.23% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13730603 5.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued -system.cpu.iq.rate 1.236792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 248819756 # Type of FU issued +system.cpu.iq.rate 1.403665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2322951 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 674003670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460004017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 236904190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3742073 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2153997 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1836768 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 249257876 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1884831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1793335 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12046906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12587 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2915006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20559231 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11749 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 326199297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1048998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 41898813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 15562062 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2080622 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12587 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4245338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3938864 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8184202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 241936044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36336721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6883712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53452 # number of nop insts executed -system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed -system.cpu.iew.exec_branches 52584405 # Number of branches executed -system.cpu.iew.exec_stores 13597002 # Number of stores executed -system.cpu.iew.exec_rate 1.177158 # Inst execution rate -system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148512928 # num instructions producing a value -system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value +system.cpu.iew.exec_nop 55634 # number of nop insts executed +system.cpu.iew.exec_refs 49775211 # number of memory reference insts executed +system.cpu.iew.exec_branches 53836233 # Number of branches executed +system.cpu.iew.exec_stores 13438490 # Number of stores executed +system.cpu.iew.exec_rate 1.364832 # Inst execution rate +system.cpu.iew.wb_sent 239697329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 238740958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 143497606 # num instructions producing a value +system.cpu.iew.wb_consumers 250089451 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back +system.cpu.iew.wb_rate 1.346808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172329527 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188683010 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 137516300 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6533063 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 156648002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.204503 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.917568 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79778069 50.93% 50.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 37231664 23.77% 74.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15824405 10.10% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8489087 5.42% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4756905 3.04% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480671 0.95% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1767391 1.13% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258526 0.80% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6061284 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172328532 # Number of instructions committed -system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 156648002 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172329527 # Number of instructions committed +system.cpu.commit.committedOps 188683010 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498565 # Number of memory references committed -system.cpu.commit.loads 29851708 # Number of loads committed +system.cpu.commit.refs 42498963 # Number of memory references committed +system.cpu.commit.loads 29851907 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283906 # Number of branches committed +system.cpu.commit.branches 40284105 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115913 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6061284 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 519029825 # The number of ROB reads -system.cpu.rob.rob_writes 693007050 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172314144 # Number of Instructions Simulated -system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated -system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads -system.cpu.int_regfile_writes 407368356 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes -system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads -system.cpu.misc_regfile_writes 824482 # number of misc regfile writes -system.cpu.icache.replacements 1934 # number of replacements -system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use -system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 476780827 # The number of ROB reads +system.cpu.rob.rob_writes 673054212 # The number of ROB writes +system.cpu.timesIdled 1680 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172315139 # Number of Instructions Simulated +system.cpu.committedOps 188668622 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172315139 # Number of Instructions Simulated +system.cpu.cpi 1.028722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.028722 # CPI: Total CPI of All Threads +system.cpu.ipc 0.972080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.972080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1073592031 # number of integer regfile reads +system.cpu.int_regfile_writes 384645437 # number of integer regfile writes +system.cpu.fp_regfile_reads 2906196 # number of floating regfile reads +system.cpu.fp_regfile_writes 2487132 # number of floating regfile writes +system.cpu.misc_regfile_reads 464057527 # number of misc regfile reads +system.cpu.misc_regfile_writes 824880 # number of misc regfile writes +system.cpu.icache.replacements 2566 # number of replacements +system.cpu.icache.tagsinuse 1366.287383 # Cycle average of tags in use +system.cpu.icache.total_refs 36753975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4308 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8531.563370 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits -system.cpu.icache.overall_hits::total 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses -system.cpu.icache.overall_misses::total 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1366.287383 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.667133 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.667133 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36753975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36753975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36753975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36753975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36753975 # number of overall hits +system.cpu.icache.overall_hits::total 36753975 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5001 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5001 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5001 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5001 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5001 # number of overall misses +system.cpu.icache.overall_misses::total 5001 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108825000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108825000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108825000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108825000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36758976 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36758976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36758976 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36758976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21760.647870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,214 +380,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 692 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 692 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 692 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 692 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4309 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78064500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78064500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18116.616384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use -system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1415.234721 # Cycle average of tags in use +system.cpu.dcache.total_refs 46401176 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 24893.334764 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits -system.cpu.dcache.overall_hits::total 48591272 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1415.234721 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 33991693 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 33991693 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356758 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356758 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27891 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27891 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24829 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24829 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46348451 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46348451 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46348451 # number of overall hits +system.cpu.dcache.overall_hits::total 46348451 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7529 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7529 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9368 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9368 # number of overall misses -system.cpu.dcache.overall_misses::total 9368 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59529000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 237156500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 237156500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9312 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9312 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9312 # number of overall misses +system.cpu.dcache.overall_misses::total 9312 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58909500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58909500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 235574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 235574500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 294484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 294484000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 33993476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 33993476 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46357763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46357763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46357763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46357763 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000609 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000201 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000201 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 20 # number of writebacks +system.cpu.dcache.writebacks::total 20 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1009 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6438 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6438 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7447 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7447 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1846 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24707500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24707500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38314500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38314500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63022000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63022000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63022000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63022000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31921.834625 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35118.698442 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33791.957105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33791.957105 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1978.402021 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2325 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2747 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.846378 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.004344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1392.392495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 527.083774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 4.009293 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1435.553811 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 538.838917 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042492 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016085 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.058700 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1633 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 81 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1714 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1633 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 90 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1633 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 90 # number of overall hits -system.cpu.l2cache.overall_hits::total 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2007 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 674 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2681 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2007 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3763 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2007 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses -system.cpu.l2cache.overall_misses::total 3763 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68771500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23150500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 91922000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68771500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 60334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 129106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68771500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 60334500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 129106000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3640 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3640 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1846 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3640 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1846 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.551374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892715 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.551374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951246 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.551374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951246 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency +system.cpu.l2cache.occ_percent::cpu.inst 0.043810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016444 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.060376 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2242 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 82 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2324 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 20 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 20 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2242 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 92 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2334 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2242 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 92 # number of overall hits +system.cpu.l2cache.overall_hits::total 2334 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2066 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 692 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2758 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2066 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1772 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3838 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2066 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1772 # number of overall misses +system.cpu.l2cache.overall_misses::total 3838 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70811000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23716000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94527000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37109500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 37109500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 70811000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 60825500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131636500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 70811000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 60825500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131636500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4308 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 774 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5082 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 20 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 20 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6172 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.479573 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894057 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990826 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.479573 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950644 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.479573 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950644 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.443369 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34271.676301 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34360.648148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.443369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34325.902935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.443369 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34325.902935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,51 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2738 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3818 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64062500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85101000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54563000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118625500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54563000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118625500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 99b3e7f21..138f6116a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:02:46 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:27:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96266258000 because target called exit() +122 123 124 Exiting @ tick 87727531000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0aeabdea4..7c2d38b1f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096266 # Number of seconds simulated -sim_ticks 96266258000 # Number of ticks simulated -final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087728 # Number of seconds simulated +sim_ticks 87727531000 # Number of ticks simulated +final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89516 # Simulator instruction rate (inst/s) -host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65247901 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1475.39 # Real time elapsed on the host +host_inst_rate 101058 # Simulator instruction rate (inst/s) +host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67127344 # Simulator tick rate (ticks/s) +host_mem_usage 229892 # Number of bytes of host memory used +host_seconds 1306.88 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 339712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 345792 # Number of bytes read from this memory +system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5308 # Number of read requests responded to by this memory +system.physmem.num_reads 5403 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 192532517 # number of cpu cycles simulated +system.cpu.numCycles 175455063 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits +system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued -system.cpu.iq.rate 1.492196 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued +system.cpu.iq.rate 1.544606 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed -system.cpu.iew.exec_branches 15642768 # Number of branches executed -system.cpu.iew.exec_stores 24031199 # Number of stores executed -system.cpu.iew.exec_rate 1.472006 # Inst execution rate -system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227553614 # num instructions producing a value -system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value +system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed +system.cpu.iew.exec_branches 14784987 # Number of branches executed +system.cpu.iew.exec_stores 23115102 # Number of stores executed +system.cpu.iew.exec_rate 1.526907 # Inst execution rate +system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214539100 # num instructions producing a value +system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,64 +269,64 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 560089335 # The number of ROB reads -system.cpu.rob.rob_writes 814800236 # The number of ROB writes -system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498424236 # The number of ROB reads +system.cpu.rob.rob_writes 706514017 # The number of ROB writes +system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530367480 # number of integer regfile reads -system.cpu.int_regfile_writes 288604591 # number of integer regfile writes -system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads -system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes -system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads +system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511675262 # number of integer regfile reads +system.cpu.int_regfile_writes 274174484 # number of integer regfile writes +system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads +system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes +system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4205 # number of replacements -system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use -system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. +system.cpu.icache.replacements 5602 # number of replacements +system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use +system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits -system.cpu.icache.overall_hits::total 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses -system.cpu.icache.overall_misses::total 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits +system.cpu.icache.overall_hits::total 25817139 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses +system.cpu.icache.overall_misses::total 9097 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use -system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use +system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits -system.cpu.dcache.overall_hits::total 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses -system.cpu.dcache.overall_misses::total 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits +system.cpu.dcache.overall_hits::total 68659580 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1707 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses +system.cpu.dcache.overall_misses::total 2472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24609000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,119 +419,119 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 427 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1755 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 323 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1704 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1704 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14613500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14613500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 74151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74151500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 74151500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33062.217195 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34940.140845 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34553.355079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2496.824684 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2842 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.756858 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2591.074934 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4164 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3853 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.080716 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008695 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.076197 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2809 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2840 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.913608 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2287.446518 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 301.714808 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000058 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069807 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.009208 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.079073 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4132 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4162 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2809 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits -system.cpu.l2cache.overall_hits::total 2848 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3358 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 193 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 193 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3358 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1950 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3358 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1950 # number of overall misses -system.cpu.l2cache.overall_misses::total 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 115037500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13496000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 128533500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53066500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 53066500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 115037500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 66562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 181600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 115037500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 66562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 181600000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6167 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 426 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 4132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4170 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38 # number of overall hits +system.cpu.l2cache.overall_hits::total 4170 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3441 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 411 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3852 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 146 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 146 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1551 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1551 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3441 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5403 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3441 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses +system.cpu.l2cache.overall_misses::total 5403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117870000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14049500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131919500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52980000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 52980000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 117870000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 67029500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 184899500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 117870000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 67029500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 184899500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7573 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 441 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8014 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 193 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6167 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 146 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 146 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1559 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1559 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7573 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9573 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7573 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9573 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.454377 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.931973 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.544511 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.454377 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.981000 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.454377 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.981000 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,48 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5403 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106751500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119495000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 84e5e8c3f..499c6a74e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.physmem system.nvmem +memories=system.nvmem system.physmem midr_regval=890224640 num_work_ids=16 physmem=system.physmem @@ -93,6 +93,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu0.tracer width=1 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -107,20 +108,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -152,20 +146,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -220,6 +207,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu1.tracer width=1 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -234,20 +222,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -279,20 +260,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -344,20 +318,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -376,20 +343,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -415,7 +375,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -457,7 +416,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -467,7 +425,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -537,7 +494,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -549,7 +505,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -559,7 +514,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -588,7 +542,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -598,7 +551,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -608,7 +560,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -621,7 +572,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -635,7 +585,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -646,7 +595,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -665,7 +613,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -675,7 +622,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -684,7 +630,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -696,7 +641,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -706,7 +650,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -716,7 +659,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -726,7 +668,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -736,7 +677,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -750,7 +690,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -764,7 +703,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -787,7 +725,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -797,7 +734,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -807,7 +743,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -817,7 +752,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 614929bfc..04178bb32 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -1,11 +1,18 @@ -Traceback (most recent call last): - File "<string>", line 1, in <module> - File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main - exec filecode in scope - File "tests/run.py", line 70, in <module> - execfile(joinpath(tests_root, 'configs', test_filename + '.py')) - File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module> - system.l2c.num_cpus = 2 - File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__ - % (self.__class__.__name__, attr) -AttributeError: Class L2 has no parameter num_cpus +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: LCD dual screen mode not supported +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index d3606030f..24932a89c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,7 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:37:03 +gem5 compiled Feb 12 2012 23:53:51 +gem5 started Feb 12 2012 23:54:00 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2411694099500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index e69de29bb..6313260b7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -0,0 +1,571 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.411694 # Number of seconds simulated +sim_ticks 2411694099500 # Number of ticks simulated +final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2070187 # Simulator instruction rate (inst/s) +host_op_rate 2676186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81119350138 # Simulator tick rate (ticks/s) +host_mem_usage 376104 # Number of bytes of host memory used +host_seconds 29.73 # Real time elapsed on the host +sim_insts 61546998 # Number of instructions simulated +sim_ops 79563488 # Number of ops (including micro ops) simulated +system.nvmem.bytes_read 68 # Number of bytes read from this memory +system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory +system.nvmem.bytes_written 0 # Number of bytes written to this memory +system.nvmem.num_reads 17 # Number of read requests responded to by this memory +system.nvmem.num_writes 0 # Number of write requests responded to by this memory +system.nvmem.num_other 0 # Number of other requests responded to by this memory +system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s) +system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s) +system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read 123270308 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10185232 # Number of bytes written to this memory +system.physmem.num_reads 14146769 # Number of read requests responded to by this memory +system.physmem.num_writes 869038 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 127720 # number of replacements +system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use +system.l2c.total_refs 1498989 # Total number of references to valid blocks. +system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 14919.913596 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3116.154269 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1287.935030 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2080.961375 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4136.957345 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.047549 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.019652 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.031753 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.063125 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.389830 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 5051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2156 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 493019 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 368109 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 131706 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 580461 # number of Writeback hits +system.l2c.Writeback_hits::total 580461 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 147 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 202 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 64831 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 37797 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5051 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 493019 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 278002 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4123 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 368109 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 169503 # number of demand (read+write) hits +system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5051 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2156 # number of overall hits +system.l2c.overall_hits::cpu0.inst 493019 # number of overall hits +system.l2c.overall_hits::cpu0.data 278002 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4123 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1590 # number of overall hits +system.l2c.overall_hits::cpu1.inst 368109 # number of overall hits +system.l2c.overall_hits::cpu1.data 169503 # number of overall hits +system.l2c.overall_hits::total 1321553 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10289 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9386 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5094 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 10130 # number of ReadReq misses +system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 6349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3492 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 791 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 531 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99048 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 48785 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 108434 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5094 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 58915 # number of demand (read+write) misses +system.l2c.demand_misses::total 182784 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10289 # number of overall misses +system.l2c.overall_misses::cpu0.data 108434 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5094 # number of overall misses +system.l2c.overall_misses::cpu1.data 58915 # number of overall misses +system.l2c.overall_misses::total 182784 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5062 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2163 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 503308 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 222557 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1603 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 373203 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 141836 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 580461 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 7125 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4015 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 733 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 163879 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 86582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5062 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2163 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 503308 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 386436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4144 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1603 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 373203 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 228418 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5062 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2163 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 503308 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 386436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4144 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1603 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 373203 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 228418 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003236 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020443 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.042173 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.008110 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.013649 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071421 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.891088 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.869738 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843284 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724420 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.604397 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.563454 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.003236 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020443 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.280600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.008110 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.013649 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.257926 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.003236 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020443 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.280600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.008110 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.013649 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.257926 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 111818 # number of writebacks +system.l2c.writebacks::total 111818 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 9339288 # DTB read hits +system.cpu0.dtb.read_misses 5153 # DTB read misses +system.cpu0.dtb.write_hits 6907876 # DTB write hits +system.cpu0.dtb.write_misses 1048 # DTB write misses +system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9344441 # DTB read accesses +system.cpu0.dtb.write_accesses 6908924 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 16247164 # DTB hits +system.cpu0.dtb.misses 6201 # DTB misses +system.cpu0.dtb.accesses 16253365 # DTB accesses +system.cpu0.itb.inst_hits 34822552 # ITB inst hits +system.cpu0.itb.inst_misses 2978 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses +system.cpu0.itb.hits 34822552 # DTB hits +system.cpu0.itb.misses 2978 # DTB misses +system.cpu0.itb.accesses 34825530 # DTB accesses +system.cpu0.numCycles 4823340800 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 34068103 # Number of instructions committed +system.cpu0.committedOps 44975797 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses +system.cpu0.num_func_calls 1311755 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39858123 # number of integer instructions +system.cpu0.num_fp_insts 4945 # number of float instructions +system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written +system.cpu0.num_mem_refs 17030946 # number of memory refs +system.cpu0.num_load_insts 9786549 # Number of load instructions +system.cpu0.num_store_insts 7244397 # Number of store instructions +system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles +system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles +system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed +system.cpu0.icache.replacements 504460 # number of replacements +system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use +system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 34319155 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34319155 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34319155 # number of overall hits +system.cpu0.icache.overall_hits::total 34319155 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses +system.cpu0.icache.overall_misses::total 504973 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 34824128 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 34824128 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 24728 # number of writebacks +system.cpu0.icache.writebacks::total 24728 # number of writebacks +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 380107 # number of replacements +system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7803296 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6534059 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 14337355 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14337355 # number of overall hits +system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 237350 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9878 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7293 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 420930 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 420930 # number of overall misses +system.cpu0.dcache.overall_misses::total 420930 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040646 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717639 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14758285 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14758285 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040036 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028522 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028522 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 339627 # number of writebacks +system.cpu0.dcache.writebacks::total 339627 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 6258230 # DTB read hits +system.cpu1.dtb.read_misses 2159 # DTB read misses +system.cpu1.dtb.write_hits 4713962 # DTB write hits +system.cpu1.dtb.write_misses 1181 # DTB write misses +system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6260389 # DTB read accesses +system.cpu1.dtb.write_accesses 4715143 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 10972192 # DTB hits +system.cpu1.dtb.misses 3340 # DTB misses +system.cpu1.dtb.accesses 10975532 # DTB accesses +system.cpu1.itb.inst_hits 27739434 # ITB inst hits +system.cpu1.itb.inst_misses 1388 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses +system.cpu1.itb.hits 27739434 # DTB hits +system.cpu1.itb.misses 1388 # DTB misses +system.cpu1.itb.accesses 27740822 # DTB accesses +system.cpu1.numCycles 4822838236 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 27478895 # Number of instructions committed +system.cpu1.committedOps 34587691 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses +system.cpu1.num_func_calls 758024 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30998246 # number of integer instructions +system.cpu1.num_fp_insts 5772 # number of float instructions +system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read +system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written +system.cpu1.num_mem_refs 11415835 # number of memory refs +system.cpu1.num_load_insts 6478994 # Number of load instructions +system.cpu1.num_store_insts 4936841 # Number of store instructions +system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles +system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles +system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed +system.cpu1.icache.replacements 374406 # number of replacements +system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use +system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 27365572 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 27365572 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 27365572 # number of overall hits +system.cpu1.icache.overall_hits::total 27365572 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 374920 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 374920 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 374920 # number of overall misses +system.cpu1.icache.overall_misses::total 374920 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27740492 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27740492 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks +system.cpu1.icache.writebacks::total 13905 # number of writebacks +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 247434 # number of replacements +system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 444.903488 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.868952 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 5955973 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3777038 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60090 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9733011 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9733011 # number of overall hits +system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 165799 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 277266 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 277266 # number of overall misses +system.cpu1.dcache.overall_misses::total 277266 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121772 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888505 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 70318 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70288 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10010277 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10010277 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027083 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027698 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027698 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 202201 # number of writebacks +system.cpu1.dcache.writebacks::total 202201 # number of writebacks +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ff8d4bf12..89a25c4c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21216000 because target called exit() +Exiting @ tick 21234500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index fc30a21c8..fdd02b36e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21216000 # Number of ticks simulated -final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21234500 # Number of ticks simulated +final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38129 # Simulator instruction rate (inst/s) -host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126288909 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 95244 # Simulator instruction rate (inst/s) +host_op_rate 95219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 315647941 # Simulator tick rate (ticks/s) +host_mem_usage 209384 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 469 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 929 # ITB hits +system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 946 # ITB accesses +system.cpu.itb.fetch_accesses 925 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42433 # number of cpu cycles simulated +system.cpu.numCycles 42470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. -system.cpu.activity 17.399194 # Percentage of cycles cpu is active +system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. +system.cpu.activity 17.402873 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1670 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1608 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2138 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2183 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. +system.cpu.execution_unit.executions 4474 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use -system.cpu.icache.total_refs 581 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits -system.cpu.icache.overall_hits::total 581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,40 +168,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 347 # n system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -238,10 +238,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,34 +266,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -311,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -340,13 +340,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,16 +367,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -385,12 +385,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 684d7e9b2..16153e12a 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12004500 because target called exit() +Exiting @ tick 12450500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 49671266a..bfc4cc915 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12004500 # Number of ticks simulated -final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12450500 # Number of ticks simulated +final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42281 # Simulator instruction rate (inst/s) -host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79460110 # Simulator tick rate (ticks/s) -host_mem_usage 210060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 87465 # Simulator instruction rate (inst/s) +host_op_rate 87444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170447462 # Simulator tick rate (ticks/s) +host_mem_usage 210080 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_read 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 485 # Number of read requests responded to by this memory +system.physmem.num_reads 490 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1860 # DTB read hits -system.cpu.dtb.read_misses 44 # DTB read misses +system.cpu.dtb.read_hits 1943 # DTB read hits +system.cpu.dtb.read_misses 53 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1904 # DTB read accesses -system.cpu.dtb.write_hits 1041 # DTB write hits -system.cpu.dtb.write_misses 28 # DTB write misses +system.cpu.dtb.read_accesses 1996 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1069 # DTB write accesses -system.cpu.dtb.data_hits 2901 # DTB hits -system.cpu.dtb.data_misses 72 # DTB misses +system.cpu.dtb.write_accesses 1103 # DTB write accesses +system.cpu.dtb.data_hits 3014 # DTB hits +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2973 # DTB accesses -system.cpu.itb.fetch_hits 2039 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses +system.cpu.dtb.data_accesses 3099 # DTB accesses +system.cpu.itb.fetch_hits 2367 # ITB hits +system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2068 # ITB accesses +system.cpu.itb.fetch_accesses 2393 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,246 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24010 # number of cpu cycles simulated +system.cpu.numCycles 24902 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2507 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2318 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2587 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9757 # Type of FU issued -system.cpu.iq.rate 0.406372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10522 # Type of FU issued +system.cpu.iq.rate 0.422536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2985 # number of memory reference insts executed -system.cpu.iew.exec_branches 1504 # Number of branches executed -system.cpu.iew.exec_stores 1071 # Number of stores executed -system.cpu.iew.exec_rate 0.387880 # Inst execution rate -system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4719 # num instructions producing a value -system.cpu.iew.wb_consumers 6404 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 3117 # number of memory reference insts executed +system.cpu.iew.exec_branches 1605 # Number of branches executed +system.cpu.iew.exec_stores 1108 # Number of stores executed +system.cpu.iew.exec_rate 0.396675 # Inst execution rate +system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4957 # num instructions producing a value +system.cpu.iew.wb_consumers 6732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back +system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -303,64 +303,64 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22763 # The number of ROB reads -system.cpu.rob.rob_writes 24313 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24667 # The number of ROB reads +system.cpu.rob.rob_writes 26868 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11830 # number of integer regfile reads -system.cpu.int_regfile_writes 6732 # number of integer regfile writes +system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads +system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12526 # number of integer regfile reads +system.cpu.int_regfile_writes 7116 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use -system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use +system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits -system.cpu.icache.overall_hits::total 1606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses -system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits +system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses +system.cpu.icache.overall_misses::total 458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,80 +369,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use -system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use +system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits -system.cpu.dcache.overall_hits::total 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits +system.cpu.dcache.overall_hits::total 2244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,103 +451,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10665000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3498000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6011500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses +system.cpu.l2cache.overall_misses::total 490 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,42 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 6aed6d3ac..eb202613d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:23 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6833000 because target called exit() +Exiting @ tick 7015000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d93b581f0..686010297 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6833000 # Number of ticks simulated -final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7015000 # Number of ticks simulated +final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16400 # Simulator instruction rate (inst/s) -host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46934615 # Simulator tick rate (ticks/s) -host_mem_usage 209144 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73930 # Simulator instruction rate (inst/s) +host_op_rate 73884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 217009042 # Simulator tick rate (ticks/s) +host_mem_usage 209140 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17280 # Number of bytes read from this memory -system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory +system.physmem.bytes_read 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 270 # Number of read requests responded to by this memory +system.physmem.num_reads 275 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 679 # DTB read hits -system.cpu.dtb.read_misses 26 # DTB read misses +system.cpu.dtb.read_hits 711 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 705 # DTB read accesses -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 380 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 374 # DTB write accesses -system.cpu.dtb.data_hits 1035 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 403 # DTB write accesses +system.cpu.dtb.data_hits 1091 # DTB hits +system.cpu.dtb.data_misses 66 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 941 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 1157 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 971 # ITB accesses +system.cpu.itb.fetch_accesses 1100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,245 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13667 # number of cpu cycles simulated +system.cpu.numCycles 14031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1201 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1081 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 995 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups +system.cpu.rename.RunCycles 1115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle +system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3881 # Type of FU issued -system.cpu.iq.rate 0.283969 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4206 # Type of FU issued +system.cpu.iq.rate 0.299765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1080 # number of memory reference insts executed -system.cpu.iew.exec_branches 629 # Number of branches executed -system.cpu.iew.exec_stores 374 # Number of stores executed -system.cpu.iew.exec_rate 0.274310 # Inst execution rate -system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1702 # num instructions producing a value -system.cpu.iew.wb_consumers 2165 # num instructions consuming a value +system.cpu.iew.exec_nop 368 # number of nop insts executed +system.cpu.iew.exec_refs 1160 # number of memory reference insts executed +system.cpu.iew.exec_branches 681 # Number of branches executed +system.cpu.iew.exec_stores 403 # Number of stores executed +system.cpu.iew.exec_rate 0.285439 # Inst execution rate +system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1793 # num instructions producing a value +system.cpu.iew.wb_consumers 2339 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -302,63 +303,63 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10645 # The number of ROB reads -system.cpu.rob.rob_writes 10410 # The number of ROB writes -system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11567 # The number of ROB reads +system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4520 # number of integer regfile reads -system.cpu.int_regfile_writes 2768 # number of integer regfile writes +system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4832 # number of integer regfile reads +system.cpu.int_regfile_writes 2958 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use +system.cpu.icache.total_refs 817 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits -system.cpu.icache.overall_hits::total 700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits +system.cpu.icache.overall_hits::total 817 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,80 +368,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use -system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use +system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits -system.cpu.dcache.overall_hits::total 765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits +system.cpu.dcache.overall_hits::total 793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.dcache.overall_misses::total 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6421500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6421500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 644 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses +system.cpu.dcache.overall_misses::total 179 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,83 +450,83 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094720 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 246 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 185 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 185 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6346000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2101500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6346000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6346000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses +system.cpu.l2cache.overall_misses::total 275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses @@ -533,13 +534,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,28 +549,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -577,13 +578,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index ab1ef55e9..e7e46b503 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:35:50 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 19:57:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10000500 because target called exit() +Exiting @ tick 10389500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 010933949..6eeb02481 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10000500 # Number of ticks simulated -final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10389500 # Number of ticks simulated +final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72927 # Simulator instruction rate (inst/s) -host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158457261 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 66059 # Simulator instruction rate (inst/s) +host_op_rate 82394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149123755 # Simulator tick rate (ticks/s) +host_mem_usage 221320 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25856 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 404 # Number of read requests responded to by this memory +system.physmem.num_reads 400 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,245 +63,246 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20002 # number of cpu cycles simulated +system.cpu.numCycles 20780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2398 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits +system.cpu.BPredUnit.lookups 2550 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2634 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8706 # Type of FU issued -system.cpu.iq.rate 0.435256 # Inst issue rate -system.cpu.iq.fu_busy_cnt 203 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9138 # Type of FU issued +system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.414059 # Inst execution rate -system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7840 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3690 # num instructions producing a value -system.cpu.iew.wb_consumers 7291 # num instructions consuming a value +system.cpu.iew.exec_refs 3325 # number of memory reference insts executed +system.cpu.iew.exec_branches 1404 # Number of branches executed +system.cpu.iew.exec_stores 1195 # Number of stores executed +system.cpu.iew.exec_rate 0.415544 # Inst execution rate +system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3863 # num instructions producing a value +system.cpu.iew.wb_consumers 7813 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -312,63 +313,63 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21205 # The number of ROB reads -system.cpu.rob.rob_writes 22566 # The number of ROB writes -system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22664 # The number of ROB reads +system.cpu.rob.rob_writes 24737 # The number of ROB writes +system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads -system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 37816 # number of integer regfile reads -system.cpu.int_regfile_writes 7658 # number of integer regfile writes +system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads +system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39570 # number of integer regfile reads +system.cpu.int_regfile_writes 8020 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 14992 # number of misc regfile reads +system.cpu.misc_regfile_reads 16023 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use -system.cpu.icache.total_refs 1559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use +system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits -system.cpu.icache.overall_hits::total 1559 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits +system.cpu.icache.overall_hits::total 1663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,94 +378,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use +system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits -system.cpu.dcache.overall_hits::total 2311 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses -system.cpu.dcache.overall_misses::total 473 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16075500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16075500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,108 +474,108 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits -system.cpu.l2cache.overall_hits::total 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses -system.cpu.l2cache.overall_misses::total 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses +system.cpu.l2cache.overall_misses::total 404 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,48 +584,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 9f59be0ce..e34fa5006 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:30 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:47 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19785000 because target called exit() +Exiting @ tick 19775000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6cd55fbff..e8bd2f84c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19785000 # Number of ticks simulated -final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19775000 # Number of ticks simulated +final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101976 # Simulator instruction rate (inst/s) -host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 346042004 # Simulator tick rate (ticks/s) -host_mem_usage 210372 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 108846 # Simulator instruction rate (inst/s) +host_op_rate 108810 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 369151681 # Simulator tick rate (ticks/s) +host_mem_usage 210376 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 455 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,16 +39,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39571 # number of cpu cycles simulated +system.cpu.numCycles 39551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. -system.cpu.activity 13.658993 # Percentage of cycles cpu is active +system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. +system.cpu.activity 13.572350 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -60,92 +60,92 @@ system.cpu.committedInsts 5827 # Nu system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits +system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1152 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2228 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2238 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 320 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.065502 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3155 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use -system.cpu.icache.total_refs 443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use +system.cpu.icache.total_refs 411 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits -system.cpu.icache.overall_hits::total 443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses -system.cpu.icache.overall_misses::total 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits +system.cpu.icache.overall_hits::total 411 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses +system.cpu.icache.overall_misses::total 343 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -154,40 +154,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits @@ -206,12 +206,12 @@ system.cpu.dcache.overall_misses::cpu.data 251 # system.cpu.dcache.overall_misses::total 251 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -225,9 +225,9 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,32 +254,32 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -297,17 +297,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -326,13 +326,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index afa267678..e545392ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:39 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:57 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12272500 because target called exit() +Exiting @ tick 12671500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 9ff42644b..f9bef2483 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12272500 # Number of ticks simulated -final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12671500 # Number of ticks simulated +final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97350 # Simulator instruction rate (inst/s) -host_op_rate 97317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230983195 # Simulator tick rate (ticks/s) -host_mem_usage 211060 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 93816 # Simulator instruction rate (inst/s) +host_op_rate 93786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229841550 # Simulator tick rate (ticks/s) +host_mem_usage 211032 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory +system.physmem.bytes_read 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 475 # Number of read requests responded to by this memory +system.physmem.num_reads 483 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24546 # number of cpu cycles simulated +system.cpu.numCycles 25344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1975 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits +system.cpu.BPredUnit.lookups 2242 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered +system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2857 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2966 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7815 # Type of FU issued -system.cpu.iq.rate 0.318382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8177 # Type of FU issued +system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1378 # number of nop insts executed -system.cpu.iew.exec_refs 3087 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1059 # Number of stores executed -system.cpu.iew.exec_rate 0.306812 # Inst execution rate -system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7118 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2758 # num instructions producing a value -system.cpu.iew.wb_consumers 3946 # num instructions consuming a value +system.cpu.iew.exec_nop 1464 # number of nop insts executed +system.cpu.iew.exec_refs 3166 # number of memory reference insts executed +system.cpu.iew.exec_branches 1317 # Number of branches executed +system.cpu.iew.exec_stores 1061 # Number of stores executed +system.cpu.iew.exec_rate 0.306305 # Inst execution rate +system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7307 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2841 # num instructions producing a value +system.cpu.iew.wb_consumers 4060 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,63 +288,63 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21779 # The number of ROB reads -system.cpu.rob.rob_writes 20794 # The number of ROB writes +system.cpu.rob.rob_reads 22904 # The number of ROB reads +system.cpu.rob.rob_writes 22029 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10280 # number of integer regfile reads -system.cpu.int_regfile_writes 4987 # number of integer regfile writes +system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads +system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10565 # number of integer regfile reads +system.cpu.int_regfile_writes 5131 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use -system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 151 # number of misc regfile reads +system.cpu.icache.replacements 19 # number of replacements +system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits -system.cpu.icache.overall_hits::total 1363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses -system.cpu.icache.overall_misses::total 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses +system.cpu.icache.overall_misses::total 447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,80 +353,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use -system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use +system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits -system.cpu.dcache.overall_hits::total 2380 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits +system.cpu.dcache.overall_hits::total 2472 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses +system.cpu.dcache.overall_misses::total 472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -437,12 +437,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -451,87 +451,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.434563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.087393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 333 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 424 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 333 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 333 # number of overall misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11418500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,42 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 8e7d01159..a3c2e1876 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:55 -gem5 started Feb 11 2012 13:55:01 +gem5 compiled Feb 12 2012 17:17:52 +gem5 started Feb 12 2012 18:17:19 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10910500 because target called exit() +Exiting @ tick 11243500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 7c789f568..e78f47ce4 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10910500 # Number of ticks simulated -final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11243500 # Number of ticks simulated +final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114395 # Simulator instruction rate (inst/s) -host_op_rate 114354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215042277 # Simulator tick rate (ticks/s) -host_mem_usage 207892 # Number of bytes of host memory used +host_inst_rate 108078 # Simulator instruction rate (inst/s) +host_op_rate 108043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209380098 # Simulator tick rate (ticks/s) +host_mem_usage 207884 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 447 # Number of read requests responded to by this memory +system.physmem.num_reads 449 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2622061317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2017872691 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2622061317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 21822 # number of cpu cycles simulated +system.cpu.numCycles 22488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2297 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits +system.cpu.BPredUnit.lookups 2514 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2045 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1920 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8536 # Type of FU issued -system.cpu.iq.rate 0.391165 # Inst issue rate -system.cpu.iq.fu_busy_cnt 154 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 9284 # Type of FU issued +system.cpu.iq.rate 0.412842 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_branches 1313 # Number of branches executed -system.cpu.iew.exec_stores 1341 # Number of stores executed -system.cpu.iew.exec_rate 0.374393 # Inst execution rate -system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7879 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4173 # num instructions producing a value -system.cpu.iew.wb_consumers 6691 # num instructions consuming a value +system.cpu.iew.exec_refs 3258 # number of memory reference insts executed +system.cpu.iew.exec_branches 1391 # Number of branches executed +system.cpu.iew.exec_stores 1554 # Number of stores executed +system.cpu.iew.exec_rate 0.389274 # Inst execution rate +system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4351 # num instructions producing a value +system.cpu.iew.wb_consumers 7020 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back +system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,62 +288,62 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 19701 # The number of ROB reads -system.cpu.rob.rob_writes 20673 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21145 # The number of ROB reads +system.cpu.rob.rob_writes 22688 # The number of ROB writes +system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12979 # number of integer regfile reads -system.cpu.int_regfile_writes 6957 # number of integer regfile writes -system.cpu.fp_regfile_reads 28 # number of floating regfile reads +system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads +system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13921 # number of integer regfile reads +system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use -system.cpu.icache.total_refs 1291 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits -system.cpu.icache.overall_hits::total 1291 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses -system.cpu.icache.overall_misses::total 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,80 +352,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12207500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12207500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 355 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use -system.cpu.dcache.total_refs 2156 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use +system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 66.296919 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1428 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 728 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 728 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits -system.cpu.dcache.overall_hits::total 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 88 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 88 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 406 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 406 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 406 # number of overall misses -system.cpu.dcache.overall_misses::total 406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2947000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2947000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10802500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10802500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits +system.cpu.dcache.overall_hits::total 2216 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses +system.cpu.dcache.overall_misses::total 399 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304015 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158470 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,106 +434,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 31 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3714500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3714500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34447.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 168.132824 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.480228 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005131 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000991 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 9 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 9 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits +system.cpu.l2cache.overall_hits::total 5 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 103 # number of overall misses -system.cpu.l2cache.overall_misses::total 447 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1895500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1678500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1678500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11818500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3574000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15392500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11818500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 57 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses +system.cpu.l2cache.overall_misses::total 449 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980057 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964912 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980057 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980057 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,42 +539,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 13c85267e..cf9740828 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:30 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18201500 because target called exit() +Hello World!Exiting @ tick 18196500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 99d0ed042..440f0bc0a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18201500 # Number of ticks simulated -final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18196500 # Number of ticks simulated +final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71915 # Simulator instruction rate (inst/s) -host_op_rate 71898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245008016 # Simulator tick rate (ticks/s) -host_mem_usage 211144 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 90140 # Simulator instruction rate (inst/s) +host_op_rate 90112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 306976844 # Simulator tick rate (ticks/s) +host_mem_usage 211148 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory @@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 423 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36404 # number of cpu cycles simulated +system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6274 # Number of cycles cpu stages are processed. -system.cpu.activity 17.234370 # Percentage of cycles cpu is active +system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 17.109963 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -42,98 +42,98 @@ system.cpu.committedInsts 5340 # Nu system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1662 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted +system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1617 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1473 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1487 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3977 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3979 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use -system.cpu.icache.total_refs 791 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use +system.cpu.icache.total_refs 827 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits -system.cpu.icache.overall_hits::total 791 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits +system.cpu.icache.overall_hits::total 827 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses system.cpu.icache.overall_misses::total 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits @@ -148,28 +148,28 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits @@ -186,14 +186,14 @@ system.cpu.dcache.demand_misses::cpu.data 340 # n system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses system.cpu.dcache.overall_misses::total 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -206,10 +206,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -234,31 +234,31 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy @@ -282,17 +282,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -311,13 +311,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ac1cd3610..eda7f85a5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:04:05 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:26:23 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11989500 because target called exit() +Exiting @ tick 12299500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 658a056fb..475f993c2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11989500 # Number of ticks simulated -final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12299500 # Number of ticks simulated +final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61798 # Simulator instruction rate (inst/s) -host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136747555 # Simulator tick rate (ticks/s) -host_mem_usage 218292 # Number of bytes of host memory used +host_inst_rate 59298 # Simulator instruction rate (inst/s) +host_op_rate 107375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134612595 # Simulator tick rate (ticks/s) +host_mem_usage 218308 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28288 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 442 # Number of read requests responded to by this memory +system.physmem.num_reads 451 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 23980 # number of cpu cycles simulated +system.cpu.numCycles 24600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits +system.cpu.BPredUnit.lookups 3225 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3508 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3795 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle +system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16792 # Type of FU issued -system.cpu.iq.rate 0.700250 # Inst issue rate -system.cpu.iq.fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17955 # Type of FU issued +system.cpu.iq.rate 0.729878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3065 # number of memory reference insts executed -system.cpu.iew.exec_branches 1589 # Number of branches executed -system.cpu.iew.exec_stores 1340 # Number of stores executed -system.cpu.iew.exec_rate 0.664804 # Inst execution rate -system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10251 # num instructions producing a value -system.cpu.iew.wb_consumers 15131 # num instructions consuming a value +system.cpu.iew.exec_refs 3212 # number of memory reference insts executed +system.cpu.iew.exec_branches 1649 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.686504 # Inst execution rate +system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10670 # num instructions producing a value +system.cpu.iew.wb_consumers 15796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back +system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,62 +269,62 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 34653 # The number of ROB reads -system.cpu.rob.rob_writes 42403 # The number of ROB writes +system.cpu.rob.rob_reads 36584 # The number of ROB reads +system.cpu.rob.rob_writes 45550 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads -system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23430 # number of integer regfile reads -system.cpu.int_regfile_writes 14518 # number of integer regfile writes +system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24791 # number of integer regfile reads +system.cpu.int_regfile_writes 15157 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.misc_regfile_reads 7406 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use -system.cpu.icache.total_refs 1498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use +system.cpu.icache.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits -system.cpu.icache.overall_hits::total 1498 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 392 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 392 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 392 # number of overall misses +system.cpu.icache.overall_misses::total 392 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13905000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13905000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13905000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13905000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199187 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199187 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,80 +333,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10684500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10684500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.091432 # Cycle average of tags in use +system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.091432 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits -system.cpu.dcache.overall_hits::total 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits +system.cpu.dcache.overall_hits::total 2365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses -system.cpu.dcache.overall_misses::total 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4056500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4056500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1624 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2462 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2462 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2462 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2558 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2558 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2558 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2558 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.075450 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075450 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,101 +415,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044951 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35232.876712 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 180.810821 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.468506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.341218 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001017 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005304 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 146.260836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.549985 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004464 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005518 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 296 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 296 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12541000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4986000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10158000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4986000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15144000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 10365500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15455000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10365500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15455000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 444 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993289 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,42 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4535500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13737500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9393500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2262000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 4edc89b33..2e652c55a 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:14 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13202000 because target called exit() +Exiting @ tick 13973500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 292756fa3..f99bdda93 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13202000 # Number of ticks simulated -final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13973500 # Number of ticks simulated +final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91406 # Simulator instruction rate (inst/s) -host_op_rate 91394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94452628 # Simulator tick rate (ticks/s) -host_mem_usage 210624 # Number of bytes of host memory used +host_inst_rate 94205 # Simulator instruction rate (inst/s) +host_op_rate 94192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103032063 # Simulator tick rate (ticks/s) +host_mem_usage 210576 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_read 62784 # Number of bytes read from this memory +system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 971 # Number of read requests responded to by this memory +system.physmem.num_reads 981 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4707165581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 3024996213 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4707165581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 3722 # DTB read hits -system.cpu.dtb.read_misses 94 # DTB read misses +system.cpu.dtb.read_hits 4112 # DTB read hits +system.cpu.dtb.read_misses 99 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 3816 # DTB read accesses -system.cpu.dtb.write_hits 1984 # DTB write hits -system.cpu.dtb.write_misses 61 # DTB write misses +system.cpu.dtb.read_accesses 4211 # DTB read accesses +system.cpu.dtb.write_hits 2113 # DTB write hits +system.cpu.dtb.write_misses 55 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2045 # DTB write accesses -system.cpu.dtb.data_hits 5706 # DTB hits -system.cpu.dtb.data_misses 155 # DTB misses +system.cpu.dtb.write_accesses 2168 # DTB write accesses +system.cpu.dtb.data_hits 6225 # DTB hits +system.cpu.dtb.data_misses 154 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 5861 # DTB accesses -system.cpu.itb.fetch_hits 4091 # ITB hits -system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.dtb.data_accesses 6379 # DTB accesses +system.cpu.itb.fetch_hits 5262 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 4147 # ITB accesses +system.cpu.itb.fetch_accesses 5308 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,360 +54,361 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 26405 # number of cpu cycles simulated +system.cpu.numCycles 27948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5174 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits +system.cpu.BPredUnit.lookups 6404 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4328 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4136 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5207 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4929 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 52 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9747 # Type of FU issued +system.cpu.iq.FU_type_0::total 10965 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9688 # Type of FU issued +system.cpu.iq.FU_type_1::total 10832 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 19435 # Type of FU issued -system.cpu.iq.rate 0.736035 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21797 # Type of FU issued +system.cpu.iq.rate 0.779913 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 75 # number of nop insts executed -system.cpu.iew.exec_nop::1 65 # number of nop insts executed -system.cpu.iew.exec_nop::total 140 # number of nop insts executed -system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1521 # Number of branches executed -system.cpu.iew.exec_branches::1 1526 # Number of branches executed -system.cpu.iew.exec_branches::total 3047 # Number of branches executed -system.cpu.iew.exec_stores::0 1031 # Number of stores executed -system.cpu.iew.exec_stores::1 1027 # Number of stores executed -system.cpu.iew.exec_stores::total 2058 # Number of stores executed -system.cpu.iew.exec_rate 0.697785 # Inst execution rate -system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4555 # num instructions producing a value -system.cpu.iew.wb_producers::1 4549 # num instructions producing a value -system.cpu.iew.wb_producers::total 9104 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value +system.cpu.iew.exec_nop::0 72 # number of nop insts executed +system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::total 141 # number of nop insts executed +system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1640 # Number of branches executed +system.cpu.iew.exec_branches::1 1645 # Number of branches executed +system.cpu.iew.exec_branches::total 3285 # Number of branches executed +system.cpu.iew.exec_stores::0 1099 # Number of stores executed +system.cpu.iew.exec_stores::1 1088 # Number of stores executed +system.cpu.iew.exec_stores::total 2187 # Number of stores executed +system.cpu.iew.exec_rate 0.725276 # Inst execution rate +system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5068 # num instructions producing a value +system.cpu.iew.wb_producers::1 5042 # num instructions producing a value +system.cpu.iew.wb_producers::total 10110 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 232 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6403 # Number of instructions committed system.cpu.commit.committedInsts::1 6404 # Number of instructions committed system.cpu.commit.committedInsts::total 12807 # Number of instructions committed @@ -438,72 +439,72 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 101307 # The number of ROB reads -system.cpu.rob.rob_writes 46689 # The number of ROB writes -system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 114163 # The number of ROB reads +system.cpu.rob.rob_writes 54209 # The number of ROB writes +system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23374 # number of integer regfile reads -system.cpu.int_regfile_writes 13316 # number of integer regfile writes +system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25651 # number of integer regfile reads +system.cpu.int_regfile_writes 14680 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::0 7 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use -system.cpu.icache.total_refs 3236 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 7 # number of replacements +system.cpu.icache.tagsinuse 324.653687 # Cycle average of tags in use +system.cpu.icache.total_refs 4369 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 631 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.923930 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits -system.cpu.icache.overall_hits::total 3236 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses -system.cpu.icache.overall_misses::total 855 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 324.653687 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.158522 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.158522 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4369 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4369 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4369 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4369 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4369 # number of overall hits +system.cpu.icache.overall_hits::total 4369 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 893 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 893 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 893 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 893 # number of overall misses +system.cpu.icache.overall_misses::total 893 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31736000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31736000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31736000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31736000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31736000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31736000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5262 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5262 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5262 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5262 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,82 +513,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 262 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 262 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 631 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 631 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 631 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22442500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22442500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22442500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22442500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use -system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.504894 # Cycle average of tags in use +system.cpu.dcache.total_refs 4696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.303116 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 216.133399 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3303 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3303 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 221.504894 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.054078 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.054078 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3676 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3676 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4323 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4323 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4323 # number of overall hits -system.cpu.dcache.overall_hits::total 4323 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 308 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 308 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4696 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4696 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4696 # number of overall hits +system.cpu.dcache.overall_hits::total 4696 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 311 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 311 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses -system.cpu.dcache.overall_misses::total 1018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11179500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24106500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35286000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses +system.cpu.dcache.overall_misses::total 1021 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11221000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11221000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22533500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22533500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33754500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33754500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33754500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33754500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3987 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3987 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5341 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085295 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5717 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5717 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,105 +597,105 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 107 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 207 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7607500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7607500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5291500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5291500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12899000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12899000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 449.601344 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 324.972112 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 124.629233 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003803 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013721 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 628 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 207 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses -system.cpu.l2cache.overall_misses::total 971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 628 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 353 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 981 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 628 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 353 # number of overall misses +system.cpu.l2cache.overall_misses::total 981 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21636000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5063500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5063500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21636000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33915500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21636000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 207 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 631 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 353 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 631 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 353 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -703,42 +704,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6570000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26229500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4611000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4611000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11181000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30840500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 71793d455..0e8b3f2e0 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:34 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:51 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25058500 because target called exit() +Exiting @ tick 25007500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index f7efdf641..a378be567 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25058500 # Number of ticks simulated -final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25007500 # Number of ticks simulated +final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93467 # Simulator instruction rate (inst/s) -host_op_rate 93457 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154309649 # Simulator tick rate (ticks/s) -host_mem_usage 211048 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 100667 # Simulator instruction rate (inst/s) +host_op_rate 100655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165855291 # Simulator tick rate (ticks/s) +host_mem_usage 211052 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27904 # Number of bytes read from this memory @@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 436 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1113554283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 761099028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1113554283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50118 # number of cpu cycles simulated +system.cpu.numCycles 50016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17625 # Number of cycles cpu stages are processed. -system.cpu.activity 35.167006 # Percentage of cycles cpu is active +system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17333 # Number of cycles cpu stages are processed. +system.cpu.activity 34.654910 # Percentage of cycles cpu is active system.cpu.comLoads 2226 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3359 # Number of Branches instructions committed @@ -42,106 +42,106 @@ system.cpu.committedInsts 15175 # Nu system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total) -system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads -system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads +system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 5166 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target. +system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 5015 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3845 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11051 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3952 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.949092 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11084 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use -system.cpu.icache.total_refs 3085 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use +system.cpu.icache.total_refs 2602 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits -system.cpu.icache.overall_hits::total 3085 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits +system.cpu.icache.overall_hits::total 2602 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses @@ -154,22 +154,22 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.082868 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023702 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023702 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.041769 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023692 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits @@ -188,14 +188,14 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3282500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19680500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19680500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19680500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19680500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3281500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3281500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19678500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19678500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19678500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19678500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -210,10 +210,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -238,34 +238,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2838000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2837000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.036640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.270807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005037 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.948941 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.256684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005034 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005991 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005988 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -284,16 +284,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 299 # system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2777500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18310500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2776500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18309500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7220000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7219000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7220000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7219000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -313,12 +313,12 @@ system.cpu.l2cache.demand_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 2cf0bff32..37bab0cbc 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:35 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:52 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18114000 because target called exit() +Exiting @ tick 19744500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b63661760..dae08ebeb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18114000 # Number of ticks simulated -final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19744500 # Number of ticks simulated +final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120891 # Simulator instruction rate (inst/s) -host_op_rate 120873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151511225 # Simulator tick rate (ticks/s) -host_mem_usage 211580 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 108489 # Simulator instruction rate (inst/s) +host_op_rate 108474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148211557 # Simulator tick rate (ticks/s) +host_mem_usage 211612 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory +system.physmem.bytes_read 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 476 # Number of read requests responded to by this memory +system.physmem.num_reads 484 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 36229 # number of cpu cycles simulated +system.cpu.numCycles 39490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5641 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits +system.cpu.BPredUnit.lookups 6899 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7524 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7253 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8680 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8245 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 639 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 705 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18581 # Type of FU issued -system.cpu.iq.rate 0.512876 # Inst issue rate -system.cpu.iq.fu_busy_cnt 139 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21701 # Type of FU issued +system.cpu.iq.rate 0.549532 # Inst issue rate +system.cpu.iq.fu_busy_cnt 179 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1102 # number of nop insts executed -system.cpu.iew.exec_refs 4620 # number of memory reference insts executed -system.cpu.iew.exec_branches 3963 # Number of branches executed -system.cpu.iew.exec_stores 1758 # Number of stores executed -system.cpu.iew.exec_rate 0.492837 # Inst execution rate -system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 17429 # cumulative count of insts written-back -system.cpu.iew.wb_producers 8123 # num instructions producing a value -system.cpu.iew.wb_consumers 9726 # num instructions consuming a value +system.cpu.iew.exec_nop 1163 # number of nop insts executed +system.cpu.iew.exec_refs 5392 # number of memory reference insts executed +system.cpu.iew.exec_branches 4300 # Number of branches executed +system.cpu.iew.exec_stores 2114 # Number of stores executed +system.cpu.iew.exec_rate 0.519397 # Inst execution rate +system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19916 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9270 # num instructions producing a value +system.cpu.iew.wb_consumers 11399 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle system.cpu.commit.committedInsts 15175 # Number of instructions committed system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -267,62 +267,62 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 46300 # The number of ROB reads -system.cpu.rob.rob_writes 43308 # The number of ROB writes -system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 52944 # The number of ROB reads +system.cpu.rob.rob_writes 51625 # The number of ROB writes +system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads -system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28557 # number of integer regfile reads -system.cpu.int_regfile_writes 15938 # number of integer regfile writes -system.cpu.misc_regfile_reads 6251 # number of misc regfile reads +system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads +system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32680 # number of integer regfile reads +system.cpu.int_regfile_writes 18187 # number of integer regfile writes +system.cpu.misc_regfile_reads 7045 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use -system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use +system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits -system.cpu.icache.overall_hits::total 4151 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses -system.cpu.icache.overall_misses::total 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits +system.cpu.icache.overall_hits::total 5020 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses +system.cpu.icache.overall_misses::total 486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -331,84 +331,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use -system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use +system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits -system.cpu.dcache.overall_hits::total 3706 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4077 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4077 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4077 # number of overall hits +system.cpu.dcache.overall_hits::total 4077 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3994500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3994500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14649500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14649500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18644000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18644000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 526 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 526 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 526 # number of overall misses +system.cpu.dcache.overall_misses::total 526 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4092500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14593500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18686000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18686000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4228 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4228 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040919 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.123463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.123463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,14 +417,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 380 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -433,87 +433,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 192.484909 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005874 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001095 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006969 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006104 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses +system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11308000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2167000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11308000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5039000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11308000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5039000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16347000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 332 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11582500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13751500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11582500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16620500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11582500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16620500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993976 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,42 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10246500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10497000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12215000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 2bb2951e2..84d6c3ee2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:55 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:18:13 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -10,10 +10,10 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed [Iteration 2, Thread 1] Got lock [Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 @@ -22,12 +22,12 @@ Iteration 1 completed [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 @@ -36,19 +36,19 @@ Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 @@ -57,26 +57,26 @@ Iteration 6 completed [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 104317500 because target called exit() +Exiting @ tick 111402500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index befe09ef8..f6ac2f26c 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,329 +1,329 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000104 # Number of seconds simulated -sim_ticks 104317500 # Number of ticks simulated -final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000111 # Number of seconds simulated +sim_ticks 111402500 # Number of ticks simulated +final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190796 # Simulator instruction rate (inst/s) -host_op_rate 190795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19532213 # Simulator tick rate (ticks/s) -host_mem_usage 225896 # Number of bytes of host memory used -host_seconds 5.34 # Real time elapsed on the host -sim_insts 1018993 # Number of instructions simulated -sim_ops 1018993 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 41984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory +host_inst_rate 189621 # Simulator instruction rate (inst/s) +host_op_rate 189621 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19396106 # Simulator tick rate (ticks/s) +host_mem_usage 226052 # Number of bytes of host memory used +host_seconds 5.74 # Real time elapsed on the host +sim_insts 1089093 # Number of instructions simulated +sim_ops 1089093 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 43072 # Number of bytes read from this memory +system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 656 # Number of read requests responded to by this memory +system.physmem.num_reads 673 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 402463633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 270558631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 402463633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 208636 # number of cpu cycles simulated +system.cpu0.numCycles 222806 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 80640 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 78657 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1043 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 79781 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 77332 # Number of BTB hits +system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 408 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16565 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478922 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 80640 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77740 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 158137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3216 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12889 # Number of cycles fetch has spent blocked +system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5515 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 190846 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.509468 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.192643 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32709 17.14% 17.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78517 41.14% 58.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 548 0.29% 58.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 994 0.52% 59.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 666 0.35% 59.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 74596 39.09% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 801 0.42% 98.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 243 0.13% 99.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1772 0.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 190846 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.386510 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.295491 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16943 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14345 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 157232 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 303 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2023 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 476750 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2023 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17547 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1397 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12300 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 156956 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 623 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 474177 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 323986 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 945682 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 945682 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 313636 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10350 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 803 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 824 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 152097 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 76745 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74317 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74189 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 396725 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 846 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 395036 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7136 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 287 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 190846 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.069920 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087146 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 31787 16.66% 16.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5152 2.70% 19.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 75953 39.80% 59.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 75299 39.46% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1582 0.83% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 772 0.40% 99.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 222 0.12% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 71 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 190846 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 35 14.96% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 80 34.19% 49.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 119 50.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 166893 42.25% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 151805 38.43% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 76338 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 395036 # Type of FU issued -system.cpu0.iq.rate 1.893422 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 234 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000592 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 981250 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405901 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 393576 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued +system.cpu0.iq.rate 1.906569 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 395270 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 73924 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1695 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1038 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2023 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1027 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 472373 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 357 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 152097 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 76745 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 745 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 734 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1201 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 394155 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 151500 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 881 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 74802 # number of nop insts executed -system.cpu0.iew.exec_refs 227728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 78432 # Number of branches executed -system.cpu0.iew.exec_stores 76228 # Number of stores executed -system.cpu0.iew.exec_rate 1.889199 # Inst execution rate -system.cpu0.iew.wb_sent 393836 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 393576 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 233255 # num instructions producing a value -system.cpu0.iew.wb_consumers 235364 # num instructions consuming a value +system.cpu0.iew.exec_nop 80538 # number of nop insts executed +system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed +system.cpu0.iew.exec_branches 84187 # Number of branches executed +system.cpu0.iew.exec_stores 82042 # Number of stores executed +system.cpu0.iew.exec_rate 1.901466 # Inst execution rate +system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 250585 # num instructions producing a value +system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.886424 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 188840 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.450747 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135046 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32333 17.12% 17.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78258 41.44% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2188 1.16% 59.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 719 0.38% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 659 0.35% 60.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 73614 38.98% 99.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 485 0.26% 99.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 280 0.15% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 304 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 462799 # Number of instructions committed -system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 496189 # Number of instructions committed +system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 226109 # Number of memory references committed -system.cpu0.commit.loads 150402 # Number of loads committed +system.cpu0.commit.refs 242804 # Number of memory references committed +system.cpu0.commit.loads 161532 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 77595 # Number of branches committed +system.cpu0.commit.branches 83160 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 311966 # Number of committed integer instructions. +system.cpu0.commit.int_insts 334226 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 304 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 659709 # The number of ROB reads -system.cpu0.rob.rob_writes 946703 # The number of ROB writes +system.cpu0.rob.rob_reads 709866 # The number of ROB reads +system.cpu0.rob.rob_writes 1020791 # The number of ROB writes system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 388389 # Number of Instructions Simulated -system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated -system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.861563 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.861563 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705230 # number of integer regfile reads -system.cpu0.int_regfile_writes 317935 # number of integer regfile writes +system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 416214 # Number of Instructions Simulated +system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated +system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 757980 # number of integer regfile reads +system.cpu0.int_regfile_writes 341432 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 229503 # number of misc regfile reads +system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 294 # number of replacements -system.cpu0.icache.tagsinuse 244.353680 # Cycle average of tags in use -system.cpu0.icache.total_refs 4810 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks. +system.cpu0.icache.replacements 300 # number of replacements +system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use +system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits -system.cpu0.icache.overall_hits::total 4810 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses -system.cpu0.icache.overall_misses::total 705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits +system.cpu0.icache.overall_hits::total 5459 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses +system.cpu0.icache.overall_misses::total 759 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -332,444 +332,444 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use -system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks. +system.cpu0.dcache.replacements 8 # number of replacements +system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use +system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 140.432794 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77005 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77005 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75125 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75125 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152130 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152130 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152130 # number of overall hits -system.cpu0.dcache.overall_hits::total 152130 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 517 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1057 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1057 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1057 # number of overall misses -system.cpu0.dcache.overall_misses::total 1057 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 371000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 371000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39427484 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39427484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75665 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits +system.cpu0.dcache.overall_hits::total 163710 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses +system.cpu0.dcache.overall_misses::total 1041 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153187 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153187 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 153187 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 153187 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006669 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007137 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28500 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks system.cpu0.dcache.writebacks::total 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 327 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 327 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 695 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 190 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 190 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174305 # number of cpu cycles simulated +system.cpu1.numCycles 187393 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52112 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 49475 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 48064 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46080 # Number of BTB hits +system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 697 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 26834 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 291745 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52112 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46777 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 102740 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3160 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 32953 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 18341 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171598 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.700166 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.136223 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 68858 40.13% 40.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52177 30.41% 70.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5705 3.32% 73.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3354 1.95% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 589 0.34% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36153 21.07% 97.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1352 0.79% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 417 0.24% 98.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 2993 1.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171598 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.298970 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.673762 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 31662 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 29517 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97194 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4829 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1999 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 288983 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1999 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 32299 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 14957 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13738 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92834 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 9374 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 287085 # Number of instructions processed by rename +system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 200836 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 551958 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 551958 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 191192 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1080 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11997 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 82183 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38955 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39306 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34408 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 238857 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 241490 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 8361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171598 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.407301 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310079 # Number of insts issued each cycle +system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 65840 38.37% 38.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21732 12.66% 51.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38892 22.66% 73.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40381 23.53% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3339 1.95% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1157 0.67% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 163 0.09% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 40 0.02% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171598 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 62 23.48% 28.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 190 71.97% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116592 48.28% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 86338 35.75% 84.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 38560 15.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 241490 # Type of FU issued -system.cpu1.iq.rate 1.385445 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001093 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 654845 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 253312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 240391 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued +system.cpu1.iq.rate 1.409476 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 241754 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34276 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1784 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 861 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1999 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1765 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 285210 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 82183 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38955 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1043 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 599 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 655 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1254 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 240751 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 81429 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 739 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40289 # number of nop insts executed -system.cpu1.iew.exec_refs 119949 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49362 # Number of branches executed -system.cpu1.iew.exec_stores 38520 # Number of stores executed -system.cpu1.iew.exec_rate 1.381205 # Inst execution rate -system.cpu1.iew.wb_sent 240558 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 240391 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 136702 # num instructions producing a value -system.cpu1.iew.wb_consumers 141193 # num instructions consuming a value +system.cpu1.iew.exec_nop 44378 # number of nop insts executed +system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed +system.cpu1.iew.exec_branches 53738 # Number of branches executed +system.cpu1.iew.exec_stores 42625 # Number of stores executed +system.cpu1.iew.exec_rate 1.402560 # Inst execution rate +system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 149144 # num instructions producing a value +system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.379140 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 275667 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 163203 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.689105 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.043033 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 64641 39.61% 39.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47587 29.16% 68.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5957 3.65% 72.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6309 3.87% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.96% 77.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 34602 21.20% 98.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 646 0.40% 98.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1051 0.64% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 839 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 275667 # Number of instructions committed -system.cpu1.commit.committedOps 275667 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 298843 # Number of instructions committed +system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 118493 # Number of memory references committed -system.cpu1.commit.loads 80399 # Number of loads committed -system.cpu1.commit.membars 4716 # Number of memory barriers committed -system.cpu1.commit.branches 48773 # Number of branches committed +system.cpu1.commit.refs 129859 # Number of memory references committed +system.cpu1.commit.loads 88054 # Number of loads committed +system.cpu1.commit.membars 4938 # Number of memory barriers committed +system.cpu1.commit.branches 52708 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 189391 # Number of committed integer instructions. +system.cpu1.commit.int_insts 204694 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 839 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 446977 # The number of ROB reads -system.cpu1.rob.rob_writes 572400 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 231385 # Number of Instructions Simulated -system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated -system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327472 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327472 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 418065 # number of integer regfile reads -system.cpu1.int_regfile_writes 194844 # number of integer regfile writes +system.cpu1.rob.rob_reads 487255 # The number of ROB reads +system.cpu1.rob.rob_writes 629168 # The number of ROB writes +system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 250401 # Number of Instructions Simulated +system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated +system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 456552 # number of integer regfile reads +system.cpu1.int_regfile_writes 212248 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 121500 # number of misc regfile reads +system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 84.541118 # Cycle average of tags in use -system.cpu1.icache.total_refs 17870 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. +system.cpu1.icache.replacements 322 # number of replacements +system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use +system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 84.541118 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 17870 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 17870 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 17870 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 17870 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 17870 # number of overall hits -system.cpu1.icache.overall_hits::total 17870 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 471 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 471 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 471 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 471 # number of overall misses -system.cpu1.icache.overall_misses::total 471 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7203000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7203000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7203000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7203000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 18341 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 18341 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 18341 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 18341 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits +system.cpu1.icache.overall_hits::total 19304 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses +system.cpu1.icache.overall_misses::total 505 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -778,90 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 427 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 427 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 427 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 24.401572 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use +system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 24.401572 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 46660 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46660 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 37905 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 37905 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 84565 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 84565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 84565 # number of overall hits -system.cpu1.dcache.overall_hits::total 84565 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 478 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 124 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 124 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 602 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 602 # number of overall misses -system.cpu1.dcache.overall_misses::total 602 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13204500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13204500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85167 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85167 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85167 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85167 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010140 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003261 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits +system.cpu1.dcache.overall_hits::total 92793 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses +system.cpu1.dcache.overall_misses::total 629 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,350 +872,350 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 18 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 341 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 261 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003288 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002787 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 174018 # number of cpu cycles simulated +system.cpu2.numCycles 187102 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 49365 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 46733 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1149 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45641 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 43566 # Number of BTB hits +system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 657 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 27807 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 273933 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 49365 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44223 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 97490 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3286 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 34440 # Number of cycles fetch has spent blocked +system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6393 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 776 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19059 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 204 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 168970 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.621193 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.105353 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71480 42.30% 42.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49528 29.31% 71.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6067 3.59% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3620 2.14% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 727 0.43% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 32913 19.48% 97.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1356 0.80% 98.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 430 0.25% 98.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2849 1.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 168970 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283678 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.574165 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 32851 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 30938 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 91697 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5032 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2059 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 271122 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2059 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 33552 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15710 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14412 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87163 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9681 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 268918 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 188425 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 514118 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 514118 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178130 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10295 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1067 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1200 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12339 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 75827 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 35627 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36245 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31070 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 223191 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6330 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 225872 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 8050 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 168970 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.336758 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.306399 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68735 40.68% 40.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22585 13.37% 54.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35942 21.27% 75.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37104 21.96% 97.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3355 1.99% 99.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 981 0.58% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 168 0.10% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 42 0.02% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 168970 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19 7.04% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 61 22.59% 29.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 190 70.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 110495 48.92% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80157 35.49% 84.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35220 15.59% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 225872 # Type of FU issued -system.cpu2.iq.rate 1.297981 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 270 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001195 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 620987 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 238263 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 224632 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued +system.cpu2.iq.rate 1.255545 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 226142 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 30940 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1843 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 852 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1941 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 266786 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 75827 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 35627 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1018 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 683 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 611 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1294 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 225039 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 74986 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 833 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37265 # number of nop insts executed -system.cpu2.iew.exec_refs 110171 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46373 # Number of branches executed -system.cpu2.iew.exec_stores 35185 # Number of stores executed -system.cpu2.iew.exec_rate 1.293194 # Inst execution rate -system.cpu2.iew.wb_sent 224805 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 224632 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 127007 # num instructions producing a value -system.cpu2.iew.wb_consumers 131418 # num instructions consuming a value +system.cpu2.iew.exec_nop 39077 # number of nop insts executed +system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed +system.cpu2.iew.exec_branches 48223 # Number of branches executed +system.cpu2.iew.exec_stores 36178 # Number of stores executed +system.cpu2.iew.exec_rate 1.248153 # Inst execution rate +system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 130712 # num instructions producing a value +system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.290855 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 256708 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 160519 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.599237 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.012927 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 67924 42.32% 42.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 44668 27.83% 70.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6005 3.74% 73.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6542 4.08% 77.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1606 1.00% 78.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31385 19.55% 98.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 504 0.31% 98.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1049 0.65% 99.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 836 0.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 256708 # Number of instructions committed -system.cpu2.commit.committedOps 256708 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 263733 # Number of instructions committed +system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108759 # Number of memory references committed -system.cpu2.commit.loads 73984 # Number of loads committed -system.cpu2.commit.membars 4966 # Number of memory barriers committed -system.cpu2.commit.branches 45704 # Number of branches committed +system.cpu2.commit.refs 111398 # Number of memory references committed +system.cpu2.commit.loads 76032 # Number of loads committed +system.cpu2.commit.membars 5840 # Number of memory barriers committed +system.cpu2.commit.branches 47167 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176579 # Number of committed integer instructions. +system.cpu2.commit.int_insts 180680 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 836 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425878 # The number of ROB reads -system.cpu2.rob.rob_writes 535627 # The number of ROB writes -system.cpu2.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 215254 # Number of Instructions Simulated -system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated -system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.236964 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.236964 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 389052 # number of integer regfile reads -system.cpu2.int_regfile_writes 181919 # number of integer regfile writes +system.cpu2.rob.rob_reads 450492 # The number of ROB reads +system.cpu2.rob.rob_writes 562082 # The number of ROB writes +system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 219944 # Number of Instructions Simulated +system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated +system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 401453 # number of integer regfile reads +system.cpu2.int_regfile_writes 187612 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 111746 # number of misc regfile reads +system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 321 # number of replacements -system.cpu2.icache.tagsinuse 85.227474 # Cycle average of tags in use -system.cpu2.icache.total_refs 18578 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. +system.cpu2.icache.replacements 325 # number of replacements +system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use +system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 85.227474 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 18578 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 18578 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 18578 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 18578 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 18578 # number of overall hits -system.cpu2.icache.overall_hits::total 18578 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 481 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 481 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 481 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 481 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 481 # number of overall misses -system.cpu2.icache.overall_misses::total 481 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 10446500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 10446500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 10446500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 10446500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19059 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19059 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19059 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19059 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025237 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025237 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025237 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits +system.cpu2.icache.overall_hits::total 21358 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses +system.cpu2.icache.overall_misses::total 512 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1224,90 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 54 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 54 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 54 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 427 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 427 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 427 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 26.582846 # Cycle average of tags in use -system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.582846 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 43569 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 43569 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 34581 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 34581 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 78150 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 78150 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 78150 # number of overall hits -system.cpu2.dcache.overall_hits::total 78150 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 459 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 459 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 120 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 120 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 61 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 579 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 579 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 579 # number of overall misses -system.cpu2.dcache.overall_misses::total 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 13980000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 13980000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 78729 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 78729 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 78729 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 78729 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010425 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003458 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.824324 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007354 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007354 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits +system.cpu2.dcache.overall_hits::total 80860 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses +system.cpu2.dcache.overall_misses::total 584 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1318,350 +1318,350 @@ system.cpu2.dcache.fast_writes 0 # nu system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 297 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 297 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 18 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 315 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 61 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 264 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002939 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.824324 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173752 # number of cpu cycles simulated +system.cpu3.numCycles 186832 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 43974 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 41362 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1065 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 40218 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 38243 # Number of BTB hits +system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 31228 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 238342 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 43974 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 38870 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 88902 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3085 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 41810 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6387 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 22959 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 170982 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.393960 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.002021 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 82080 48.01% 48.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 46273 27.06% 75.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8028 4.70% 79.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3581 2.09% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 661 0.39% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 25734 15.05% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1333 0.78% 98.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 378 0.22% 98.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2914 1.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 170982 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.253085 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.371737 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 38250 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 36210 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 81249 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6942 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1944 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 235582 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1944 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 38898 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21197 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14171 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 74841 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13544 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 233650 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 34 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 161376 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 435940 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 435940 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 151925 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 9451 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1060 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1201 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16222 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 63593 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 28573 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31152 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24018 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 191280 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8270 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 196054 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 8200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 7610 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 629 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 170982 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.146635 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.276395 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 79237 46.34% 46.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28336 16.57% 62.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 28717 16.80% 79.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30135 17.62% 97.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3289 1.92% 99.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1034 0.60% 99.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 139 0.08% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 41 0.02% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 170982 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 4.49% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 44 17.96% 22.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 190 77.55% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 97962 49.97% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 69919 35.66% 85.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 28173 14.37% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 196054 # Type of FU issued -system.cpu3.iq.rate 1.128355 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 245 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001250 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 563338 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 207780 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 194934 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued +system.cpu3.iq.rate 1.169655 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 196299 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 23899 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1728 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 841 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1944 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 231715 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 63593 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 28573 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 992 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 631 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 549 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1180 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 195273 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 62778 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 781 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32165 # number of nop insts executed -system.cpu3.iew.exec_refs 90920 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41191 # Number of branches executed -system.cpu3.iew.exec_stores 28142 # Number of stores executed -system.cpu3.iew.exec_rate 1.123860 # Inst execution rate -system.cpu3.iew.wb_sent 195091 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 194934 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 107675 # num instructions producing a value -system.cpu3.iew.wb_consumers 111992 # num instructions consuming a value +system.cpu3.iew.exec_nop 36198 # number of nop insts executed +system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed +system.cpu3.iew.exec_branches 45494 # Number of branches executed +system.cpu3.iew.exec_stores 32232 # Number of stores executed +system.cpu3.iew.exec_rate 1.162692 # Inst execution rate +system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 119982 # num instructions producing a value +system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.121909 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 162652 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.366697 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.912123 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 80351 49.40% 49.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 39430 24.24% 73.64% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6019 3.70% 77.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8502 5.23% 82.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1632 1.00% 83.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24257 14.91% 98.49% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 559 0.34% 98.83% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 841 0.52% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 222296 # Number of instructions committed -system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 244729 # Number of instructions committed +system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 89597 # Number of memory references committed -system.cpu3.commit.loads 61865 # Number of loads committed -system.cpu3.commit.membars 6925 # Number of memory barriers committed -system.cpu3.commit.branches 40618 # Number of branches committed +system.cpu3.commit.refs 100719 # Number of memory references committed +system.cpu3.commit.loads 69310 # Number of loads committed +system.cpu3.commit.membars 7019 # Number of memory barriers committed +system.cpu3.commit.branches 44389 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 152335 # Number of committed integer instructions. +system.cpu3.commit.int_insts 167227 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 841 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 392929 # The number of ROB reads -system.cpu3.rob.rob_writes 465356 # The number of ROB writes -system.cpu3.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 183965 # Number of Instructions Simulated -system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated -system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.058779 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.058779 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 330929 # number of integer regfile reads -system.cpu3.int_regfile_writes 155348 # number of integer regfile writes +system.cpu3.rob.rob_reads 432891 # The number of ROB reads +system.cpu3.rob.rob_writes 522404 # The number of ROB writes +system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 202534 # Number of Instructions Simulated +system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated +system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 369217 # number of integer regfile reads +system.cpu3.int_regfile_writes 172842 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 92475 # number of misc regfile reads +system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.006059 # Cycle average of tags in use -system.cpu3.icache.total_refs 22493 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. +system.cpu3.icache.replacements 320 # number of replacements +system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use +system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.006059 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 22493 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 22493 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 22493 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 22493 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 22493 # number of overall hits -system.cpu3.icache.overall_hits::total 22493 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 466 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 466 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 466 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 466 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 466 # number of overall misses -system.cpu3.icache.overall_misses::total 466 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6527000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6527000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6527000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6527000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 22959 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 22959 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 22959 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 22959 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020297 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020297 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020297 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits +system.cpu3.icache.overall_hits::total 23951 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses +system.cpu3.icache.overall_misses::total 503 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1670,90 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 40 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 40 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 40 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 426 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 426 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 426 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 23.407477 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use +system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 23.407477 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 38412 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 38412 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 27537 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 27537 # number of WriteReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.049395 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.049395 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 42933 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 42933 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 31189 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 31189 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 65949 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 65949 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 65949 # number of overall hits -system.cpu3.dcache.overall_hits::total 65949 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 448 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 448 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 125 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 573 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 573 # number of overall misses -system.cpu3.dcache.overall_misses::total 573 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 12269000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 12269000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 66522 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 66522 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 66522 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 66522 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011529 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004519 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.800000 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008614 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008614 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23288 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency +system.cpu3.dcache.demand_hits::cpu3.data 74122 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 74122 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 74122 # number of overall hits +system.cpu3.dcache.overall_hits::total 74122 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 420 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 420 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 569 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 569 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 569 # number of overall misses +system.cpu3.dcache.overall_misses::total 569 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8616000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8616000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3007500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3007500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1198000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1198000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11623500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11623500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11623500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11623500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 43353 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 43353 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 31338 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1764,222 +1764,222 @@ system.cpu3.dcache.fast_writes 0 # nu system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 279 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 17 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 296 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 169 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004349 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003904 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.231635 # Cycle average of tags in use -system.l2c.total_refs 1446 # Total number of references to valid blocks. -system.l2c.sampled_refs 527 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. +system.l2c.tagsinuse 441.136869 # Cycle average of tags in use +system.l2c.total_refs 1471 # Total number of references to valid blocks. +system.l2c.sampled_refs 544 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.704044 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 4.965624 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 287.776309 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.398265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 10.494682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 0.774865 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 57.571117 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5.683514 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.828706 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.738553 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004391 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000906 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000878 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 294.783080 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.595754 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 9.493651 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.732946 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 64.319288 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 5.723296 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.834559 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.775880 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000074 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004498 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000909 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000145 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000981 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006534 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 228 # number of ReadReq hits +system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006731 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 231 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 12 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 420 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 12 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1449 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 231 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 12 # number of demand (read+write) hits -system.l2c.demand_hits::total 1449 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 228 # number of overall hits +system.l2c.demand_hits::cpu3.inst 430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::total 1474 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 231 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # number of overall hits -system.l2c.overall_hits::cpu1.data 12 # number of overall hits -system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu1.inst 420 # number of overall hits +system.l2c.overall_hits::cpu1.data 13 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits system.l2c.overall_hits::cpu2.data 7 # number of overall hits -system.l2c.overall_hits::cpu3.inst 424 # number of overall hits -system.l2c.overall_hits::cpu3.data 12 # number of overall hits -system.l2c.overall_hits::total 1449 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 354 # number of ReadReq misses +system.l2c.overall_hits::cpu3.inst 430 # number of overall hits +system.l2c.overall_hits::cpu3.data 13 # number of overall hits +system.l2c.overall_hits::total 1474 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 78 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 85 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 549 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 354 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 78 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 85 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 664 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 354 # number of overall misses +system.l2c.demand_misses::total 680 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 363 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses system.l2c.overall_misses::cpu1.inst 15 # number of overall misses system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 78 # number of overall misses +system.l2c.overall_misses::cpu2.inst 85 # number of overall misses system.l2c.overall_misses::cpu2.data 20 # number of overall misses system.l2c.overall_misses::cpu3.inst 2 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 664 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 18441500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3931500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 745000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 680 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 18919500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3929500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 744500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 4016500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 365500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 96000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 4376000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 99500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 27701000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 28540000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4940000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4939500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 683000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 680500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 18441500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8871500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 745000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::total 6875000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18919500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 744500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 4016500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1048500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 96000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 4376000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1046500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 99500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34579000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 18441500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8871500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 745000 # number of overall miss cycles +system.l2c.demand_miss_latency::total 35415000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18919500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 744500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 4016500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1048500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 96000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 4376000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1046500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 99500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34579000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 582 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::total 35415000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 594 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 435 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 440 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 426 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 432 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 594 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 435 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 440 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 426 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2113 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 582 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 432 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 594 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 435 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 440 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 426 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2113 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.608247 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu3.inst 432 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.035129 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.076923 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.182670 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.004695 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.076923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses @@ -1987,52 +1987,52 @@ system.l2c.ReadExReq_miss_rate::cpu0.data 1 # m system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.608247 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.035129 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.520000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.182670 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.004695 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.520000 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.608247 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.035129 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.520000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.182670 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.004695 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.520000 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52094.632768 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52420 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49666.666667 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51493.589744 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52214.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2386.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 2386.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2386.363636 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52553.191489 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52538.461538 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52425 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52425 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -2042,104 +2042,101 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 353 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 80 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 353 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 80 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 656 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 353 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 673 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 80 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 656 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14091500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3019000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 561000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 673 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14492500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3016500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 560000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2922000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 3200000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 20993500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 840000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3480000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3792000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 524500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21669000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 680000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3200000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3793000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 522500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 14091500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6811000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 561000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2922000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 804500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5278500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14492500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6809500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 560000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 521500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 3200000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 802500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 26272500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14091500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6811000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 561000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 521000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2922000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 804500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26947500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14492500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6809500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 560000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 521500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 3200000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 802500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 26272500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::total 26947500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses @@ -2147,27 +2144,27 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency @@ -2175,24 +2172,24 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |