diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-20 22:44:22 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-20 22:44:22 -0400 |
| commit | d1e8be9a73ace42caf479005acf0e57f805e7bc2 (patch) | |
| tree | e20c1d95e4a683bf6cbbb74069ffafbb5ed61bbe /tests | |
| parent | 08c1a6f41b3d74b5bf388c05efbd99c1b79b3bfe (diff) | |
| download | gem5-d1e8be9a73ace42caf479005acf0e57f805e7bc2.tar.xz | |
inorder: sparc: add hello world regression
- add InOrderCPU compile option to SPARC
- add hello regression for SPARC
Diffstat (limited to 'tests')
4 files changed, 516 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini new file mode 100644 index 000000000..37073b2df --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -0,0 +1,237 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchBuffSize=4 +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=4 +system=system +threadModel=SMT +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=tests/test-progs/hello/bin/sparc/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout new file mode 100755 index 000000000..ca819dade --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jun 20 2011 19:27:12 +gem5 started Jun 20 2011 19:28:17 +gem5 executing on zooks +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 18208500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt new file mode 100644 index 000000000..50ad2ecd7 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -0,0 +1,267 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18208500 # Number of ticks simulated +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 40053 # Simulator instruction rate (inst/s) +host_tick_rate 136538838 # Simulator tick rate (ticks/s) +host_mem_usage 158968 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5340 # Number of instructions simulated +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 36418 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 9732 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30132 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6286 # Number of cycles cpu stages are processed. +system.cpu.activity 17.260695 # Percentage of cycles cpu is active +system.cpu.comLoads 716 # Number of Load instructions committed +system.cpu.comStores 673 # Number of Store instructions committed +system.cpu.comBranches 1116 # Number of Branches instructions committed +system.cpu.comNops 173 # Number of Nop instructions committed +system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed +system.cpu.comInts 2537 # Number of Integer instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed +system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total) +system.cpu.cpi 6.819850 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 6.819850 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146631 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.146631 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1667 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1128 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 904 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1481 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 657 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 44.361918 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 724 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 943 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5610 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9610 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 1749 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1473 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 407 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 434 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 841 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 275 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 75.358423 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3970 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 31732 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4686 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.867263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33196 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3222 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.847273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33369 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3049 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.372234 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35435 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.699215 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33245 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3173 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.712724 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 136.664121 # Cycle average of tags in use +system.cpu.icache.total_refs 791 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 136.664121 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.066731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits +system.cpu.icache.demand_hits 791 # number of demand (read+write) hits +system.cpu.icache.overall_hits 791 # number of overall hits +system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses +system.cpu.icache.demand_misses 347 # number of demand (read+write) misses +system.cpu.icache.overall_misses 347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 19112000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19112000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19112000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55077.809798 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55077.809798 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55077.809798 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 15471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15471500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 82.862842 # Cycle average of tags in use +system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 82.862842 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020230 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits +system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1049 # number of overall hits +system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses +system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 162.289874 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 162.289874 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 423 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 17920000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 22150500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 22150500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52397.660819 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52365.248227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52365.248227 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |