diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
| commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
| tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests | |
| parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
| download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests')
63 files changed, 6047 insertions, 4661 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index 330249aa1..7683e2958 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -146,6 +146,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -569,6 +570,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -618,6 +620,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -747,6 +750,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 4fcd96b8e..e432f371b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,28 +4,31 @@ sim_seconds 1.884236 # Nu sim_ticks 1884235597000 # Number of ticks simulated final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284222 # Simulator instruction rate (inst/s) -host_op_rate 284222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9542341098 # Simulator tick rate (ticks/s) -host_mem_usage 373416 # Number of bytes of host memory used -host_seconds 197.46 # Real time elapsed on the host +host_inst_rate 167027 # Simulator instruction rate (inst/s) +host_op_rate 167027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5607682389 # Simulator tick rate (ticks/s) +host_mem_usage 359752 # Number of bytes of host memory used +host_seconds 336.01 # Real time elapsed on the host sim_insts 56122640 # Number of instructions simulated sim_ops 56122640 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) @@ -33,7 +36,8 @@ system.physmem.bw_inst_read::total 558945 # In system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 404934 # Number of read requests accepted @@ -446,8 +450,8 @@ system.cpu.dcache.tags.total_refs 13772439 # To system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id @@ -456,69 +460,69 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7814297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182732 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13390675 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13390675 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits system.cpu.dcache.overall_hits::total 13390675 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 573763 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17288 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 1775403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1775403 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses system.cpu.dcache.overall_misses::total 1775403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51714049793 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 51714049793 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51714049793 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 9015937 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 6150141 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150141 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198999 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15166078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15166078 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15166078 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15166078 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133280 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093293 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086431 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117064 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117064 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117064 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117064 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25826.915091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36041.702834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36041.702834 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13377.819875 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -530,67 +534,67 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks system.cpu.dcache.writebacks::total 838265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127268 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127268 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269487 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396755 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 396755 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 396755 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396755 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 396755 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 396755 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074372 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074372 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1074372 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304276 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304276 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304276 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17285 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17285 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17285 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378648 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378648 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1378648 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378648 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378648 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1378648 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26917637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26917637000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 26917637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10249005096 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10249005096 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196537750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196537750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37166642096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37166642096 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37166642096 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37166642096 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423897500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002909000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002909000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426806500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3426806500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119164 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119164 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049475 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086416 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086416 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090903 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.090903 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090903 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.090903 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25054.298697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25054.298697 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33683.251706 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33683.251706 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11370.422332 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11370.422332 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332 # average LoadLockedReq mshr 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-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1459474 # number of replacements @@ -685,9 +689,11 @@ system.cpu.l2cache.tags.sampled_refs 404595 # Sa system.cpu.l2cache.tags.avg_refs 7.373326 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 54499.677348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10825.657308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5826.101052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4999.556256 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.831599 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165186 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088899 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.076287 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.996786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id @@ -698,69 +704,87 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 30263477 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 30263477 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2263052 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1443639 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 819413 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2263052 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 838265 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 838265 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # 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for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383443 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.383443 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141928 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278592 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141928 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011271 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278592 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65543.688143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72775.931215 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65106.454848 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12617.470588 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.344261 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66572.913111 # average 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.852143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56539.364471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 16f8b652d..f1c3d0229 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,21 +4,23 @@ sim_seconds 2.845843 # Nu sim_ticks 2845842660500 # Number of ticks simulated final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164712 # Simulator instruction rate (inst/s) -host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3743328799 # Simulator tick rate (ticks/s) -host_mem_usage 646452 # Number of bytes of host memory used -host_seconds 760.24 # Real time elapsed on the host +host_inst_rate 92448 # Simulator instruction rate (inst/s) +host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101025547 # Simulator tick rate (ticks/s) +host_mem_usage 635156 # Number of bytes of host memory used +host_seconds 1354.50 # Real time elapsed on the host sim_insts 125221621 # Number of instructions simulated sim_ops 151624712 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory @@ -26,28 +28,32 @@ system.physmem.bytes_inst_read::cpu0.inst 1722304 # N system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) @@ -55,16 +61,18 @@ system.physmem.bw_inst_read::cpu0.inst 605200 # In system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) @@ -544,8 +552,8 @@ system.cpu0.dcache.tags.total_refs 40476936 # To system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id @@ -554,81 +562,81 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22808347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16863099 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381264 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362825 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39671446 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39671446 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 540080 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532227 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 19898 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1072307 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1072307 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6648434719 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8319872197 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 104923750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438142885 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 309000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14968306916 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14968306916 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23348427 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395326 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387753 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382723 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40743753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40743753 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023131 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030596 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016735 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026318 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026318 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -640,77 +648,77 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks system.cpu0.dcache.writebacks::total 523102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42658 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230433 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273091 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 497422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 301794 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses 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overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6190990749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4804555500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles 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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1982441 # number of replacements @@ -821,12 +829,14 @@ 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-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution @@ -1343,8 +1390,8 @@ system.cpu1.dcache.tags.total_refs 7034054 # To system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 478.493571 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.934558 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id @@ -1352,81 +1399,81 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3762812 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3070723 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 89288 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6833535 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6833535 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 181434 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139542 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5058 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23425 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 320976 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 320976 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses system.cpu1.dcache.overall_misses::total 320976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2698134351 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3673411367 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 91654251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540931813 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 185500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6371545718 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6371545718 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3944246 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3210265 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94346 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92687 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7154511 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7154511 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046000 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.053611 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.252732 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044863 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044863 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044863 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044863 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14871.161695 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26324.772233 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18120.650652 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23092.073127 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1438,77 +1485,77 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks system.cpu1.dcache.writebacks::total 113901 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49794 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64931 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64931 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 64931 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166297 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166297 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89748 # number of WriteReq MSHR misses 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StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4326043539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326043539 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4326043539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4326043539 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 330271000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 330271000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 203208500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 533479500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042162 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.053611 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.252732 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.252732 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13003.300294 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24107.876610 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16118.376631 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21041.843629 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 908016 # number of replacements @@ -1618,12 +1665,14 @@ system.cpu1.l2cache.tags.warmup_cycle 0 # Cy system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.324938 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id @@ -1645,119 +1694,137 @@ system.cpu1.l2cache.tags.tag_accesses 21629208 # Nu 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SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 24979 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1018898 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 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miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 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overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution @@ -2139,18 +2225,22 @@ system.l2c.tags.warmup_cycle 0 # Cy system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9505.348435 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2919.846446 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1856.879628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1274.245745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 582.633884 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.189593 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.145040 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044553 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028334 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.019443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008890 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id @@ -2173,210 +2263,246 @@ system.l2c.tags.tag_accesses 5313847 # Nu system.l2c.tags.data_accesses 5313847 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of 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183727 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 74496 # number of overall hits +system.l2c.overall_hits::cpu0.inst 48963 # number of overall hits +system.l2c.overall_hits::cpu0.data 25533 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 25339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 16648 # number of overall hits +system.l2c.overall_hits::cpu1.data 8691 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits system.l2c.overall_hits::total 183727 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number 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system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 217279 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 8068ce076..6a8c865e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,47 +4,51 @@ sim_seconds 2.852858 # Nu sim_ticks 2852857543000 # Number of ticks simulated final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169259 # Simulator instruction rate (inst/s) -host_op_rate 204656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4303403710 # Simulator tick rate (ticks/s) -host_mem_usage 619600 # Number of bytes of host memory used -host_seconds 662.93 # Real time elapsed on the host +host_inst_rate 109881 # Simulator instruction rate (inst/s) +host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2793727953 # Simulator tick rate (ticks/s) +host_mem_usage 608784 # Number of bytes of host memory used +host_seconds 1021.17 # Real time elapsed on the host sim_insts 112207125 # Number of instructions simulated sim_ops 135672670 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10837924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 169862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3798971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3805114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 170006 # Number of read requests accepted @@ -534,8 +538,8 @@ system.cpu.dcache.tags.total_refs 42762284 # To system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id @@ -544,77 +548,77 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23536274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18304900 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460268 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 41841174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 41841174 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits system.cpu.dcache.overall_hits::total 41841174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 583393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 541748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8195 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 1125141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1125141 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses system.cpu.dcache.overall_misses::total 1125141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8651014339 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21393186307 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 116036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 30044200646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 30044200646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 24119667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 18846648 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466104 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466104 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460270 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460270 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42966315 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42966315 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42966315 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42966315 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42966315 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42966315 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024187 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.024187 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028745 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028745 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.028745 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017582 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017582 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017582 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.026187 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.026187 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14828.793522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39489.183729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.426480 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26702.609403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26702.609403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -626,73 +630,73 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks system.cpu.dcache.writebacks::total 698310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242834 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 287983 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 287983 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 538244 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298914 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 298914 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8195 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8195 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 837158 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 837158 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 837158 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 837158 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837158 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 837158 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6893184142 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6893184142 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6893184142 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11166823654 # number of WriteReq MSHR miss cycles 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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18060007796 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18060007796 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790998000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439562500 # number of WriteReq MSHR uncacheable cycles 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0.019484 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019484 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12806.801640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37357.981406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency 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latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2900110 # number of replacements @@ -797,11 +801,13 @@ system.cpu.l2cache.tags.warmup_cycle 0 # Cy system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 17501.014446 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267044 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id @@ -817,113 +823,131 @@ system.cpu.l2cache.tags.tag_accesses 36621683 # Nu system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 3409631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 53 # number of UpgradeReq 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145565 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 168707 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 168578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 23013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145565 # number of overall misses system.cpu.l2cache.overall_misses::total 168707 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10214250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773098000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1672158250 # number of ReadReq miss cycles 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system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71166 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 4430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 3743128 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2900607 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 842521 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 3818724 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71166 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 4430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3743128 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2900607 # number of overall (read+write) accesses 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UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.443005 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443005 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.443005 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001799 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000226 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172773 # miss 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of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131168 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131168 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 168416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145423 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 168545 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 168416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22993 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 168545 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8641250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2295827000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1382505500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 913321500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2304530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27979779 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27979779 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27979779 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7500556317 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500556317 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500556317 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8641250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9796383317 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1382505500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413877817 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9805087067 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8641250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9796383317 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1382505500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413877817 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 159586250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385715000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107025000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 159586250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9492740000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010806 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026087 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.981285 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981285 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443005 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index f860bb1f1..069845b38 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -782,9 +782,9 @@ system.cpu0.iew.iewDispNonSpecInsts 862014 # Nu system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 287591 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 287589 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 683111 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 683109 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 0523405d3..da0ad220f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -341,10 +341,10 @@ system.physmem_0.preEnergy 73012500 # En system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68915344410 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 68919855390 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860850713630 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.510917 # Core power per rank (mW) +system.physmem_0.totalEnergy 1860855224610 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.510956 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3b8bb2577..f7aa432dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,22 +4,24 @@ sim_seconds 47.355615 # Nu sim_ticks 47355615197500 # Number of ticks simulated final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178863 # Simulator instruction rate (inst/s) -host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9462962325 # Simulator tick rate (ticks/s) -host_mem_usage 759628 # Number of bytes of host memory used -host_seconds 5004.31 # Real time elapsed on the host +host_inst_rate 119180 # Simulator instruction rate (inst/s) +host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6305360463 # Simulator tick rate (ticks/s) +host_mem_usage 747912 # Number of bytes of host memory used +host_seconds 7510.37 # Real time elapsed on the host sim_insts 895084962 # Number of instructions simulated sim_ops 1052703090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory @@ -27,30 +29,34 @@ system.physmem.bytes_inst_read::cpu0.inst 8104128 # N system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) @@ -58,17 +64,19 @@ system.physmem.bw_inst_read::cpu0.inst 171133 # In system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) @@ -354,23 +362,31 @@ system.physmem_1.memoryStateTime::REF 1581308040000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). @@ -588,8 +604,8 @@ system.cpu0.dcache.tags.total_refs 150576282 # To system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id @@ -598,93 +614,93 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 251432 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1745310 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1668274 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 146466768 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 146466768 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3852692 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2255601 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 766100 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 104059 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 180014 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6108293 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6108293 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54452724607 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 41906959422 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 27296991314 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1502404735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3769027814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2840500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 96359684029 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 96359684029 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 80967470 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 71607591 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 1017532 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1849369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1848288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 152575061 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 152575061 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047583 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.031499 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.752900 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.056267 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.097395 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.040035 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.040035 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -696,91 +712,91 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 361487 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 935411 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 100 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 34 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1296898 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1296898 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3491205 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1320190 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 766000 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 104025 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 179947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4811395 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4811395 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42113152704 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles 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of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency 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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 9463678 # number of replacements @@ -891,12 +907,14 @@ system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cy system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 9438.642805 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.576089 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id @@ -922,137 +940,155 @@ system.cpu0.l2cache.tags.tag_accesses 319708402 # Nu system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq 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overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 26585104533 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9672004742 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558383242 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5338553005 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10896936247 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.189149 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.746347 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.648936 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813285 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231718 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 183500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution @@ -1441,8 +1496,8 @@ system.cpu1.dcache.tags.total_refs 161270449 # To system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 426.107402 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id @@ -1451,93 +1506,93 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 83489779 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 73474609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 71990 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1908367 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1854336 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 156964388 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 156964388 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 4311289 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2366929 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 476593 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 141331 # number of LoadLockedReq misses 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-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 60722587231 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 38093191666 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 11613108236 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1977833980 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3982712056 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2357000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 98815778897 # number of demand (read+write) miss cycles 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system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 548583 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2049698 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2048188 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 163642606 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 163642606 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.049103 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.031209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.868771 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.068952 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.094646 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.040810 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.040810 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1549,91 +1604,91 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits 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of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1368730 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1368730 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1368730 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3913497 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3913497 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1395991 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1395991 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 476533 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 476533 # number of WriteInvalidateReq MSHR misses system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 141284 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141284 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193784 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5309488 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5309488 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5309488 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5309488 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 46779736993 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46779736993 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20386885918 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20386885918 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 10653380764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10653380764 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1693632498 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3584420895 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67166622911 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 67166622911 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 548139751 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 613571252 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1161711003 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 9215030 # number of replacements @@ -1744,12 +1799,14 @@ system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # C system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id @@ -1776,141 +1833,159 @@ system.cpu1.l2cache.tags.tag_accesses 321109712 # Nu system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11678610 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of 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miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.573995 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.573995 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.639408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.639408 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.784248 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784248 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency 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latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution @@ -2344,20 +2438,24 @@ system.l2c.tags.warmup_cycle 8003493500 # Cy system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7682.914611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy 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MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9732785245 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5045750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 897969250 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.207448 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.198415 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.775863 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.467828 # mshr miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.601667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.583921 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.584394 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585970 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.576077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508392 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 969598 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 3ebfb1ad5..f3459bbfc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,47 +4,51 @@ sim_seconds 51.728175 # Nu sim_ticks 51728174627500 # Number of ticks simulated final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184836 # Simulator instruction rate (inst/s) -host_op_rate 217188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10028441874 # Simulator tick rate (ticks/s) -host_mem_usage 718288 # Number of bytes of host memory used -host_seconds 5158.15 # Real time elapsed on the host +host_inst_rate 121986 # Simulator instruction rate (inst/s) +host_op_rate 143338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6618487836 # Simulator tick rate (ticks/s) +host_mem_usage 708088 # Number of bytes of host memory used +host_seconds 7815.71 # Real time elapsed on the host sim_insts 953410832 # Number of instructions simulated sim_ops 1120287994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1230983 # Number of read requests accepted @@ -311,17 +315,21 @@ system.physmem_1.memoryStateTime::REF 1727317280000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). @@ -526,8 +534,8 @@ system.cpu.dcache.tags.total_refs 331084794 # To system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id @@ -537,89 +545,89 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # number of WriteInvalidateReq hits system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4114364 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4358642 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 322224479 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 322224479 # number of overall hits system.cpu.dcache.overall_hits::total 322224479 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 8085158 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 4338895 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4338895 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245002 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245002 # number of WriteInvalidateReq misses system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246013 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 246013 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 12424053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 12424053 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 12424053 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 12424053 # number of overall misses system.cpu.dcache.overall_misses::total 12424053 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128824080247 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128824080247 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 144514675403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 144514675403 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29607413192 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 29607413192 # number of WriteInvalidateReq miss cycles system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3571422003 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3571422003 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 273338755650 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 273338755650 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 273338755650 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 273338755650 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 177856096 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 177856096 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 156792436 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156792436 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1582500 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1582500 # number of WriteInvalidateReq accesses(hits+misses) system.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4360377 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4360377 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4358644 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4358644 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 334648532 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 334648532 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 334648532 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 334648532 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045459 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027673 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027673 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.786731 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786731 # miss rate for WriteInvalidateReq accesses system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056420 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056420 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.037126 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037126 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.037126 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037126 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15933.402940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15933.402940 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33306.792490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33306.792490 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23781.016570 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 23781.016570 # average WriteInvalidateReq miss latency system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14517.208452 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14517.208452 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -631,85 +639,85 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks system.cpu.dcache.writebacks::total 8593512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 755938 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 755938 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1899458 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1899458 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 141 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 141 # number of WriteInvalidateReq MSHR hits system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2655396 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2655396 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2655396 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2655396 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7329220 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7329220 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2439437 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2439437 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244861 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244861 # number of WriteInvalidateReq MSHR misses system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246009 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246009 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9768657 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9768657 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR 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cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5585117500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5585117500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11312933499 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11312933499 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041209 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041209 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015558 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015558 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.786642 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786642 # mshr miss rate for WriteInvalidateReq accesses system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056419 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056419 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13988.652101 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30209.600192 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21781.079621 # average WriteInvalidateReq mshr miss latency system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12510.001654 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24725990 # number of replacements @@ -814,11 +822,13 @@ system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cy system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 28524.406895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8071.479946 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20452.926949 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.435248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.312087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id @@ -834,125 +844,143 @@ system.cpu.l2cache.tags.tag_accesses 371551924 # Nu system.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 31858848 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 24618722 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7240126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 704117 # number of WriteInvalidateReq hits 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719318 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 719318 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 1161996 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 107787 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1054209 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 1161996 # number of overall misses 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WriteInvalidateReq miss cycles system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 431949947 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431949947 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 53534470118 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53534470118 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 86895985079 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7986963739 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 78909021340 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 86895985079 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7986963739 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 78909021340 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 32301526 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24726509 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7575017 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback 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-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 0f19127f8..fdc0fba9d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125948 # Number of seconds simulated -sim_ticks 5125948496500 # Number of ticks simulated -final_tick 5125948496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.129943 # Number of seconds simulated +sim_ticks 5129943020500 # Number of ticks simulated +final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181287 # Simulator instruction rate (inst/s) -host_op_rate 358347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2277524092 # Simulator tick rate (ticks/s) -host_mem_usage 808864 # Number of bytes of host memory used -host_seconds 2250.67 # Real time elapsed on the host -sim_insts 408017153 # Number of instructions simulated -sim_ops 806519171 # Number of ops (including micro ops) simulated +host_inst_rate 121408 # Simulator instruction rate (inst/s) +host_op_rate 239988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1526556123 # Simulator tick rate (ticks/s) +host_mem_usage 798272 # Number of bytes of host memory used +host_seconds 3360.47 # Real time elapsed on the host +sim_insts 407987808 # Number of instructions simulated +sim_ops 806471132 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1048640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10814912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11896448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1048640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1048640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9598912 # Number of bytes written to this memory -system.physmem.bytes_written::total 9598912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168983 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory +system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149983 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149983 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2109836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2320829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1872612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1872612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1872612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2109836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4193440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185882 # Number of read requests accepted -system.physmem.writeReqs 196703 # Number of write requests accepted -system.physmem.readBursts 185882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196703 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11884864 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue -system.physmem.bytesWritten 12459008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11896448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12588992 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2006 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1725 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11442 # Per bank write bursts -system.physmem.perBankRdBursts::1 11010 # Per bank write bursts -system.physmem.perBankRdBursts::2 11990 # Per bank write bursts -system.physmem.perBankRdBursts::3 11673 # Per bank write bursts -system.physmem.perBankRdBursts::4 12100 # Per bank write bursts -system.physmem.perBankRdBursts::5 11243 # Per bank write bursts -system.physmem.perBankRdBursts::6 11527 # Per bank write bursts -system.physmem.perBankRdBursts::7 11544 # Per bank write bursts -system.physmem.perBankRdBursts::8 11275 # Per bank write bursts -system.physmem.perBankRdBursts::9 11901 # Per bank write bursts -system.physmem.perBankRdBursts::10 11758 # Per bank write bursts -system.physmem.perBankRdBursts::11 11788 # Per bank write bursts -system.physmem.perBankRdBursts::12 11617 # Per bank write bursts -system.physmem.perBankRdBursts::13 12244 # Per bank write bursts -system.physmem.perBankRdBursts::14 11799 # Per bank write bursts -system.physmem.perBankRdBursts::15 10790 # Per bank write bursts -system.physmem.perBankWrBursts::0 14290 # Per bank write bursts -system.physmem.perBankWrBursts::1 13466 # Per bank write bursts -system.physmem.perBankWrBursts::2 12356 # Per bank write bursts -system.physmem.perBankWrBursts::3 11306 # Per bank write bursts -system.physmem.perBankWrBursts::4 11781 # Per bank write bursts -system.physmem.perBankWrBursts::5 11472 # Per bank write bursts -system.physmem.perBankWrBursts::6 11444 # Per bank write bursts -system.physmem.perBankWrBursts::7 11849 # Per bank write bursts -system.physmem.perBankWrBursts::8 11105 # Per bank write bursts -system.physmem.perBankWrBursts::9 11337 # Per bank write bursts -system.physmem.perBankWrBursts::10 12902 # Per bank write bursts -system.physmem.perBankWrBursts::11 12297 # Per bank write bursts -system.physmem.perBankWrBursts::12 12359 # Per bank write bursts -system.physmem.perBankWrBursts::13 12104 # Per bank write bursts -system.physmem.perBankWrBursts::14 12504 # Per bank write bursts -system.physmem.perBankWrBursts::15 12100 # Per bank write bursts +system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185604 # Number of read requests accepted +system.physmem.writeReqs 196636 # Number of write requests accepted +system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue +system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11483 # Per bank write bursts +system.physmem.perBankRdBursts::1 10958 # Per bank write bursts +system.physmem.perBankRdBursts::2 11903 # Per bank write bursts +system.physmem.perBankRdBursts::3 11497 # Per bank write bursts +system.physmem.perBankRdBursts::4 11986 # Per bank write bursts +system.physmem.perBankRdBursts::5 11369 # Per bank write bursts +system.physmem.perBankRdBursts::6 11563 # Per bank write bursts +system.physmem.perBankRdBursts::7 11462 # Per bank write bursts +system.physmem.perBankRdBursts::8 11178 # Per bank write bursts +system.physmem.perBankRdBursts::9 11812 # Per bank write bursts +system.physmem.perBankRdBursts::10 11732 # Per bank write bursts +system.physmem.perBankRdBursts::11 11823 # Per bank write bursts +system.physmem.perBankRdBursts::12 11783 # Per bank write bursts +system.physmem.perBankRdBursts::13 12309 # Per bank write bursts +system.physmem.perBankRdBursts::14 11732 # Per bank write bursts +system.physmem.perBankRdBursts::15 10811 # Per bank write bursts +system.physmem.perBankWrBursts::0 14023 # Per bank write bursts +system.physmem.perBankWrBursts::1 13077 # Per bank write bursts +system.physmem.perBankWrBursts::2 12485 # Per bank write bursts +system.physmem.perBankWrBursts::3 11134 # Per bank write bursts +system.physmem.perBankWrBursts::4 11942 # Per bank write bursts +system.physmem.perBankWrBursts::5 11710 # Per bank write bursts +system.physmem.perBankWrBursts::6 11692 # Per bank write bursts +system.physmem.perBankWrBursts::7 11673 # Per bank write bursts +system.physmem.perBankWrBursts::8 11519 # Per bank write bursts +system.physmem.perBankWrBursts::9 11764 # Per bank write bursts +system.physmem.perBankWrBursts::10 12914 # Per bank write bursts +system.physmem.perBankWrBursts::11 11938 # Per bank write bursts +system.physmem.perBankWrBursts::12 12257 # Per bank write bursts +system.physmem.perBankWrBursts::13 11913 # Per bank write bursts +system.physmem.perBankWrBursts::14 12398 # Per bank write bursts +system.physmem.perBankWrBursts::15 11971 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5125948445000 # Total gap between requests +system.physmem.totGap 5129942968500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185882 # Read request sizes (log2) +system.physmem.readPktSize::6 185604 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196703 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196636 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see @@ -156,322 +156,323 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.488559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.903299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.428888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27891 37.06% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17298 22.99% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7596 10.09% 70.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4208 5.59% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3159 4.20% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2000 2.66% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1345 1.79% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1163 1.55% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10594 14.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75254 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7808 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.780866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.702276 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7807 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7808 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.932377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.361157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.539970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6379 81.70% 81.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.63% 82.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.12% 82.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 259 3.32% 85.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.39% 88.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.68% 88.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.44% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 61 0.78% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 178 2.28% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.24% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.17% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 27 0.35% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.24% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 50 0.64% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 97 1.24% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.10% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 20 0.26% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 156 2.00% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 7 0.09% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 10 0.13% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 29 0.37% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.14% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.05% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.20% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 10 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.14% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.13% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 7 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7808 # Writes before turning the bus around for reads -system.physmem.totQLat 1993300749 # Total ticks spent queuing -system.physmem.totMemAccLat 5475194499 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10733.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads +system.physmem.totQLat 1998636250 # Total ticks spent queuing +system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29483.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.46 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.04 # Average write queue length when enqueuing -system.physmem.readRowHits 152642 # Number of row buffer hits during reads -system.physmem.writeRowHits 152476 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.31 # Row buffer hit rate for writes -system.physmem.avgGap 13398195.03 # Average gap between requests -system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 279704880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 152616750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721718400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 634806720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129444104115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2962019880750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3428054662095 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.765327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4927513863750 # Time in different power states -system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing +system.physmem.readRowHits 152292 # Number of row buffer hits during reads +system.physmem.writeRowHits 152229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes +system.physmem.avgGap 13420738.20 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764961 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states +system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27267949750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 289215360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 157806000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726741600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 626667840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129734124390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2961765477000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3428101862670 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.774535 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4927089550750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.773213 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states +system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27689450500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86963954 # Number of BP lookups -system.cpu.branchPred.condPredicted 86963954 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 905408 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80060833 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78220075 # Number of BTB hits +system.cpu.branchPred.lookups 86966196 # Number of BP lookups +system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.700801 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1554669 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179026 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449722784 # number of cpu cycles simulated +system.cpu.numCycles 449725865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27725020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429300438 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86963954 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79774744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417978242 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1899598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 143976 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 212054 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 124897 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 365 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9198894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 449574 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4910 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447183567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281562684 62.96% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2296710 0.51% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72185404 16.14% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1608090 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2152491 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328628 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1534045 0.34% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1900420 0.42% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81615095 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447183567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23075597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264910108 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150816162 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7431901 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 949799 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838865197 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 949799 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25926245 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223342995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13219671 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154710115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29034742 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835373495 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 478818 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12412845 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 182552 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13765619 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997850152 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814454577 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115386152 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 142 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964539686 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33310464 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 472576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39019315 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17353635 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10197147 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1310615 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1095058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829813890 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1210662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824509848 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 239912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23585262 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36379120 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447183567 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418075 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262867260 58.78% 58.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13875410 3.10% 61.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10102524 2.26% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6917845 1.55% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74366987 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4460507 1.00% 83.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72819289 16.28% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1200322 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573423 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447183567 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1986412 71.97% 71.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 252 0.01% 71.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1233 0.04% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 612541 22.19% 94.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159591 5.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292966 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796097417 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150721 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125468 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued @@ -498,98 +499,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18437939 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9405337 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824509848 # Type of FU issued -system.cpu.iq.rate 1.833374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2760029 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099202980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854622338 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819935754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826976810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1879265 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued +system.cpu.iq.rate 1.833352 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3349902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15405 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14537 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1763571 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72078 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 949799 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205606066 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9444034 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831024552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 186671 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17353635 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10197147 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 713788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 414805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8129418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14537 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 518368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 539118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1057486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822883825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18037381 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1492626 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27216272 # number of memory reference insts executed -system.cpu.iew.exec_branches 83330623 # Number of branches executed -system.cpu.iew.exec_stores 9178891 # Number of stores executed -system.cpu.iew.exec_rate 1.829758 # Inst execution rate -system.cpu.iew.wb_sent 822374066 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819935816 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641195588 # num instructions producing a value -system.cpu.iew.wb_consumers 1050795800 # num instructions consuming a value +system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed +system.cpu.iew.exec_branches 83327917 # Number of branches executed +system.cpu.iew.exec_stores 9177504 # Number of stores executed +system.cpu.iew.exec_rate 1.829721 # Inst execution rate +system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641186937 # num instructions producing a value +system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610200 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24410170 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055982 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 917776 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443513895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675053 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272662791 61.48% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11205596 2.53% 64.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3584252 0.81% 64.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74566158 16.81% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433850 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1609395 0.36% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 952580 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71045442 16.02% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5453831 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443513895 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408017153 # Number of instructions committed -system.cpu.commit.committedOps 806519171 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407987808 # Number of instructions committed +system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22437308 # Number of memory references committed -system.cpu.commit.loads 14003732 # Number of loads committed -system.cpu.commit.membars 475345 # Number of memory barriers committed -system.cpu.commit.branches 82208289 # Number of branches committed +system.cpu.commit.refs 22432051 # Number of memory references committed +system.cpu.commit.loads 14002440 # Number of loads committed +system.cpu.commit.membars 475347 # Number of memory barriers committed +system.cpu.commit.branches 82201961 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735327062 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156001 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174296 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783640915 97.16% 97.18% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145051 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121601 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735281139 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155976 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -616,167 +617,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 14003732 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8433576 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806519171 # Class of committed instruction -system.cpu.commit.bw_lim_events 5453831 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction +system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268911189 # The number of ROB reads -system.cpu.rob.rob_writes 1665544826 # The number of ROB writes -system.cpu.timesIdled 297395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2539217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9802174458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408017153 # Number of Instructions Simulated -system.cpu.committedOps 806519171 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102215 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907264 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907264 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092796597 # number of integer regfile reads -system.cpu.int_regfile_writes 656284247 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.cc_regfile_reads 416355955 # number of cc regfile reads -system.cpu.cc_regfile_writes 322152728 # number of cc regfile writes -system.cpu.misc_regfile_reads 265715662 # number of misc regfile reads -system.cpu.misc_regfile_writes 402877 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1660514 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996956 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19150908 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1661026 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.529565 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1268912158 # The number of ROB reads +system.cpu.rob.rob_writes 1665595320 # The number of ROB writes +system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407987808 # Number of Instructions Simulated +system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads +system.cpu.int_regfile_writes 656276714 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads +system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes +system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads +system.cpu.misc_regfile_writes 402822 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1660901 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996956 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88414778 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88414778 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10992291 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10992291 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8090245 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8090245 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65628 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65628 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19082536 # 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# average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.489862 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38578.653610 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38578.653610 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18468.221681 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18468.221681 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15514.221771 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15514.221771 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 376585 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 40008 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 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mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38708.934608 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13874.573459 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13874.573459 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18608.815838 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18608.815838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17462.154406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17462.154406 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -784,58 +785,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73235 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.785723 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 116281 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73250 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.587454 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785723 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986608 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986608 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 455451 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 455451 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116283 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 116283 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116283 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 116283 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116283 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 116283 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74295 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74295 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74295 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74295 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74295 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74295 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 915742192 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 915742192 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 915742192 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 915742192 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 915742192 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 915742192 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190578 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190578 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190578 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190578 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190578 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190578 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389840 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389840 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389840 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389840 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389840 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389840 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12325.758019 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12325.758019 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12325.758019 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,180 +845,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 20236 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 20236 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74295 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74295 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74295 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74295 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74295 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74295 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 767004478 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 767004478 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 767004478 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 767004478 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 767004478 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 767004478 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389840 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389840 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389840 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10323.769810 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000725 # number of replacements -system.cpu.icache.tags.tagsinuse 510.147155 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8133580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1001237 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.123531 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1000738 # number of replacements +system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.147155 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996381 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996381 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10200177 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10200177 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8133580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8133580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8133580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8133580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8133580 # number of overall hits -system.cpu.icache.overall_hits::total 8133580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065313 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065313 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065313 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065313 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065313 # number of overall misses -system.cpu.icache.overall_misses::total 1065313 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14771324125 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14771324125 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14771324125 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14771324125 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14771324125 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14771324125 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9198893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9198893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9198893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9198893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9198893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9198893 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115809 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115809 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115809 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115809 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115809 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115809 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.712823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13865.712823 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.712823 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13865.712823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.712823 # average overall miss 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of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12129331538 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12129331538 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12129331538 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12129331538 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12129331538 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12129331538 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108719 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108719 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108719 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.595977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.595977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14176 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.015804 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26673 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14191 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.879572 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101167924000 # Cycle when the warmup percentage was hit. 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per task id -system.cpu.itb_walker_cache.tags.tag_accesses 98532 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 98532 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26674 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26674 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 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# number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16998 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 16998 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16998 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 16998 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16998 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 16998 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 202038998 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 202038998 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 202038998 # number of demand (read+write) miss cycles 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11886.045299 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11886.045299 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,177 +1027,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2894 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2894 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15060 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15060 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15060 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15060 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15060 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15060 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144633033 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144633033 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144633033 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144633033 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144633033 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144633033 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360857 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360857 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.360840 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.360840 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.360840 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.360840 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9603.787052 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9603.787052 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9603.787052 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2256 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2256 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16998 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16998 # number of ReadReq MSHR misses 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miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 113005 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64819.841328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3843950 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 177067 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.709014 # Average number of references to valid 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per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170129 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64062 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52637 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35098786 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35098786 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 984793 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1337105 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2402250 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1584244 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1584244 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 297 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 297 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 153417 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 153417 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 67803 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 984793 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1490522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2555667 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 984793 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1490522 # number of overall hits -system.cpu.l2cache.overall_hits::total 2555667 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16386 # number of ReadReq misses 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overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16386 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169930 # number of overall misses -system.cpu.l2cache.overall_misses::total 186387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6099500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 482500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1248819000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2837713246 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4093114246 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17341312 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17341312 # number of UpgradeReq miss cycles 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miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12188750964 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13444151964 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67868 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1372965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2454567 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1584244 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1584244 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses) 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.466352 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000478 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016367 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102340 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.067973 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000478 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016367 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102340 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.067973 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93838.461538 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80416.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76212.559502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79133.107808 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78236.791980 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.362517 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.362517 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69747.428343 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69747.428343 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93838.461538 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80416.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76212.559502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71728.070170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72130.309324 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93838.461538 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80416.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76212.559502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71728.070170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72130.309324 # average overall miss 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latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency 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MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169649 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 186114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 68 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16392 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169649 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186114 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5576250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 344500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049607750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2389031498 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3444559998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15363423 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15363423 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7651301287 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7651301287 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5576250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049607750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10040332785 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11095861285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5576250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049607750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10040332785 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11095861285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397352000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397352000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672948500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672948500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021290 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827982 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827982 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465820 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465820 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067767 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067767 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64031.707540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66559.816622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65788.609152 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10639.489612 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10639.489612 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57203.424796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57203.424796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1305,55 +1306,55 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3074514 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3073974 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1584244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6133560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30509 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8328931 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64075456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207996475 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 988736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5638656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278699323 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 58087 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4385762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010862 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103651 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 57093 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4338126 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47636 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4385762 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4071958893 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1506070002 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3144166318 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22600980 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 111516357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225687 # Transaction distribution -system.iobus.trans_dist::ReadResp 225687 # Transaction distribution +system.iobus.trans_dist::ReadReq 225688 # Transaction distribution +system.iobus.trans_dist::ReadResp 225688 # Transaction distribution system.iobus.trans_dist::WriteReq 57721 # Transaction distribution system.iobus.trans_dist::WriteResp 11001 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1378,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) @@ -1402,12 +1403,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276506 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1443,54 +1444,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448361200 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52371753 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47581 # number of replacements -system.iocache.tags.tagsinuse 0.091546 # Cycle average of tags in use +system.iocache.tags.replacements 47582 # number of replacements +system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992992715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091546 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005722 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005722 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428724 # Number of tag accesses -system.iocache.tags.data_accesses 428724 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses -system.iocache.ReadReq_misses::total 916 # number of ReadReq misses +system.iocache.tags.tag_accesses 428733 # Number of tag accesses +system.iocache.tags.data_accesses 428733 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses +system.iocache.ReadReq_misses::total 917 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses -system.iocache.demand_misses::total 916 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses -system.iocache.overall_misses::total 916 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149161446 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149161446 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12345702001 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12345702001 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149161446 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149161446 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149161446 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149161446 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses +system.iocache.demand_misses::total 917 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses +system.iocache.overall_misses::total 917 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles +system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1499,40 +1500,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162840.006550 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162840.006550 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162840.006550 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70237 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9120 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.701425 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101504946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9916256007 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9916256007 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101504946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101504946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1541,75 +1542,75 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662646 # Transaction distribution -system.membus.trans_dist::ReadResp 662640 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 149983 # Transaction distribution +system.membus.trans_dist::ReadReq 662691 # Transaction distribution +system.membus.trans_dist::ReadResp 662685 # Transaction distribution +system.membus.trans_dist::WriteReq 13891 # Transaction distribution +system.membus.trans_dist::WriteResp 13891 # Transaction distribution +system.membus.trans_dist::Writeback 149916 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2187 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1743 # Transaction distribution -system.membus.trans_dist::ReadExReq 133791 # Transaction distribution -system.membus.trans_dist::ReadExResp 133789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution +system.membus.trans_dist::ReadExReq 133471 # Transaction distribution +system.membus.trans_dist::ReadExResp 133469 # Transaction distribution system.membus.trans_dist::MessageReq 1644 # Transaction distribution system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1725388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1870142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18480320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20272507 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26284203 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1595 # Total snoops (count) -system.membus.snoop_fanout::samples 385911 # Request fanout histogram +system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1626 # Total snoops (count) +system.membus.snoop_fanout::samples 385584 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385911 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385911 # Request fanout histogram -system.membus.reqLayer0.occupancy 251714500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 385584 # Request fanout histogram +system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583067000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1996777999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3163999272 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54979247 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini index c9ccea56d..2f7786e68 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini @@ -705,7 +705,7 @@ header_cycles=1 use_default_range=false width=8 default=system.pc.pciconfig.pio -master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave +master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port [system.mem_ctrls] @@ -787,7 +787,7 @@ port=system.ruby.dir_cntrl0.memory [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge eventq_index=0 intrctrl=system.intrctrl system=system @@ -808,7 +808,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[11] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -820,7 +820,7 @@ pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.master[12] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -846,7 +846,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[13] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -864,7 +864,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[14] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -882,7 +882,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[15] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -900,9 +900,9 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[16] +pio=system.iobus.master[17] -[system.pc.i_dont_exist] +[system.pc.i_dont_exist1] type=IsaFake clk_domain=system.clk_domain eventq_index=0 @@ -920,6 +920,24 @@ update_data=false warn_access= pio=system.iobus.master[10] +[system.pc.i_dont_exist2] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=9223372036854776045 +pio_latency=100000 +pio_size=1 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[11] + [system.pc.pciconfig] type=PciConfigAll bus=0 @@ -1397,7 +1415,7 @@ ruby_system=system.ruby system=system using_ruby_tester=false version=1 -slave=system.iobus.master[19] +slave=system.iobus.master[20] [system.ruby.l1_cntrl0] type=L1Cache_Controller @@ -1416,7 +1434,7 @@ number_of_TBEs=256 prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl0.sequencer system=system to_l2_latency=1 @@ -1489,7 +1507,7 @@ version=0 master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave mem_master_port=system.iobus.slave[2] pio_master_port=system.iobus.slave[1] -pio_slave_port=system.iobus.master[17] +pio_slave_port=system.iobus.master[18] slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master [system.ruby.l1_cntrl1] @@ -1509,7 +1527,7 @@ number_of_TBEs=256 prefetcher=system.ruby.l1_cntrl1.prefetcher recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl1.sequencer system=system to_l2_latency=1 @@ -1582,7 +1600,7 @@ version=1 master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave mem_master_port=system.iobus.slave[4] pio_master_port=system.iobus.slave[3] -pio_slave_port=system.iobus.master[18] +pio_slave_port=system.iobus.master[19] slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master [system.ruby.l2_cntrl0] diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 77c265ccb..89d9becf2 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,74 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.221319 # Number of seconds simulated -sim_ticks 4442638390 # Number of ticks simulated -final_tick 4442638390 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.233778 # Number of seconds simulated +sim_ticks 4467555024 # Number of ticks simulated +final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 1901707 # Simulator instruction rate (inst/s) -host_op_rate 1902455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3812734 # Simulator tick rate (ticks/s) -host_mem_usage 568684 # Number of bytes of host memory used -host_seconds 1165.21 # Real time elapsed on the host -sim_insts 2215889371 # Number of instructions simulated -sim_ops 2216760815 # Number of ops (including micro ops) simulated +host_inst_rate 1794168 # Simulator instruction rate (inst/s) +host_op_rate 1794873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3597181 # Simulator tick rate (ticks/s) +host_mem_usage 569892 # Number of bytes of host memory used +host_seconds 1241.96 # Real time elapsed on the host +sim_insts 2228284650 # Number of instructions simulated +sim_ops 2229160714 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 2 # Clock period in ticks system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.bw_read::cpu.data 7559 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_read::total 7559 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total::cpu.data 7559 # Total bandwidth to/from this memory (bytes/s) -system.hypervisor_desc.bw_total::total 7559 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory -system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory -system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory -system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory -system.partition_desc.bw_read::cpu.data 2182 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_read::total 2182 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total::cpu.data 2182 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bw_total::total 2182 # Total bandwidth to/from this memory (bytes/s) -system.physmem1.bytes_read::cpu.inst 8278734588 # Number of bytes read from this memory -system.physmem1.bytes_read::cpu.data 1487826857 # Number of bytes read from this memory -system.physmem1.bytes_read::total 9766561445 # Number of bytes read from this memory -system.physmem1.bytes_inst_read::cpu.inst 8278734588 # Number of instructions bytes read from this memory -system.physmem1.bytes_inst_read::total 8278734588 # Number of instructions bytes read from this memory -system.physmem1.bytes_written::cpu.data 890413424 # Number of bytes written to this memory -system.physmem1.bytes_written::total 890413424 # Number of bytes written to this memory -system.physmem1.num_reads::cpu.inst 2069683647 # Number of read requests responded to by this memory -system.physmem1.num_reads::cpu.data 322864285 # Number of read requests responded to by this memory -system.physmem1.num_reads::total 2392547932 # Number of read requests responded to by this memory -system.physmem1.num_writes::cpu.data 186352766 # Number of write requests responded to by this memory -system.physmem1.num_writes::total 186352766 # Number of write requests responded to by this memory -system.physmem1.num_other::cpu.data 5352814 # Number of other requests responded to by this memory -system.physmem1.num_other::total 5352814 # Number of other requests responded to by this memory -system.physmem1.bw_read::cpu.inst 3726945054 # Total read bandwidth from this memory (bytes/s) -system.physmem1.bw_read::cpu.data 669794265 # Total read bandwidth from this memory (bytes/s) -system.physmem1.bw_read::total 4396739319 # Total read bandwidth from this memory (bytes/s) -system.physmem1.bw_inst_read::cpu.inst 3726945054 # Instruction read bandwidth from this memory (bytes/s) -system.physmem1.bw_inst_read::total 3726945054 # Instruction read bandwidth from this memory (bytes/s) -system.physmem1.bw_write::cpu.data 400848931 # Write bandwidth from this memory (bytes/s) -system.physmem1.bw_write::total 400848931 # Write bandwidth from this memory (bytes/s) -system.physmem1.bw_total::cpu.inst 3726945054 # Total bandwidth to/from this memory (bytes/s) -system.physmem1.bw_total::cpu.data 1070643195 # Total bandwidth to/from this memory (bytes/s) -system.physmem1.bw_total::total 4797588250 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 194612 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 313504 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 508116 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 194612 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 194612 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 194612 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 313504 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 508116 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory system.nvram.bytes_read::total 284 # Number of bytes read from this memory system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory @@ -77,87 +29,149 @@ system.nvram.num_reads::cpu.data 284 # Nu system.nvram.num_reads::total 284 # Number of read requests responded to by this memory system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 128 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 128 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 169 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 169 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bytes_read::cpu.inst 601850192 # Number of bytes read from this memory -system.physmem0.bytes_read::cpu.data 95637362 # Number of bytes read from this memory -system.physmem0.bytes_read::total 697487554 # Number of bytes read from this memory -system.physmem0.bytes_inst_read::cpu.inst 601850192 # Number of instructions bytes read from this memory -system.physmem0.bytes_inst_read::total 601850192 # Number of instructions bytes read from this memory -system.physmem0.bytes_written::cpu.data 15105383 # Number of bytes written to this memory -system.physmem0.bytes_written::total 15105383 # Number of bytes written to this memory -system.physmem0.num_reads::cpu.inst 150462548 # Number of read requests responded to by this memory -system.physmem0.num_reads::cpu.data 11907116 # Number of read requests responded to by this memory -system.physmem0.num_reads::total 162369664 # Number of read requests responded to by this memory -system.physmem0.num_writes::cpu.data 1890212 # Number of write requests responded to by this memory -system.physmem0.num_writes::total 1890212 # Number of write requests responded to by this memory +system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory +system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory +system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory +system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory +system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) +system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory +system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory +system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory +system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory +system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory +system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory +system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory +system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory +system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory +system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory +system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory +system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory system.physmem0.num_other::total 14 # Number of other requests responded to by this memory -system.physmem0.bw_read::cpu.inst 270942687 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_read::cpu.data 43054309 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_read::total 313996996 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_inst_read::cpu.inst 270942687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem0.bw_inst_read::total 270942687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem0.bw_write::cpu.data 6800186 # Write bandwidth from this memory (bytes/s) -system.physmem0.bw_write::total 6800186 # Write bandwidth from this memory (bytes/s) -system.physmem0.bw_total::cpu.inst 270942687 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bw_total::cpu.data 49854494 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bw_total::total 320797182 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 2559471185 # Transaction distribution -system.membus.trans_dist::ReadResp 2559471185 # Transaction distribution -system.membus.trans_dist::WriteReq 188250351 # Transaction distribution -system.membus.trans_dist::WriteResp 188250351 # Transaction distribution -system.membus.trans_dist::SwapReq 5352828 # Transaction distribution -system.membus.trans_dist::SwapResp 5352828 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 300925096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4139367294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 4440508538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8711566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 27594684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1029139730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1065640190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5506148728 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 601850192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8278734588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8881017076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34744011 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 110742969 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2439206055 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 2585411825 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11466428901 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2753074364 # Request fanout histogram -system.membus.snoop_fanout::mean 0.806464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.395070 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 532820095 19.35% 19.35% # Request fanout histogram -system.membus.snoop_fanout::1 2220254269 80.65% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2753074364 # Request fanout histogram -system.iobus.trans_dist::ReadReq 4348534 # Transaction distribution -system.iobus.trans_dist::ReadResp 4348534 # Transaction distribution -system.iobus.trans_dist::WriteReq 7249 # Transaction distribution -system.iobus.trans_dist::WriteResp 7249 # Transaction distribution +system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) +system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) +system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) +system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory +system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory +system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory +system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory +system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory +system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory +system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory +system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory +system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory +system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory +system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory +system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory +system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory +system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory +system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) +system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) +system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) +system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) +system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) +system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 2 # Clock period in ticks +system.cpu.numCycles 2233777513 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2228284650 # Number of instructions committed +system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses +system.cpu.num_func_calls 44037246 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls +system.cpu.num_int_insts 1839325658 # number of integer instructions +system.cpu.num_fp_insts 14608322 # number of float instructions +system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read +system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read +system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written +system.cpu.num_mem_refs 547951940 # number of memory refs +system.cpu.num_load_insts 349807670 # Number of load instructions +system.cpu.num_store_insts 198144270 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 2233777513 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 441057355 # Number of branches fetched +system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction +system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction +system.cpu.op_class::MemRead 356274529 15.95% 91.04% # Class of executed instruction +system.cpu.op_class::MemWrite 200199782 8.96% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2233583679 # Class of executed instruction +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution +system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution +system.iobus.trans_dist::WriteReq 7569 # Transaction distribution +system.iobus.trans_dist::WriteResp 7569 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes) @@ -168,10 +182,10 @@ system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 8711566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes) @@ -182,70 +196,56 @@ system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14589 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34728964 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 34744011 # Cumulative packet size per connected master and slave (bytes) -system.cpu_clk_domain.clock 2 # Clock period in ticks -system.cpu.numCycles 2221319196 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2215889371 # Number of instructions committed -system.cpu.committedOps 2216760815 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1828751674 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 14599184 # Number of float alu accesses -system.cpu.num_func_calls 43845838 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 314910579 # number of instructions that are conditional controls -system.cpu.num_int_insts 1828751674 # number of integer instructions -system.cpu.num_fp_insts 14599184 # number of float instructions -system.cpu.num_int_register_reads 4280788221 # number of times the integer registers were read -system.cpu.num_int_register_writes 2088786554 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35382311 # number of times the floating registers were read -system.cpu.num_fp_register_writes 22904834 # number of times the floating registers were written -system.cpu.num_mem_refs 545231836 # number of memory refs -system.cpu.num_load_insts 348274583 # Number of load instructions -system.cpu.num_store_insts 196957253 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2221319196 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 439059324 # Number of branches fetched -system.cpu.op_class::No_OpClass 49315635 2.22% 2.22% # Class of executed instruction -system.cpu.op_class::IntAlu 1609688995 72.47% 74.69% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.69% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.69% # Class of executed instruction -system.cpu.op_class::FloatAdd 8416009 0.38% 75.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.07% # Class of executed instruction -system.cpu.op_class::MemRead 354694578 15.97% 91.04% # Class of executed instruction -system.cpu.op_class::MemWrite 199010496 8.96% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2221125713 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution +system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution +system.membus.trans_dist::WriteReq 189322556 # Transaction distribution +system.membus.trans_dist::WriteResp 189322556 # Transaction distribution +system.membus.trans_dist::SwapReq 5403081 # Transaction distribution +system.membus.trans_dist::SwapResp 5403081 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram +system.membus.snoop_fanout::mean 0.806616 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.394951 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 535285646 19.34% 19.34% # Request fanout histogram +system.membus.snoop_fanout::1 2232707615 80.66% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2767993261 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 04ace1eeb..e8166ece0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 52746e018..4f1cfb81e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271090 # Simulator instruction rate (inst/s) -host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183993432 # Simulator tick rate (ticks/s) -host_mem_usage 445016 # Number of bytes of host memory used -host_seconds 334.22 # Real time elapsed on the host +host_inst_rate 144123 # Simulator instruction rate (inst/s) +host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97818525 # Simulator tick rate (ticks/s) +host_mem_usage 433504 # Number of bytes of host memory used +host_seconds 628.65 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::total 996800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 26267660 # To system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id @@ -400,61 +404,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -466,45 +470,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements @@ -599,9 +603,11 @@ system.cpu.l2cache.tags.sampled_refs 15558 # Sa system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id @@ -612,57 +618,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits 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demand (read+write) misses system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles 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+system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,43 +696,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 8fe365c4e..3203f61e7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 93f93a6a3..9abbba24f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.410940 # Nu sim_ticks 410940483000 # Number of ticks simulated final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339016 # Simulator instruction rate (inst/s) -host_op_rate 339016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 227676015 # Simulator tick rate (ticks/s) -host_mem_usage 297088 # Number of bytes of host memory used -host_seconds 1804.94 # Real time elapsed on the host +host_inst_rate 207244 # Simulator instruction rate (inst/s) +host_op_rate 207244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139181064 # Simulator tick rate (ticks/s) +host_mem_usage 283892 # Number of bytes of host memory used +host_seconds 2952.56 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377337 # Number of read requests responded to by this memory system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 416138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58766583 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 416138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58766583 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 380009 # Number of read requests accepted system.physmem.writeReqs 292569 # Number of write requests accepted @@ -339,8 +343,8 @@ system.cpu.dcache.tags.total_refs 202631199 # To system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.778260 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -350,53 +354,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 146964985 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666214 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 202631199 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 202631199 # number of overall hits system.cpu.dcache.overall_hits::total 202631199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1908330 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543820 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3452150 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3452150 # number of overall misses system.cpu.dcache.overall_misses::total 3452150 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36414832750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44905898000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81320730750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81320730750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 148873315 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206083349 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206083349 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19082.041759 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -408,45 +412,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks system.cpu.dcache.writebacks::total 2340060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143560 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769044 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912604 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912604 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912604 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764770 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774776 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774776 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539546 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539546 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539546 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30222614500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21167535500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51390150000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51390150000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17125.525989 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27320.845638 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3192 # number of replacements @@ -543,9 +547,11 @@ system.cpu.l2cache.tags.sampled_refs 379722 # Sa system.cpu.l2cache.tags.avg_refs 9.773324 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 188676425000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21419.098483 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.778788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.648433 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7901.130355 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.653659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005452 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.241123 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.900234 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id @@ -556,57 +562,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18831 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 40234870 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 40234870 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1593052 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2349 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1590703 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1593052 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2340060 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2340060 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571506 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 571506 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 571506 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164558 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2349 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2162209 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2164558 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164558 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2349 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2162209 # number of overall hits system.cpu.l2cache.overall_hits::total 2164558 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 173383 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2672 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 170711 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 173383 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206626 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206626 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206626 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 380009 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2672 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 377337 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 380009 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2672 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 377337 # number of overall misses system.cpu.l2cache.overall_misses::total 380009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672404250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189570250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12482834000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 12672404250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14718134000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14718134000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 14718134000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27390538250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 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accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2340060 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2340060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778132 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 778132 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 778132 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5021 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539546 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5021 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539546 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.532165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096917 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265541 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.532165 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.532165 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70946.949850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73122.610728 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71230.793801 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -618,37 +642,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 292569 # number of writebacks system.cpu.l2cache.writebacks::total 292569 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173383 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2672 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170711 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 173383 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206626 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206626 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377337 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155967750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10304871500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12089060000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 155967750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22393931500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 155967750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22393931500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096917 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265541 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58371.163922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60364.425843 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58506.964274 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 2fe2a523a..452217687 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index a1fa65b86..441853c88 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.365317 # Nu sim_ticks 365317233000 # Number of ticks simulated final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241300 # Simulator instruction rate (inst/s) -host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174011250 # Simulator tick rate (ticks/s) -host_mem_usage 315696 # Number of bytes of host memory used -host_seconds 2099.39 # Real time elapsed on the host +host_inst_rate 157262 # Simulator instruction rate (inst/s) +host_op_rate 170335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113407877 # Simulator tick rate (ticks/s) +host_mem_usage 304680 # Number of bytes of host memory used +host_seconds 3221.27 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144157 # Number of read requests accepted system.physmem.writeReqs 96561 # Number of write requests accepted @@ -428,8 +432,8 @@ system.cpu.dcache.tags.total_refs 171281876 # To system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id @@ -439,61 +443,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168304794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168304794 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits system.cpu.dcache.overall_hits::total 168304794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854755 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700596 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1555351 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1555351 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses system.cpu.dcache.overall_misses::total 1555351 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13707430482 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20521575250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34229005732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34229005732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 169860145 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 169860145 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009157 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009157 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency 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ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71026.561942 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71026.561942 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72103.668417 # average overall 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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 8a55cdea8..537f6d0ab 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index fd544a1a5..688c5f811 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.226819 # Nu sim_ticks 226818771000 # Number of ticks simulated final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333141 # Simulator instruction rate (inst/s) -host_op_rate 333141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189539219 # Simulator tick rate (ticks/s) -host_mem_usage 300760 # Number of bytes of host memory used -host_seconds 1196.69 # Real time elapsed on the host +host_inst_rate 207340 # Simulator instruction rate (inst/s) +host_op_rate 207340 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117965343 # Simulator tick rate (ticks/s) +host_mem_usage 287544 # Number of bytes of host memory used +host_seconds 1922.76 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 168028615 # To system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id @@ -318,53 +322,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168028615 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168028615 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits system.cpu.dcache.overall_hits::total 168028615 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168035734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168035734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -376,45 +380,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2743 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements @@ -510,9 +514,11 @@ system.cpu.l2cache.tags.sampled_refs 5273 # Sa system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id @@ -522,57 +528,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 88415 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 88415 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1405 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1279 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1405 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1466 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1279 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1466 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1466 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1279 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits system.cpu.l2cache.overall_hits::total 1466 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4736 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3895 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 841 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4736 # number of ReadReq misses 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-system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9339 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9339 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.752802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869700 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.771210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.752802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -582,37 +606,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3895 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 841 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 4736 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index c0739097e..de709e95a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index d0b9d8c3b..dd174365b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.216828 # Nu sim_ticks 216828260500 # Number of ticks simulated final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175239 # Simulator instruction rate (inst/s) -host_op_rate 210394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139163086 # Simulator tick rate (ticks/s) -host_mem_usage 320864 # Number of bytes of host memory used -host_seconds 1558.09 # Real time elapsed on the host +host_inst_rate 113548 # Simulator instruction rate (inst/s) +host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90171945 # Simulator tick rate (ticks/s) +host_mem_usage 309844 # Number of bytes of host memory used +host_seconds 2404.61 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 485440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory system.physmem.bytes_read::total 485440 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 7585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2238823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2238823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7585 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 168783807 # To system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -402,61 +406,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 86714567 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 82047450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168762017 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168762017 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7290 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126489706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360451750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486941456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168769307 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168769307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -468,45 +472,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2870 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36927 # number of replacements @@ -603,9 +607,11 @@ system.cpu.l2cache.tags.sampled_refs 5647 # Sa system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -616,57 +622,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35746 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35746 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits system.cpu.l2cache.overall_hits::total 35746 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4776 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 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ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 521320250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 43376 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 43376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -676,43 +700,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 45 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 45 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index a21e90645..05b955543 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 896e43907..7bcf4595f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.559962 # Nu sim_ticks 559961514500 # Number of ticks simulated final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 343254 # Simulator instruction rate (inst/s) -host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206945650 # Simulator tick rate (ticks/s) -host_mem_usage 305268 # Number of bytes of host memory used -host_seconds 2705.84 # Real time elapsed on the host +host_inst_rate 216839 # Simulator instruction rate (inst/s) +host_op_rate 216839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130731039 # Simulator tick rate (ticks/s) +host_mem_usage 291560 # Number of bytes of host memory used +host_seconds 4283.31 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18657216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted @@ -331,8 +335,8 @@ system.cpu.dcache.tags.total_refs 323503178 # To system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id @@ -343,53 +347,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 225339131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 323503178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 323503178 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits system.cpu.dcache.overall_hits::total 323503178 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 711929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) 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WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -401,45 +405,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks system.cpu.dcache.writebacks::total 91489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 312 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) 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0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 11060cf95..7a6d5db32 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.541786 # Nu sim_ticks 541786101000 # Number of ticks simulated final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183531 # Simulator instruction rate (inst/s) -host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155207340 # Simulator tick rate (ticks/s) -host_mem_usage 320704 # Number of bytes of host memory used -host_seconds 3490.72 # Real time elapsed on the host +host_inst_rate 115987 # Simulator instruction rate (inst/s) +host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98087491 # Simulator tick rate (ticks/s) +host_mem_usage 309428 # Number of bytes of host memory used +host_seconds 5523.50 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted @@ -415,8 +419,8 @@ system.cpu.dcache.tags.total_refs 378457747 # To system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id @@ -427,61 +431,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 249632505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 128813764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 378446269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 378446269 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 379297729 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 379297729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -493,45 +497,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68391 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 69143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements @@ -626,9 +630,11 @@ system.cpu.l2cache.tags.sampled_refs 290493 # Sa system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id @@ -639,57 +645,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 513866 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 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number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) 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# miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -701,43 +725,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 32 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 32 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 1993a40dc..47efecce5 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.058585 # Nu sim_ticks 58584661500 # Number of ticks simulated final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 346754 # Simulator instruction rate (inst/s) -host_op_rate 346754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 229702503 # Simulator tick rate (ticks/s) -host_mem_usage 303900 # Number of bytes of host memory used -host_seconds 255.05 # Real time elapsed on the host +host_inst_rate 201524 # Simulator instruction rate (inst/s) +host_op_rate 201524 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133496887 # Simulator tick rate (ticks/s) +host_mem_usage 290684 # Number of bytes of host memory used +host_seconds 438.85 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10664384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182033722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 166631 # Number of read requests accepted system.physmem.writeReqs 114048 # Number of write requests accepted @@ -335,8 +339,8 @@ system.cpu.dcache.tags.total_refs 34616515 # To system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.523211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994024 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id @@ -345,53 +349,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20283193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34616515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34616515 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits system.cpu.dcache.overall_hits::total 34616515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89440 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369495 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses system.cpu.dcache.overall_misses::total 369495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4407640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 19996177500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24403818000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24403818000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 34986010 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34986010 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010561 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010561 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49280.417039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71400.894467 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66046.409288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -403,45 +407,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28125 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136498 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164623 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164623 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164623 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164623 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61315 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61315 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204872 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204872 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204872 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204872 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2422248250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2422248250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9931035500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9931035500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12353283750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12353283750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12353283750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12353283750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12353283750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005856 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39504.986545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39504.986545 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69178.343794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69178.343794 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60297.569946 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60297.569946 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 153786 # number of replacements @@ -537,9 +541,11 @@ system.cpu.l2cache.tags.sampled_refs 164780 # Sa system.cpu.l2cache.tags.avg_refs 1.339076 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26240.320965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4237.109970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2376.783596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1860.326375 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.800791 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056773 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.930097 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id @@ -550,57 +556,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4542362 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4542362 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 181399 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 147762 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 181399 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 168546 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168546 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12676 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12676 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12676 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 194075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 147762 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46313 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 194075 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 194075 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 147762 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46313 # number of overall hits system.cpu.l2cache.overall_hits::total 194075 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 35750 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 8073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27677 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 35750 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 130882 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 166632 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 8073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158559 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 166632 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 166632 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 8073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158559 # number of overall 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system.cpu.l2cache.Writeback_accesses::writebacks 168546 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143558 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143558 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143558 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 360707 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 155835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204872 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 360707 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 360707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 155835 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204872 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 360707 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.164634 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.051805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.451398 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.164634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911701 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911701 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911701 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461959 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.051805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773942 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.461959 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461959 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.051805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.461959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72831.601399 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71794.004707 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73134.254074 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73812.147583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73812.147583 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73812.147583 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 73601.776670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73601.776670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -612,37 +636,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks system.cpu.l2cache.writebacks::total 114048 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35750 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8073 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27677 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 35750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8073 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158559 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 166632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166632 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8073 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158559 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 166632 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2149088750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 478164000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1670924750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2149088750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7975554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975554000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975554000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10124642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 478164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9646478750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 10124642750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 478164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9646478750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.451398 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911701 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.461959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.461959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59230.026013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60372.321783 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60936.981403 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 72bc50e35..532524c0d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index e5a2f02e5..b9814d1e2 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.057816 # Nu sim_ticks 57815555000 # Number of ticks simulated final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199176 # Simulator instruction rate (inst/s) -host_op_rate 254717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162383906 # Simulator tick rate (ticks/s) -host_mem_usage 320240 # Number of bytes of host memory used -host_seconds 356.04 # Real time elapsed on the host +host_inst_rate 131971 # Simulator instruction rate (inst/s) +host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 107593052 # Simulator tick rate (ticks/s) +host_mem_usage 309228 # Number of bytes of host memory used +host_seconds 537.35 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 142657249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128872 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted @@ -419,8 +423,8 @@ system.cpu.dcache.tags.total_refs 42664902 # To system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id @@ -429,61 +433,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22989229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42633064 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42633064 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206066 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262131 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262131 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17343763437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42895195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42895195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -495,45 +499,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2577 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits 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53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160524 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160524 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1987609313 # number of ReadReq MSHR miss cycles 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system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42682 # number of replacements @@ -629,9 +633,11 @@ system.cpu.l2cache.tags.sampled_refs 126852 # Sa system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3229.441462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098555 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id @@ -642,57 +648,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 71548 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4755 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76303 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 76303 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits system.cpu.l2cache.overall_hits::total 76303 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26665 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # 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# number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107036 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 205249 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 44725 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160524 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 205249 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44725 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160524 # number of overall (read+write) accesses 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72890.908380 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was 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-system.cpu.l2cache.demand_mshr_misses::cpu.inst 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123802 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 298810000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1336295500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6164329000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 298810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7500624500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 298810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7500624500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402352 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955576 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 6bff9ac08..969dafec8 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index e7cd333d6..0dacf1436 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 1.199774 # Nu sim_ticks 1199774280000 # Number of ticks simulated final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 344306 # Simulator instruction rate (inst/s) -host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 226179780 # Simulator tick rate (ticks/s) -host_mem_usage 294788 # Number of bytes of host memory used -host_seconds 5304.52 # Real time elapsed on the host +host_inst_rate 216625 # Simulator instruction rate (inst/s) +host_op_rate 216625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 142303871 # Simulator tick rate (ticks/s) +host_mem_usage 282608 # Number of bytes of host memory used +host_seconds 8431.08 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted @@ -342,8 +346,8 @@ system.cpu.dcache.tags.total_refs 601828569 # To system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id @@ -353,53 +357,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits system.cpu.dcache.overall_hits::total 601828569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses system.cpu.dcache.overall_misses::total 9528336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -411,45 +415,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks system.cpu.dcache.writebacks::total 3700624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351432 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402243 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements @@ -543,9 +547,11 @@ system.cpu.l2cache.tags.sampled_refs 1958100 # Sa system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15804.919969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 43.293989 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15761.625979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482328 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001321 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.481007 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id @@ -556,57 +562,72 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15531 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106466843 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 106466843 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058136 # number of ReadReq hits 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system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887335 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126093 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses 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accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214859 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214777 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214777 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70652.502607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79828.761873 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80741.377895 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -618,37 +639,49 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180622 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779450 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960072 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960072 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55699750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79417889000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53122771000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55699750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132540660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55699750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132540660000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412990 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index cfff7eb6d..deabb9ce1 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1d6a1c5a9..1df40303a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 1.108725 # Nu sim_ticks 1108725388000 # Number of ticks simulated final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243193 # Simulator instruction rate (inst/s) -host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174570169 # Simulator tick rate (ticks/s) -host_mem_usage 311428 # Number of bytes of host memory used -host_seconds 6351.17 # Real time elapsed on the host +host_inst_rate 160331 # Simulator instruction rate (inst/s) +host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115089854 # Simulator tick rate (ticks/s) +host_mem_usage 301444 # Number of bytes of host memory used +host_seconds 9633.56 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 2055599 # Number of read requests accepted system.physmem.writeReqs 1046417 # Number of write requests accepted @@ -423,8 +427,8 @@ system.cpu.dcache.tags.total_refs 624087400 # To system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id @@ -434,61 +438,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -500,45 +504,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements @@ -633,9 +637,11 @@ system.cpu.l2cache.tags.sampled_refs 2052670 # Sa system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16254.854737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id @@ -646,57 +652,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6082213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090823 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7173036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7173036 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7173004 # number of overall hits system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255508 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 788 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1254720 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800096 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 800096 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2055604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2054816 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2055604 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100200408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64467346000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164667754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164667754000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55257250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337721 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7336901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890919 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890919 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9228640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9227820 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9228640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9227820 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423125 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423125 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222676 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222676 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79808.657531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80574.513558 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -708,43 +732,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks system.cpu.l2cache.writebacks::total 1046417 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index d573e8898..67aea2f65 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 3a5076b7f..ae03186ae 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.052167 # Nu sim_ticks 52167245000 # Number of ticks simulated final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 368966 # Simulator instruction rate (inst/s) -host_op_rate 368966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209437459 # Simulator tick rate (ticks/s) -host_mem_usage 299464 # Number of bytes of host memory used -host_seconds 249.08 # Real time elapsed on the host +host_inst_rate 211928 # Simulator instruction rate (inst/s) +host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120297341 # Simulator tick rate (ticks/s) +host_mem_usage 286252 # Number of bytes of host memory used +host_seconds 433.65 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 340352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory system.physmem.bytes_read::total 340352 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 5318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6524247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 26568138 # To system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -318,53 +322,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20069946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 26568138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26568138 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits system.cpu.dcache.overall_hits::total 26568138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of 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0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -376,45 +380,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 34 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1166 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1166 # number 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per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id @@ -524,57 +530,75 @@ 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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -584,37 +608,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 432 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 3599 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 168018c03..ca02b53f3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index b930735f4..fa4a217dd 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -82,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -122,6 +123,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -171,6 +173,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -220,6 +223,7 @@ eventq_index=0 type=LiveProcess cmd=twolf smred cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +drivers= egid=100 env= errout=cerr @@ -228,6 +232,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 75d7eb795..c2d632546 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.131746 # Nu sim_ticks 131745950000 # Number of ticks simulated final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246838 # Simulator instruction rate (inst/s) -host_op_rate 260207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188720644 # Simulator tick rate (ticks/s) -host_mem_usage 315756 # Number of bytes of host memory used -host_seconds 698.10 # Real time elapsed on the host +host_inst_rate 165378 # Simulator instruction rate (inst/s) +host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126440065 # Simulator tick rate (ticks/s) +host_mem_usage 304748 # Number of bytes of host memory used +host_seconds 1041.96 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3867 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 40762987 # To system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id @@ -402,61 +406,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 2436 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 2436 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115610250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 169622234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 40720609 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 40720609 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -468,45 +472,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 626 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 626 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq 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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2909 # number of replacements @@ -603,9 +607,11 @@ system.cpu.l2cache.tags.sampled_refs 2785 # Sa system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491287 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id @@ -616,57 +622,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 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ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ee9b56ccf..2a2f37965 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -102,6 +102,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -142,6 +143,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -232,6 +234,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -272,6 +275,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -403,6 +407,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -438,6 +443,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 3f9a7bd5f..22813f4db 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -102,6 +102,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -142,6 +143,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -191,6 +193,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -320,6 +323,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 8f2902a1b..9e0ef63d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=/work/gem5.latest/tests/halt.sh +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -98,6 +98,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -224,6 +226,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -264,6 +267,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -339,7 +343,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -362,7 +366,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -395,6 +399,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -430,6 +435,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -578,7 +584,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 39571b45c..3be47cc9f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=/work/gem5.latest/tests/halt.sh +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -98,6 +98,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -187,6 +189,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -260,7 +263,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -283,7 +286,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -316,6 +319,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -464,7 +468,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index aaf42338c..dfefc0ae8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -142,6 +142,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -218,6 +219,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -328,6 +330,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -349,19 +352,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -435,6 +446,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -511,6 +523,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -621,6 +634,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -642,19 +656,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -721,6 +743,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -756,6 +779,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index ce59aa175..214674a58 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -142,6 +142,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -218,6 +219,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -328,6 +330,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -411,6 +414,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index a40d111c2..ab3d1e239 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -214,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -324,6 +326,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -345,19 +348,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -427,6 +438,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -503,6 +515,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -613,6 +626,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -634,19 +648,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -713,6 +735,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -748,6 +771,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 0ae66cc7f..8649cd2a1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -214,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -324,6 +326,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -407,6 +410,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 72e487329..f413c6048 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -142,6 +142,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -218,6 +219,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -513,6 +515,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -548,6 +551,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 14e332c86..76a216752 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -142,6 +142,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -218,6 +219,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -328,6 +330,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -349,19 +352,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -435,6 +446,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -511,6 +523,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -621,6 +634,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -642,19 +656,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -721,6 +743,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -756,6 +779,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini index f85d9f074..eb15ee6f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -142,6 +142,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -218,6 +219,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -328,6 +330,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -411,6 +414,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index bc3129ffa..95d0c343b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -214,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -324,6 +326,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -345,19 +348,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -427,6 +438,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -503,6 +515,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -613,6 +626,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -634,19 +648,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -713,6 +735,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -748,6 +771,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index 0f90b5153..a676cb380 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -214,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -324,6 +326,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -407,6 +410,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr index 744db2c76..744db2c76 100644..100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 80ccc521c..180ce1eb4 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -188,6 +189,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -223,6 +225,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -289,6 +292,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -324,6 +328,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -826,6 +831,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1202,7 +1208,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1225,7 +1231,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 014efe16e..4721e8a2a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -134,6 +134,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -184,6 +185,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -219,6 +221,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -285,6 +288,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -320,6 +324,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -822,6 +827,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1198,7 +1204,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1221,7 +1227,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini index bbd960583..0f651c9f7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini @@ -130,6 +130,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -553,6 +554,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -602,6 +604,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -651,6 +654,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -659,6 +663,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -732,6 +737,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 954061e30..eedb7e6a0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.000035 # Nu sim_ticks 34993500 # Number of ticks simulated final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162128 # Simulator instruction rate (inst/s) -host_op_rate 162075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 885888965 # Simulator tick rate (ticks/s) -host_mem_usage 292456 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 25302 # Simulator instruction rate (inst/s) +host_op_rate 25300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 138325772 # Simulator tick rate (ticks/s) +host_mem_usage 279800 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory system.physmem.bytes_read::total 34112 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 1973 # To system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id @@ -315,53 +319,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits system.cpu.dcache.overall_hits::total 1973 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -371,45 +375,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 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number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for 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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements @@ -502,8 +506,10 @@ system.cpu.l2cache.tags.total_refs 1 # To system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of 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cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 67de80452..9165579c2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 091cdad96..8332a7a3a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -82,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -122,6 +123,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -171,6 +173,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -220,6 +223,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -228,6 +232,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index c9efff137..66098146a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -130,6 +130,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -553,6 +554,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -602,6 +604,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -651,6 +654,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -659,6 +663,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -732,6 +737,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 8eeabeb60..6a0f7583b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.000019 # Nu sim_ticks 18733500 # Number of ticks simulated final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81438 # Simulator instruction rate (inst/s) -host_op_rate 81405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 589715743 # Simulator tick rate (ticks/s) -host_mem_usage 292180 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 33056 # Simulator instruction rate (inst/s) +host_op_rate 33048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239448729 # Simulator tick rate (ticks/s) +host_mem_usage 278492 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 19712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1052232631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs 692 # To system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.478730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id @@ -315,53 +319,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 441 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 692 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 692 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 692 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 692 # number of overall hits system.cpu.dcache.overall_hits::total 692 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 104 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 104 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4644500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3502000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 8146500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 796 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 796 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.121514 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -371,45 +375,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 16 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements @@ -502,8 +506,10 @@ system.cpu.l2cache.tags.total_refs 0 # To system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.534478 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.615214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.919264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003620 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id @@ -511,45 +517,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 58 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 27 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 308 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6303750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20965250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6303750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -559,37 +580,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 308 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 5f42de628..19ac3530d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -551,6 +553,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -600,6 +603,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -608,6 +612,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +686,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index 300b9d035..c7a245793 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 58622e09f..452f74fef 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.000028 # Nu sim_ticks 27981000 # Number of ticks simulated final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95550 # Simulator instruction rate (inst/s) -host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 580422337 # Simulator tick rate (ticks/s) -host_mem_usage 309164 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 40383 # Simulator instruction rate (inst/s) +host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 245344554 # Simulator tick rate (ticks/s) +host_mem_usage 297404 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -389,8 +393,8 @@ system.cpu.dcache.tags.total_refs 1922 # To system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id @@ -398,61 +402,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits system.cpu.dcache.overall_hits::total 1900 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -462,45 +466,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements @@ -593,8 +597,10 @@ system.cpu.l2cache.tags.total_refs 39 # To system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id @@ -602,51 +608,69 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 81 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 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ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.786408 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -656,43 +680,55 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 41775f550..64e1a1f99 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -161,6 +161,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -518,6 +519,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -584,6 +586,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -633,6 +636,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -641,6 +645,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 144007094..8f525a009 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -155,6 +155,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -502,6 +503,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -552,6 +554,7 @@ eventq_index=0 type=LiveProcess cmd=test_atomic 4 cwd= +drivers= egid=100 env= errout=cerr @@ -560,6 +563,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -681,6 +685,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -1028,6 +1033,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -1186,6 +1192,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -1533,6 +1540,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -1691,6 +1699,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -2038,6 +2047,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -2106,6 +2116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -2183,6 +2194,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 |